Lines Matching +full:emc +full:- +full:timings +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
21 #include <soc/tegra/emc.h>
264 #define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD BIT(1)
269 #define DRAM_DEV_SEL_1 (1 << 30)
274 #define EMC_REFCTRL_DEV_SEL(n) (((n > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)
275 #define EMC_DRAM_DEV_SEL(n) ((n > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
282 DRAM_TYPE_DDR1 = 1,
476 struct emc_timing *timings; member
488 static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value, in emc_ccfifo_writel() argument
491 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()
492 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()
495 static void emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument
500 writel(1, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
503 value = readl(emc->regs + EMC_STATUS); in emc_seq_update_timing()
506 udelay(1); in emc_seq_update_timing()
509 dev_err(emc->dev, "timing update timed out\n"); in emc_seq_update_timing()
512 static void emc_seq_disable_auto_cal(struct tegra_emc *emc) in emc_seq_disable_auto_cal() argument
517 writel(0, emc->regs + EMC_AUTO_CAL_INTERVAL); in emc_seq_disable_auto_cal()
520 value = readl(emc->regs + EMC_AUTO_CAL_STATUS); in emc_seq_disable_auto_cal()
523 udelay(1); in emc_seq_disable_auto_cal()
526 dev_err(emc->dev, "auto cal disable timed out\n"); in emc_seq_disable_auto_cal()
529 static void emc_seq_wait_clkchange(struct tegra_emc *emc) in emc_seq_wait_clkchange() argument
535 value = readl(emc->regs + EMC_INTSTATUS); in emc_seq_wait_clkchange()
538 udelay(1); in emc_seq_wait_clkchange()
541 dev_err(emc->dev, "clock change timed out\n"); in emc_seq_wait_clkchange()
544 static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc, in tegra_emc_find_timing() argument
550 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_find_timing()
551 if (emc->timings[i].rate == rate) { in tegra_emc_find_timing()
552 timing = &emc->timings[i]; in tegra_emc_find_timing()
558 dev_err(emc->dev, "no timing for rate %lu\n", rate); in tegra_emc_find_timing()
565 int tegra_emc_prepare_timing_change(struct tegra_emc *emc, in tegra_emc_prepare_timing_change() argument
568 struct emc_timing *timing = tegra_emc_find_timing(emc, rate); in tegra_emc_prepare_timing_change()
569 struct emc_timing *last = &emc->last_timing; in tegra_emc_prepare_timing_change()
577 return -ENOENT; in tegra_emc_prepare_timing_change()
579 if ((last->emc_mode_1 & 0x1) == (timing->emc_mode_1 & 0x1)) in tegra_emc_prepare_timing_change()
581 else if (timing->emc_mode_1 & 0x1) in tegra_emc_prepare_timing_change()
587 writel(EMC_INTSTATUS_CLKCHANGE_COMPLETE, emc->regs + EMC_INTSTATUS); in tegra_emc_prepare_timing_change()
589 /* Disable dynamic self-refresh */ in tegra_emc_prepare_timing_change()
590 val = readl(emc->regs + EMC_CFG); in tegra_emc_prepare_timing_change()
593 writel(val, emc->regs + EMC_CFG); in tegra_emc_prepare_timing_change()
599 if (emc->dram_type == DRAM_TYPE_DDR3) in tegra_emc_prepare_timing_change()
604 val = readl(emc->regs + EMC_SEL_DPD_CTRL); in tegra_emc_prepare_timing_change()
607 writel(val, emc->regs + EMC_SEL_DPD_CTRL); in tegra_emc_prepare_timing_change()
611 val = readl(emc->regs + EMC_BGBIAS_CTL0); in tegra_emc_prepare_timing_change()
612 val2 = last->emc_bgbias_ctl0; in tegra_emc_prepare_timing_change()
613 if (!(timing->emc_bgbias_ctl0 & in tegra_emc_prepare_timing_change()
626 writel(val2, emc->regs + EMC_BGBIAS_CTL0); in tegra_emc_prepare_timing_change()
632 val = readl(emc->regs + EMC_XM2DQSPADCTRL2); in tegra_emc_prepare_timing_change()
633 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_VREF_ENABLE && in tegra_emc_prepare_timing_change()
639 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE && in tegra_emc_prepare_timing_change()
646 writel(val, emc->regs + EMC_XM2DQSPADCTRL2); in tegra_emc_prepare_timing_change()
653 emc_seq_update_timing(emc); in tegra_emc_prepare_timing_change()
658 if (last->emc_ctt_term_ctrl != timing->emc_ctt_term_ctrl) { in tegra_emc_prepare_timing_change()
659 emc_seq_disable_auto_cal(emc); in tegra_emc_prepare_timing_change()
660 writel(timing->emc_ctt_term_ctrl, in tegra_emc_prepare_timing_change()
661 emc->regs + EMC_CTT_TERM_CTRL); in tegra_emc_prepare_timing_change()
662 emc_seq_update_timing(emc); in tegra_emc_prepare_timing_change()
666 for (i = 0; i < ARRAY_SIZE(timing->emc_burst_data); ++i) in tegra_emc_prepare_timing_change()
667 writel(timing->emc_burst_data[i], in tegra_emc_prepare_timing_change()
668 emc->regs + emc_burst_regs[i]); in tegra_emc_prepare_timing_change()
670 writel(timing->emc_xm2dqspadctrl2, emc->regs + EMC_XM2DQSPADCTRL2); in tegra_emc_prepare_timing_change()
671 writel(timing->emc_zcal_interval, emc->regs + EMC_ZCAL_INTERVAL); in tegra_emc_prepare_timing_change()
673 tegra_mc_write_emem_configuration(emc->mc, timing->rate); in tegra_emc_prepare_timing_change()
675 val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK; in tegra_emc_prepare_timing_change()
676 emc_ccfifo_writel(emc, val, EMC_CFG); in tegra_emc_prepare_timing_change()
679 if (timing->emc_auto_cal_config2 != last->emc_auto_cal_config2) in tegra_emc_prepare_timing_change()
680 emc_ccfifo_writel(emc, timing->emc_auto_cal_config2, in tegra_emc_prepare_timing_change()
683 if (timing->emc_auto_cal_config3 != last->emc_auto_cal_config3) in tegra_emc_prepare_timing_change()
684 emc_ccfifo_writel(emc, timing->emc_auto_cal_config3, in tegra_emc_prepare_timing_change()
687 if (timing->emc_auto_cal_config != last->emc_auto_cal_config) { in tegra_emc_prepare_timing_change()
688 val = timing->emc_auto_cal_config; in tegra_emc_prepare_timing_change()
690 emc_ccfifo_writel(emc, val, EMC_AUTO_CAL_CONFIG); in tegra_emc_prepare_timing_change()
694 if (emc->dram_type == DRAM_TYPE_DDR3 && in tegra_emc_prepare_timing_change()
698 if (timing->emc_zcal_interval != 0 && in tegra_emc_prepare_timing_change()
699 last->emc_zcal_interval == 0) in tegra_emc_prepare_timing_change()
700 cnt -= emc->dram_num * 256; in tegra_emc_prepare_timing_change()
702 val = (timing->emc_mrs_wait_cnt in tegra_emc_prepare_timing_change()
708 val = timing->emc_mrs_wait_cnt in tegra_emc_prepare_timing_change()
713 writel(val, emc->regs + EMC_MRS_WAIT_CNT); in tegra_emc_prepare_timing_change()
716 val = timing->emc_cfg_2; in tegra_emc_prepare_timing_change()
718 emc_ccfifo_writel(emc, val, EMC_CFG_2); in tegra_emc_prepare_timing_change()
720 /* DDR3: Turn off DLL and enter self-refresh */ in tegra_emc_prepare_timing_change()
721 if (emc->dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_OFF) in tegra_emc_prepare_timing_change()
722 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS); in tegra_emc_prepare_timing_change()
725 emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num), in tegra_emc_prepare_timing_change()
727 if (emc->dram_type == DRAM_TYPE_DDR3) in tegra_emc_prepare_timing_change()
728 emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num) | in tegra_emc_prepare_timing_change()
733 emc_ccfifo_writel(emc, 1, EMC_STALL_THEN_EXE_AFTER_CLKCHANGE); in tegra_emc_prepare_timing_change()
735 /* DDR3: Exit self-refresh */ in tegra_emc_prepare_timing_change()
736 if (emc->dram_type == DRAM_TYPE_DDR3) in tegra_emc_prepare_timing_change()
737 emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num), in tegra_emc_prepare_timing_change()
739 emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num) | in tegra_emc_prepare_timing_change()
744 if (emc->dram_type == DRAM_TYPE_DDR3) { in tegra_emc_prepare_timing_change()
745 if (timing->emc_mode_1 != last->emc_mode_1) in tegra_emc_prepare_timing_change()
746 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS); in tegra_emc_prepare_timing_change()
747 if (timing->emc_mode_2 != last->emc_mode_2) in tegra_emc_prepare_timing_change()
748 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_EMRS2); in tegra_emc_prepare_timing_change()
750 if ((timing->emc_mode_reset != last->emc_mode_reset) || in tegra_emc_prepare_timing_change()
752 val = timing->emc_mode_reset; in tegra_emc_prepare_timing_change()
759 emc_ccfifo_writel(emc, val, EMC_MRS); in tegra_emc_prepare_timing_change()
762 if (timing->emc_mode_2 != last->emc_mode_2) in tegra_emc_prepare_timing_change()
763 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_MRW2); in tegra_emc_prepare_timing_change()
764 if (timing->emc_mode_1 != last->emc_mode_1) in tegra_emc_prepare_timing_change()
765 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_MRW); in tegra_emc_prepare_timing_change()
766 if (timing->emc_mode_4 != last->emc_mode_4) in tegra_emc_prepare_timing_change()
767 emc_ccfifo_writel(emc, timing->emc_mode_4, EMC_MRW4); in tegra_emc_prepare_timing_change()
771 if (timing->emc_zcal_interval != 0 && last->emc_zcal_interval == 0) { in tegra_emc_prepare_timing_change()
772 emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV0, EMC_ZQ_CAL); in tegra_emc_prepare_timing_change()
773 if (emc->dram_num > 1) in tegra_emc_prepare_timing_change()
774 emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV1, in tegra_emc_prepare_timing_change()
779 emc_ccfifo_writel(emc, 0, EMC_CCFIFO_STATUS); in tegra_emc_prepare_timing_change()
781 if (timing->emc_cfg_2 & EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR) in tegra_emc_prepare_timing_change()
782 emc_ccfifo_writel(emc, timing->emc_cfg_2, EMC_CFG_2); in tegra_emc_prepare_timing_change()
785 emc_seq_disable_auto_cal(emc); in tegra_emc_prepare_timing_change()
788 readl(emc->regs + EMC_INTSTATUS); in tegra_emc_prepare_timing_change()
793 void tegra_emc_complete_timing_change(struct tegra_emc *emc, in tegra_emc_complete_timing_change() argument
796 struct emc_timing *timing = tegra_emc_find_timing(emc, rate); in tegra_emc_complete_timing_change()
797 struct emc_timing *last = &emc->last_timing; in tegra_emc_complete_timing_change()
804 emc_seq_wait_clkchange(emc); in tegra_emc_complete_timing_change()
807 if (timing->emc_ctt_term_ctrl != last->emc_ctt_term_ctrl) in tegra_emc_complete_timing_change()
808 writel(timing->emc_auto_cal_interval, in tegra_emc_complete_timing_change()
809 emc->regs + EMC_AUTO_CAL_INTERVAL); in tegra_emc_complete_timing_change()
811 /* Restore dynamic self-refresh */ in tegra_emc_complete_timing_change()
812 if (timing->emc_cfg & EMC_CFG_PWR_MASK) in tegra_emc_complete_timing_change()
813 writel(timing->emc_cfg, emc->regs + EMC_CFG); in tegra_emc_complete_timing_change()
816 writel(timing->emc_zcal_cnt_long, emc->regs + EMC_ZCAL_WAIT_CNT); in tegra_emc_complete_timing_change()
819 if (emc->dram_type == DRAM_TYPE_LPDDR3 && in tegra_emc_complete_timing_change()
820 timing->emc_bgbias_ctl0 & in tegra_emc_complete_timing_change()
822 val = timing->emc_bgbias_ctl0; in tegra_emc_complete_timing_change()
825 writel(val, emc->regs + EMC_BGBIAS_CTL0); in tegra_emc_complete_timing_change()
827 if (emc->dram_type == DRAM_TYPE_DDR3 && in tegra_emc_complete_timing_change()
828 readl(emc->regs + EMC_BGBIAS_CTL0) != in tegra_emc_complete_timing_change()
829 timing->emc_bgbias_ctl0) { in tegra_emc_complete_timing_change()
830 writel(timing->emc_bgbias_ctl0, in tegra_emc_complete_timing_change()
831 emc->regs + EMC_BGBIAS_CTL0); in tegra_emc_complete_timing_change()
834 writel(timing->emc_auto_cal_interval, in tegra_emc_complete_timing_change()
835 emc->regs + EMC_AUTO_CAL_INTERVAL); in tegra_emc_complete_timing_change()
842 writel(timing->emc_sel_dpd_ctrl, emc->regs + EMC_SEL_DPD_CTRL); in tegra_emc_complete_timing_change()
843 emc_seq_update_timing(emc); in tegra_emc_complete_timing_change()
845 emc->last_timing = *timing; in tegra_emc_complete_timing_change()
850 static void emc_read_current_timing(struct tegra_emc *emc, in emc_read_current_timing() argument
856 timing->emc_burst_data[i] = in emc_read_current_timing()
857 readl(emc->regs + emc_burst_regs[i]); in emc_read_current_timing()
859 timing->emc_cfg = readl(emc->regs + EMC_CFG); in emc_read_current_timing()
861 timing->emc_auto_cal_interval = 0; in emc_read_current_timing()
862 timing->emc_zcal_cnt_long = 0; in emc_read_current_timing()
863 timing->emc_mode_1 = 0; in emc_read_current_timing()
864 timing->emc_mode_2 = 0; in emc_read_current_timing()
865 timing->emc_mode_4 = 0; in emc_read_current_timing()
866 timing->emc_mode_reset = 0; in emc_read_current_timing()
869 static int emc_init(struct tegra_emc *emc) in emc_init() argument
871 emc->dram_type = readl(emc->regs + EMC_FBIO_CFG5); in emc_init()
872 emc->dram_type &= EMC_FBIO_CFG5_DRAM_TYPE_MASK; in emc_init()
873 emc->dram_type >>= EMC_FBIO_CFG5_DRAM_TYPE_SHIFT; in emc_init()
875 emc->dram_num = tegra_mc_get_emem_device_count(emc->mc); in emc_init()
877 emc_read_current_timing(emc, &emc->last_timing); in emc_init()
882 static int load_one_timing_from_dt(struct tegra_emc *emc, in load_one_timing_from_dt() argument
889 err = of_property_read_u32(node, "clock-frequency", &value); in load_one_timing_from_dt()
891 dev_err(emc->dev, "timing %pOFn: failed to read rate: %d\n", in load_one_timing_from_dt()
896 timing->rate = value; in load_one_timing_from_dt()
898 err = of_property_read_u32_array(node, "nvidia,emc-configuration", in load_one_timing_from_dt()
899 timing->emc_burst_data, in load_one_timing_from_dt()
900 ARRAY_SIZE(timing->emc_burst_data)); in load_one_timing_from_dt()
902 dev_err(emc->dev, in load_one_timing_from_dt()
903 "timing %pOFn: failed to read emc burst data: %d\n", in load_one_timing_from_dt()
909 err = of_property_read_u32(node, dtprop, &timing->prop); \ in load_one_timing_from_dt()
911 dev_err(emc->dev, "timing %pOFn: failed to read " #prop ": %d\n", \ in load_one_timing_from_dt()
917 EMC_READ_PROP(emc_auto_cal_config, "nvidia,emc-auto-cal-config") in load_one_timing_from_dt()
918 EMC_READ_PROP(emc_auto_cal_config2, "nvidia,emc-auto-cal-config2") in load_one_timing_from_dt()
919 EMC_READ_PROP(emc_auto_cal_config3, "nvidia,emc-auto-cal-config3") in load_one_timing_from_dt()
920 EMC_READ_PROP(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval") in load_one_timing_from_dt()
921 EMC_READ_PROP(emc_bgbias_ctl0, "nvidia,emc-bgbias-ctl0") in load_one_timing_from_dt()
922 EMC_READ_PROP(emc_cfg, "nvidia,emc-cfg") in load_one_timing_from_dt()
923 EMC_READ_PROP(emc_cfg_2, "nvidia,emc-cfg-2") in load_one_timing_from_dt()
924 EMC_READ_PROP(emc_ctt_term_ctrl, "nvidia,emc-ctt-term-ctrl") in load_one_timing_from_dt()
925 EMC_READ_PROP(emc_mode_1, "nvidia,emc-mode-1") in load_one_timing_from_dt()
926 EMC_READ_PROP(emc_mode_2, "nvidia,emc-mode-2") in load_one_timing_from_dt()
927 EMC_READ_PROP(emc_mode_4, "nvidia,emc-mode-4") in load_one_timing_from_dt()
928 EMC_READ_PROP(emc_mode_reset, "nvidia,emc-mode-reset") in load_one_timing_from_dt()
929 EMC_READ_PROP(emc_mrs_wait_cnt, "nvidia,emc-mrs-wait-cnt") in load_one_timing_from_dt()
930 EMC_READ_PROP(emc_sel_dpd_ctrl, "nvidia,emc-sel-dpd-ctrl") in load_one_timing_from_dt()
931 EMC_READ_PROP(emc_xm2dqspadctrl2, "nvidia,emc-xm2dqspadctrl2") in load_one_timing_from_dt()
932 EMC_READ_PROP(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long") in load_one_timing_from_dt()
933 EMC_READ_PROP(emc_zcal_interval, "nvidia,emc-zcal-interval") in load_one_timing_from_dt()
945 if (a->rate < b->rate) in cmp_timings()
946 return -1; in cmp_timings()
947 else if (a->rate == b->rate) in cmp_timings()
950 return 1; in cmp_timings()
953 static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc, in tegra_emc_load_timings_from_dt() argument
962 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing), in tegra_emc_load_timings_from_dt()
964 if (!emc->timings) in tegra_emc_load_timings_from_dt()
965 return -ENOMEM; in tegra_emc_load_timings_from_dt()
967 emc->num_timings = child_count; in tegra_emc_load_timings_from_dt()
970 timing = &emc->timings[i++]; in tegra_emc_load_timings_from_dt()
972 err = load_one_timing_from_dt(emc, timing, child); in tegra_emc_load_timings_from_dt()
979 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, in tegra_emc_load_timings_from_dt()
986 { .compatible = "nvidia,tegra124-emc" },
987 { .compatible = "nvidia,tegra132-emc" },
1000 err = of_property_read_u32(np, "nvidia,ram-code", &value); in tegra_emc_find_node_by_ram_code()
1014 * to control the EMC frequency. The top-level directory can be found here:
1016 * /sys/kernel/debug/emc
1020 * - available_rates: This file contains a list of valid, space-separated
1021 * EMC frequencies.
1023 * - min_rate: Writing a value to this file sets the given frequency as the
1025 * configured EMC frequency, this will cause the frequency to be
1028 * - max_rate: Similarily to the min_rate file, writing a value to this file
1030 * the value is lower than the currently configured EMC frequency, this
1035 static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate) in tegra_emc_validate_rate() argument
1039 for (i = 0; i < emc->num_timings; i++) in tegra_emc_validate_rate()
1040 if (rate == emc->timings[i].rate) in tegra_emc_validate_rate()
1049 struct tegra_emc *emc = s->private; in tegra_emc_debug_available_rates_show() local
1053 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_debug_available_rates_show()
1054 seq_printf(s, "%s%lu", prefix, emc->timings[i].rate); in tegra_emc_debug_available_rates_show()
1067 struct tegra_emc *emc = data; in tegra_emc_debug_min_rate_get() local
1069 *rate = emc->debugfs.min_rate; in tegra_emc_debug_min_rate_get()
1076 struct tegra_emc *emc = data; in tegra_emc_debug_min_rate_set() local
1079 if (!tegra_emc_validate_rate(emc, rate)) in tegra_emc_debug_min_rate_set()
1080 return -EINVAL; in tegra_emc_debug_min_rate_set()
1082 err = clk_set_min_rate(emc->clk, rate); in tegra_emc_debug_min_rate_set()
1086 emc->debugfs.min_rate = rate; in tegra_emc_debug_min_rate_set()
1097 struct tegra_emc *emc = data; in tegra_emc_debug_max_rate_get() local
1099 *rate = emc->debugfs.max_rate; in tegra_emc_debug_max_rate_get()
1106 struct tegra_emc *emc = data; in tegra_emc_debug_max_rate_set() local
1109 if (!tegra_emc_validate_rate(emc, rate)) in tegra_emc_debug_max_rate_set()
1110 return -EINVAL; in tegra_emc_debug_max_rate_set()
1112 err = clk_set_max_rate(emc->clk, rate); in tegra_emc_debug_max_rate_set()
1116 emc->debugfs.max_rate = rate; in tegra_emc_debug_max_rate_set()
1125 static void emc_debugfs_init(struct device *dev, struct tegra_emc *emc) in emc_debugfs_init() argument
1130 emc->clk = devm_clk_get(dev, "emc"); in emc_debugfs_init()
1131 if (IS_ERR(emc->clk)) { in emc_debugfs_init()
1132 if (PTR_ERR(emc->clk) != -ENODEV) { in emc_debugfs_init()
1133 dev_err(dev, "failed to get EMC clock: %ld\n", in emc_debugfs_init()
1134 PTR_ERR(emc->clk)); in emc_debugfs_init()
1139 emc->debugfs.min_rate = ULONG_MAX; in emc_debugfs_init()
1140 emc->debugfs.max_rate = 0; in emc_debugfs_init()
1142 for (i = 0; i < emc->num_timings; i++) { in emc_debugfs_init()
1143 if (emc->timings[i].rate < emc->debugfs.min_rate) in emc_debugfs_init()
1144 emc->debugfs.min_rate = emc->timings[i].rate; in emc_debugfs_init()
1146 if (emc->timings[i].rate > emc->debugfs.max_rate) in emc_debugfs_init()
1147 emc->debugfs.max_rate = emc->timings[i].rate; in emc_debugfs_init()
1150 if (!emc->num_timings) { in emc_debugfs_init()
1151 emc->debugfs.min_rate = clk_get_rate(emc->clk); in emc_debugfs_init()
1152 emc->debugfs.max_rate = emc->debugfs.min_rate; in emc_debugfs_init()
1155 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, in emc_debugfs_init()
1156 emc->debugfs.max_rate); in emc_debugfs_init()
1158 dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n", in emc_debugfs_init()
1159 emc->debugfs.min_rate, emc->debugfs.max_rate, in emc_debugfs_init()
1160 emc->clk); in emc_debugfs_init()
1164 emc->debugfs.root = debugfs_create_dir("emc", NULL); in emc_debugfs_init()
1165 if (!emc->debugfs.root) { in emc_debugfs_init()
1170 debugfs_create_file("available_rates", 0444, emc->debugfs.root, emc, in emc_debugfs_init()
1172 debugfs_create_file("min_rate", 0644, emc->debugfs.root, in emc_debugfs_init()
1173 emc, &tegra_emc_debug_min_rate_fops); in emc_debugfs_init()
1174 debugfs_create_file("max_rate", 0644, emc->debugfs.root, in emc_debugfs_init()
1175 emc, &tegra_emc_debug_max_rate_fops); in emc_debugfs_init()
1182 struct tegra_emc *emc; in tegra_emc_probe() local
1187 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); in tegra_emc_probe()
1188 if (!emc) in tegra_emc_probe()
1189 return -ENOMEM; in tegra_emc_probe()
1191 emc->dev = &pdev->dev; in tegra_emc_probe()
1194 emc->regs = devm_ioremap_resource(&pdev->dev, res); in tegra_emc_probe()
1195 if (IS_ERR(emc->regs)) in tegra_emc_probe()
1196 return PTR_ERR(emc->regs); in tegra_emc_probe()
1198 np = of_parse_phandle(pdev->dev.of_node, "nvidia,memory-controller", 0); in tegra_emc_probe()
1200 dev_err(&pdev->dev, "could not get memory controller\n"); in tegra_emc_probe()
1201 return -ENOENT; in tegra_emc_probe()
1207 return -ENOENT; in tegra_emc_probe()
1209 emc->mc = platform_get_drvdata(mc); in tegra_emc_probe()
1210 if (!emc->mc) in tegra_emc_probe()
1211 return -EPROBE_DEFER; in tegra_emc_probe()
1215 np = tegra_emc_find_node_by_ram_code(pdev->dev.of_node, ram_code); in tegra_emc_probe()
1217 dev_err(&pdev->dev, in tegra_emc_probe()
1218 "no memory timings for RAM code %u found in DT\n", in tegra_emc_probe()
1220 return -ENOENT; in tegra_emc_probe()
1223 err = tegra_emc_load_timings_from_dt(emc, np); in tegra_emc_probe()
1228 if (emc->num_timings == 0) { in tegra_emc_probe()
1229 dev_err(&pdev->dev, in tegra_emc_probe()
1230 "no memory timings for RAM code %u registered\n", in tegra_emc_probe()
1232 return -ENOENT; in tegra_emc_probe()
1235 err = emc_init(emc); in tegra_emc_probe()
1237 dev_err(&pdev->dev, "EMC initialization failed: %d\n", err); in tegra_emc_probe()
1241 platform_set_drvdata(pdev, emc); in tegra_emc_probe()
1244 emc_debugfs_init(&pdev->dev, emc); in tegra_emc_probe()
1252 .name = "tegra-emc",