Lines Matching +full:switching +full:- +full:freq
1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/devfreq-event.h>
100 * struct dmc_opp_table - Operating level desciption
112 * struct exynos5_dmc - main structure describing DMC device
195 __val = (t_val) << (timing)->bit_beg; \
219 TIMING_FIELD("tW2W-C2C", 14, 14),
220 TIMING_FIELD("tR2R-C2C", 12, 12),
242 for (i = 0; i < dmc->num_counters; i++) { in exynos5_counters_set_event()
243 if (!dmc->counter[i]) in exynos5_counters_set_event()
245 ret = devfreq_event_set_event(dmc->counter[i]); in exynos5_counters_set_event()
256 for (i = 0; i < dmc->num_counters; i++) { in exynos5_counters_enable_edev()
257 if (!dmc->counter[i]) in exynos5_counters_enable_edev()
259 ret = devfreq_event_enable_edev(dmc->counter[i]); in exynos5_counters_enable_edev()
270 for (i = 0; i < dmc->num_counters; i++) { in exynos5_counters_disable_edev()
271 if (!dmc->counter[i]) in exynos5_counters_disable_edev()
273 ret = devfreq_event_disable_edev(dmc->counter[i]); in exynos5_counters_disable_edev()
281 * find_target_freq_id() - Finds requested frequency in local DMC configuration
293 for (i = dmc->opp_count - 1; i >= 0; i--) in find_target_freq_idx()
294 if (dmc->opp[i].freq_hz <= target_rate) in find_target_freq_idx()
297 return -EINVAL; in find_target_freq_idx()
301 * exynos5_switch_timing_regs() - Changes bank register set for DRAM timings
318 ret = regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, ®); in exynos5_switch_timing_regs()
327 regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, reg); in exynos5_switch_timing_regs()
333 * exynos5_init_freq_table() - Initialized PM OPP framework
344 unsigned long freq; in exynos5_init_freq_table() local
346 ret = dev_pm_opp_of_add_table(dmc->dev); in exynos5_init_freq_table()
348 dev_err(dmc->dev, "Failed to get OPP table\n"); in exynos5_init_freq_table()
352 dmc->opp_count = dev_pm_opp_get_opp_count(dmc->dev); in exynos5_init_freq_table()
354 dmc->opp = devm_kmalloc_array(dmc->dev, dmc->opp_count, in exynos5_init_freq_table()
356 if (!dmc->opp) in exynos5_init_freq_table()
359 idx = dmc->opp_count - 1; in exynos5_init_freq_table()
360 for (i = 0, freq = ULONG_MAX; i < dmc->opp_count; i++, freq--) { in exynos5_init_freq_table()
363 opp = dev_pm_opp_find_freq_floor(dmc->dev, &freq); in exynos5_init_freq_table()
367 dmc->opp[idx - i].freq_hz = freq; in exynos5_init_freq_table()
368 dmc->opp[idx - i].volt_uv = dev_pm_opp_get_voltage(opp); in exynos5_init_freq_table()
376 dev_pm_opp_of_remove_table(dmc->dev); in exynos5_init_freq_table()
378 return -EINVAL; in exynos5_init_freq_table()
382 * exynos5_set_bypass_dram_timings() - Low-level changes of the DRAM timings
385 * Low-level function for changing timings for DRAM memory clocking from
392 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF); in exynos5_set_bypass_dram_timings()
394 writel(dmc->bypass_timing_row, in exynos5_set_bypass_dram_timings()
395 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW1); in exynos5_set_bypass_dram_timings()
396 writel(dmc->bypass_timing_row, in exynos5_set_bypass_dram_timings()
397 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW1); in exynos5_set_bypass_dram_timings()
398 writel(dmc->bypass_timing_data, in exynos5_set_bypass_dram_timings()
399 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA1); in exynos5_set_bypass_dram_timings()
400 writel(dmc->bypass_timing_data, in exynos5_set_bypass_dram_timings()
401 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA1); in exynos5_set_bypass_dram_timings()
402 writel(dmc->bypass_timing_power, in exynos5_set_bypass_dram_timings()
403 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER1); in exynos5_set_bypass_dram_timings()
404 writel(dmc->bypass_timing_power, in exynos5_set_bypass_dram_timings()
405 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER1); in exynos5_set_bypass_dram_timings()
409 * exynos5_dram_change_timings() - Low-level changes of the DRAM final timings
413 * Low-level function for changing timings for DRAM memory operating from main
424 for (idx = dmc->opp_count - 1; idx >= 0; idx--) in exynos5_dram_change_timings()
425 if (dmc->opp[idx].freq_hz <= target_rate) in exynos5_dram_change_timings()
429 return -EINVAL; in exynos5_dram_change_timings()
432 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF); in exynos5_dram_change_timings()
434 writel(dmc->timing_row[idx], in exynos5_dram_change_timings()
435 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW0); in exynos5_dram_change_timings()
436 writel(dmc->timing_row[idx], in exynos5_dram_change_timings()
437 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW0); in exynos5_dram_change_timings()
438 writel(dmc->timing_data[idx], in exynos5_dram_change_timings()
439 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA0); in exynos5_dram_change_timings()
440 writel(dmc->timing_data[idx], in exynos5_dram_change_timings()
441 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA0); in exynos5_dram_change_timings()
442 writel(dmc->timing_power[idx], in exynos5_dram_change_timings()
443 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER0); in exynos5_dram_change_timings()
444 writel(dmc->timing_power[idx], in exynos5_dram_change_timings()
445 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER0); in exynos5_dram_change_timings()
451 * exynos5_dmc_align_target_voltage() - Sets the final voltage for the DMC
465 if (dmc->curr_volt <= target_volt) in exynos5_dmc_align_target_voltage()
468 ret = regulator_set_voltage(dmc->vdd_mif, target_volt, in exynos5_dmc_align_target_voltage()
471 dmc->curr_volt = target_volt; in exynos5_dmc_align_target_voltage()
477 * exynos5_dmc_align_bypass_voltage() - Sets the voltage for the DMC
491 if (dmc->curr_volt >= target_volt) in exynos5_dmc_align_bypass_voltage()
494 ret = regulator_set_voltage(dmc->vdd_mif, target_volt, in exynos5_dmc_align_bypass_voltage()
497 dmc->curr_volt = target_volt; in exynos5_dmc_align_bypass_voltage()
503 * exynos5_dmc_align_bypass_dram_timings() - Chooses and sets DRAM timings
515 return -EINVAL; in exynos5_dmc_align_bypass_dram_timings()
523 * exynos5_dmc_switch_to_bypass_configuration() - Switching to temporary clock
524 * @dmc: DMC device for which the switching is going to happen
565 * exynos5_dmc_change_freq_and_volt() - Changes voltage and frequency of the DMC
577 * T-period. There is two bank sets for keeping DRAM
579 * chosen. The 2nd set of regs is used for 'bypass' clock. Switching between
582 * this intermediate step with switching to 'bypass' parent clock source.
601 * so switching clock source is safe now. in exynos5_dmc_change_freq_and_volt()
603 clk_prepare_enable(dmc->fout_spll); in exynos5_dmc_change_freq_and_volt()
604 clk_prepare_enable(dmc->mout_spll); in exynos5_dmc_change_freq_and_volt()
605 clk_prepare_enable(dmc->mout_mx_mspll_ccore); in exynos5_dmc_change_freq_and_volt()
607 ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_mx_mspll_ccore); in exynos5_dmc_change_freq_and_volt()
618 clk_set_rate(dmc->fout_bpll, target_rate); in exynos5_dmc_change_freq_and_volt()
624 ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_bpll); in exynos5_dmc_change_freq_and_volt()
635 clk_disable_unprepare(dmc->mout_mx_mspll_ccore); in exynos5_dmc_change_freq_and_volt()
636 clk_disable_unprepare(dmc->mout_spll); in exynos5_dmc_change_freq_and_volt()
637 clk_disable_unprepare(dmc->fout_spll); in exynos5_dmc_change_freq_and_volt()
643 * exynos5_dmc_get_volt_freq() - Gets the frequency and voltage from the OPP
646 * @freq: requested frequency in KHz
658 unsigned long *freq, in exynos5_dmc_get_volt_freq() argument
664 opp = devfreq_recommended_opp(dmc->dev, freq, flags); in exynos5_dmc_get_volt_freq()
676 * exynos5_dmc_target() - Function responsible for changing frequency of DMC
678 * @freq: requested frequency in KHz
687 static int exynos5_dmc_target(struct device *dev, unsigned long *freq, in exynos5_dmc_target() argument
695 ret = exynos5_dmc_get_volt_freq(dmc, freq, &target_rate, &target_volt, in exynos5_dmc_target()
701 if (target_rate == dmc->curr_rate) in exynos5_dmc_target()
704 mutex_lock(&dmc->lock); in exynos5_dmc_target()
709 mutex_unlock(&dmc->lock); in exynos5_dmc_target()
713 dmc->curr_rate = target_rate; in exynos5_dmc_target()
715 mutex_unlock(&dmc->lock); in exynos5_dmc_target()
720 * exynos5_counters_get() - Gets the performance counters values.
740 for (i = 0; i < dmc->num_counters; i++) { in exynos5_counters_get()
741 if (!dmc->counter[i]) in exynos5_counters_get()
744 ret = devfreq_event_get_event(dmc->counter[i], &event); in exynos5_counters_get()
760 * exynos5_dmc_start_perf_events() - Setup and start performance event counters
771 writel(PERF_CNT2, dmc->base_drexi0 + DREX_INTENS_PPC); in exynos5_dmc_start_perf_events()
772 writel(PERF_CNT2, dmc->base_drexi1 + DREX_INTENS_PPC); in exynos5_dmc_start_perf_events()
775 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_CNTENS_PPC); in exynos5_dmc_start_perf_events()
776 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_CNTENS_PPC); in exynos5_dmc_start_perf_events()
779 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_FLAG_PPC); in exynos5_dmc_start_perf_events()
780 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_FLAG_PPC); in exynos5_dmc_start_perf_events()
783 writel(CC_RESET | PPC_COUNTER_RESET, dmc->base_drexi0 + DREX_PMNC_PPC); in exynos5_dmc_start_perf_events()
784 writel(CC_RESET | PPC_COUNTER_RESET, dmc->base_drexi1 + DREX_PMNC_PPC); in exynos5_dmc_start_perf_events()
788 * will be gathered is calculated as: 0xffffffff - beg_value in exynos5_dmc_start_perf_events()
790 writel(beg_value, dmc->base_drexi0 + DREX_PMCNT2_PPC); in exynos5_dmc_start_perf_events()
791 writel(beg_value, dmc->base_drexi1 + DREX_PMCNT2_PPC); in exynos5_dmc_start_perf_events()
794 writel(PPC_ENABLE, dmc->base_drexi0 + DREX_PMNC_PPC); in exynos5_dmc_start_perf_events()
795 writel(PPC_ENABLE, dmc->base_drexi1 + DREX_PMNC_PPC); in exynos5_dmc_start_perf_events()
799 * exynos5_dmc_perf_events_calc() - Calculate utilization
824 dmc->load = 70; in exynos5_dmc_perf_events_calc()
825 dmc->total = 100; in exynos5_dmc_perf_events_calc()
831 dmc->load = 35; in exynos5_dmc_perf_events_calc()
832 dmc->total = 100; in exynos5_dmc_perf_events_calc()
835 dev_dbg(dmc->dev, "diff_ts=%llu\n", diff_ts); in exynos5_dmc_perf_events_calc()
839 * exynos5_dmc_perf_events_check() - Checks the status of the counters
853 writel(0, dmc->base_drexi0 + DREX_PMNC_PPC); in exynos5_dmc_perf_events_check()
854 writel(0, dmc->base_drexi1 + DREX_PMNC_PPC); in exynos5_dmc_perf_events_check()
857 val = readl(dmc->base_drexi0 + DREX_FLAG_PPC); in exynos5_dmc_perf_events_check()
859 diff_ts = ts - dmc->last_overflow_ts[0]; in exynos5_dmc_perf_events_check()
860 dmc->last_overflow_ts[0] = ts; in exynos5_dmc_perf_events_check()
861 dev_dbg(dmc->dev, "drex0 0xE050 val= 0x%08x\n", val); in exynos5_dmc_perf_events_check()
863 val = readl(dmc->base_drexi1 + DREX_FLAG_PPC); in exynos5_dmc_perf_events_check()
864 diff_ts = ts - dmc->last_overflow_ts[1]; in exynos5_dmc_perf_events_check()
865 dmc->last_overflow_ts[1] = ts; in exynos5_dmc_perf_events_check()
866 dev_dbg(dmc->dev, "drex1 0xE050 val= 0x%08x\n", val); in exynos5_dmc_perf_events_check()
875 * exynos5_dmc_enable_perf_events() - Enable performance events
885 writel(PEREV_CLK_EN, dmc->base_drexi0 + DREX_PPCCLKCON); in exynos5_dmc_enable_perf_events()
886 writel(PEREV_CLK_EN, dmc->base_drexi1 + DREX_PPCCLKCON); in exynos5_dmc_enable_perf_events()
889 writel(READ_TRANSFER_CH0, dmc->base_drexi0 + DREX_PEREV2CONFIG); in exynos5_dmc_enable_perf_events()
890 writel(READ_TRANSFER_CH1, dmc->base_drexi1 + DREX_PEREV2CONFIG); in exynos5_dmc_enable_perf_events()
893 dmc->last_overflow_ts[0] = ts; in exynos5_dmc_enable_perf_events()
894 dmc->last_overflow_ts[1] = ts; in exynos5_dmc_enable_perf_events()
897 dmc->load = 99; in exynos5_dmc_enable_perf_events()
898 dmc->total = 100; in exynos5_dmc_enable_perf_events()
902 * exynos5_dmc_disable_perf_events() - Disable performance events
910 writel(0, dmc->base_drexi0 + DREX_PMNC_PPC); in exynos5_dmc_disable_perf_events()
911 writel(0, dmc->base_drexi1 + DREX_PMNC_PPC); in exynos5_dmc_disable_perf_events()
914 writel(PERF_CNT2, dmc->base_drexi0 + DREX_INTENC_PPC); in exynos5_dmc_disable_perf_events()
915 writel(PERF_CNT2, dmc->base_drexi1 + DREX_INTENC_PPC); in exynos5_dmc_disable_perf_events()
918 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_CNTENC_PPC); in exynos5_dmc_disable_perf_events()
919 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_CNTENC_PPC); in exynos5_dmc_disable_perf_events()
922 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_FLAG_PPC); in exynos5_dmc_disable_perf_events()
923 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_FLAG_PPC); in exynos5_dmc_disable_perf_events()
927 * exynos5_dmc_get_status() - Read current DMC performance statistics.
942 if (dmc->in_irq_mode) { in exynos5_dmc_get_status()
943 mutex_lock(&dmc->lock); in exynos5_dmc_get_status()
944 stat->current_frequency = dmc->curr_rate; in exynos5_dmc_get_status()
945 mutex_unlock(&dmc->lock); in exynos5_dmc_get_status()
947 stat->busy_time = dmc->load; in exynos5_dmc_get_status()
948 stat->total_time = dmc->total; in exynos5_dmc_get_status()
952 return -EINVAL; in exynos5_dmc_get_status()
955 stat->busy_time = load >> 10; in exynos5_dmc_get_status()
956 stat->total_time = total >> 10; in exynos5_dmc_get_status()
969 * exynos5_dmc_get_cur_freq() - Function returns current DMC frequency
971 * @freq: returned frequency value
977 static int exynos5_dmc_get_cur_freq(struct device *dev, unsigned long *freq) in exynos5_dmc_get_cur_freq() argument
981 mutex_lock(&dmc->lock); in exynos5_dmc_get_cur_freq()
982 *freq = dmc->curr_rate; in exynos5_dmc_get_cur_freq()
983 mutex_unlock(&dmc->lock); in exynos5_dmc_get_cur_freq()
989 * exynos5_dmc_df_profile - Devfreq governor's profile structure
1001 * exynos5_dmc_align_initial_frequency() - Align initial frequency value
1021 aligned_freq = dmc->opp[idx].freq_hz; in exynos5_dmc_align_init_freq()
1023 aligned_freq = dmc->opp[dmc->opp_count - 1].freq_hz; in exynos5_dmc_align_init_freq()
1029 * create_timings_aligned() - Create register values and align with standard
1049 return -EINVAL; in create_timings_aligned()
1055 val = dmc->timings->tRFC / clk_period_ps; in create_timings_aligned()
1056 val += dmc->timings->tRFC % clk_period_ps ? 1 : 0; in create_timings_aligned()
1057 val = max(val, dmc->min_tck->tRFC); in create_timings_aligned()
1061 val = dmc->timings->tRRD / clk_period_ps; in create_timings_aligned()
1062 val += dmc->timings->tRRD % clk_period_ps ? 1 : 0; in create_timings_aligned()
1063 val = max(val, dmc->min_tck->tRRD); in create_timings_aligned()
1067 val = dmc->timings->tRPab / clk_period_ps; in create_timings_aligned()
1068 val += dmc->timings->tRPab % clk_period_ps ? 1 : 0; in create_timings_aligned()
1069 val = max(val, dmc->min_tck->tRPab); in create_timings_aligned()
1073 val = dmc->timings->tRCD / clk_period_ps; in create_timings_aligned()
1074 val += dmc->timings->tRCD % clk_period_ps ? 1 : 0; in create_timings_aligned()
1075 val = max(val, dmc->min_tck->tRCD); in create_timings_aligned()
1079 val = dmc->timings->tRC / clk_period_ps; in create_timings_aligned()
1080 val += dmc->timings->tRC % clk_period_ps ? 1 : 0; in create_timings_aligned()
1081 val = max(val, dmc->min_tck->tRC); in create_timings_aligned()
1085 val = dmc->timings->tRAS / clk_period_ps; in create_timings_aligned()
1086 val += dmc->timings->tRAS % clk_period_ps ? 1 : 0; in create_timings_aligned()
1087 val = max(val, dmc->min_tck->tRAS); in create_timings_aligned()
1092 val = dmc->timings->tWTR / clk_period_ps; in create_timings_aligned()
1093 val += dmc->timings->tWTR % clk_period_ps ? 1 : 0; in create_timings_aligned()
1094 val = max(val, dmc->min_tck->tWTR); in create_timings_aligned()
1098 val = dmc->timings->tWR / clk_period_ps; in create_timings_aligned()
1099 val += dmc->timings->tWR % clk_period_ps ? 1 : 0; in create_timings_aligned()
1100 val = max(val, dmc->min_tck->tWR); in create_timings_aligned()
1104 val = dmc->timings->tRTP / clk_period_ps; in create_timings_aligned()
1105 val += dmc->timings->tRTP % clk_period_ps ? 1 : 0; in create_timings_aligned()
1106 val = max(val, dmc->min_tck->tRTP); in create_timings_aligned()
1110 val = dmc->timings->tW2W_C2C / clk_period_ps; in create_timings_aligned()
1111 val += dmc->timings->tW2W_C2C % clk_period_ps ? 1 : 0; in create_timings_aligned()
1112 val = max(val, dmc->min_tck->tW2W_C2C); in create_timings_aligned()
1116 val = dmc->timings->tR2R_C2C / clk_period_ps; in create_timings_aligned()
1117 val += dmc->timings->tR2R_C2C % clk_period_ps ? 1 : 0; in create_timings_aligned()
1118 val = max(val, dmc->min_tck->tR2R_C2C); in create_timings_aligned()
1122 val = dmc->timings->tWL / clk_period_ps; in create_timings_aligned()
1123 val += dmc->timings->tWL % clk_period_ps ? 1 : 0; in create_timings_aligned()
1124 val = max(val, dmc->min_tck->tWL); in create_timings_aligned()
1128 val = dmc->timings->tDQSCK / clk_period_ps; in create_timings_aligned()
1129 val += dmc->timings->tDQSCK % clk_period_ps ? 1 : 0; in create_timings_aligned()
1130 val = max(val, dmc->min_tck->tDQSCK); in create_timings_aligned()
1134 val = dmc->timings->tRL / clk_period_ps; in create_timings_aligned()
1135 val += dmc->timings->tRL % clk_period_ps ? 1 : 0; in create_timings_aligned()
1136 val = max(val, dmc->min_tck->tRL); in create_timings_aligned()
1141 val = dmc->timings->tFAW / clk_period_ps; in create_timings_aligned()
1142 val += dmc->timings->tFAW % clk_period_ps ? 1 : 0; in create_timings_aligned()
1143 val = max(val, dmc->min_tck->tFAW); in create_timings_aligned()
1147 val = dmc->timings->tXSR / clk_period_ps; in create_timings_aligned()
1148 val += dmc->timings->tXSR % clk_period_ps ? 1 : 0; in create_timings_aligned()
1149 val = max(val, dmc->min_tck->tXSR); in create_timings_aligned()
1153 val = dmc->timings->tXP / clk_period_ps; in create_timings_aligned()
1154 val += dmc->timings->tXP % clk_period_ps ? 1 : 0; in create_timings_aligned()
1155 val = max(val, dmc->min_tck->tXP); in create_timings_aligned()
1159 val = dmc->timings->tCKE / clk_period_ps; in create_timings_aligned()
1160 val += dmc->timings->tCKE % clk_period_ps ? 1 : 0; in create_timings_aligned()
1161 val = max(val, dmc->min_tck->tCKE); in create_timings_aligned()
1165 val = dmc->timings->tMRD / clk_period_ps; in create_timings_aligned()
1166 val += dmc->timings->tMRD % clk_period_ps ? 1 : 0; in create_timings_aligned()
1167 val = max(val, dmc->min_tck->tMRD); in create_timings_aligned()
1175 * of_get_dram_timings() - helper function for parsing DT settings for DRAM
1187 np_ddr = of_parse_phandle(dmc->dev->of_node, "device-handle", 0); in of_get_dram_timings()
1189 dev_warn(dmc->dev, "could not find 'device-handle' in DT\n"); in of_get_dram_timings()
1190 return -EINVAL; in of_get_dram_timings()
1193 dmc->timing_row = devm_kmalloc_array(dmc->dev, TIMING_COUNT, in of_get_dram_timings()
1195 if (!dmc->timing_row) in of_get_dram_timings()
1196 return -ENOMEM; in of_get_dram_timings()
1198 dmc->timing_data = devm_kmalloc_array(dmc->dev, TIMING_COUNT, in of_get_dram_timings()
1200 if (!dmc->timing_data) in of_get_dram_timings()
1201 return -ENOMEM; in of_get_dram_timings()
1203 dmc->timing_power = devm_kmalloc_array(dmc->dev, TIMING_COUNT, in of_get_dram_timings()
1205 if (!dmc->timing_power) in of_get_dram_timings()
1206 return -ENOMEM; in of_get_dram_timings()
1208 dmc->timings = of_lpddr3_get_ddr_timings(np_ddr, dmc->dev, in of_get_dram_timings()
1210 &dmc->timings_arr_size); in of_get_dram_timings()
1211 if (!dmc->timings) { in of_get_dram_timings()
1213 dev_warn(dmc->dev, "could not get timings from DT\n"); in of_get_dram_timings()
1214 return -EINVAL; in of_get_dram_timings()
1217 dmc->min_tck = of_lpddr3_get_min_tck(np_ddr, dmc->dev); in of_get_dram_timings()
1218 if (!dmc->min_tck) { in of_get_dram_timings()
1220 dev_warn(dmc->dev, "could not get tck from DT\n"); in of_get_dram_timings()
1221 return -EINVAL; in of_get_dram_timings()
1225 for (idx = 0; idx < dmc->opp_count; idx++) { in of_get_dram_timings()
1226 freq_mhz = dmc->opp[idx].freq_hz / 1000000; in of_get_dram_timings()
1229 ret = create_timings_aligned(dmc, &dmc->timing_row[idx], in of_get_dram_timings()
1230 &dmc->timing_data[idx], in of_get_dram_timings()
1231 &dmc->timing_power[idx], in of_get_dram_timings()
1238 dmc->bypass_timing_row = dmc->timing_row[idx - 1]; in of_get_dram_timings()
1239 dmc->bypass_timing_data = dmc->timing_data[idx - 1]; in of_get_dram_timings()
1240 dmc->bypass_timing_power = dmc->timing_power[idx - 1]; in of_get_dram_timings()
1246 * exynos5_dmc_init_clks() - Initialize clocks needed for DMC operation.
1259 dmc->fout_spll = devm_clk_get(dmc->dev, "fout_spll"); in exynos5_dmc_init_clks()
1260 if (IS_ERR(dmc->fout_spll)) in exynos5_dmc_init_clks()
1261 return PTR_ERR(dmc->fout_spll); in exynos5_dmc_init_clks()
1263 dmc->fout_bpll = devm_clk_get(dmc->dev, "fout_bpll"); in exynos5_dmc_init_clks()
1264 if (IS_ERR(dmc->fout_bpll)) in exynos5_dmc_init_clks()
1265 return PTR_ERR(dmc->fout_bpll); in exynos5_dmc_init_clks()
1267 dmc->mout_mclk_cdrex = devm_clk_get(dmc->dev, "mout_mclk_cdrex"); in exynos5_dmc_init_clks()
1268 if (IS_ERR(dmc->mout_mclk_cdrex)) in exynos5_dmc_init_clks()
1269 return PTR_ERR(dmc->mout_mclk_cdrex); in exynos5_dmc_init_clks()
1271 dmc->mout_bpll = devm_clk_get(dmc->dev, "mout_bpll"); in exynos5_dmc_init_clks()
1272 if (IS_ERR(dmc->mout_bpll)) in exynos5_dmc_init_clks()
1273 return PTR_ERR(dmc->mout_bpll); in exynos5_dmc_init_clks()
1275 dmc->mout_mx_mspll_ccore = devm_clk_get(dmc->dev, in exynos5_dmc_init_clks()
1277 if (IS_ERR(dmc->mout_mx_mspll_ccore)) in exynos5_dmc_init_clks()
1278 return PTR_ERR(dmc->mout_mx_mspll_ccore); in exynos5_dmc_init_clks()
1280 dmc->mout_spll = devm_clk_get(dmc->dev, "ff_dout_spll2"); in exynos5_dmc_init_clks()
1281 if (IS_ERR(dmc->mout_spll)) { in exynos5_dmc_init_clks()
1282 dmc->mout_spll = devm_clk_get(dmc->dev, "mout_sclk_spll"); in exynos5_dmc_init_clks()
1283 if (IS_ERR(dmc->mout_spll)) in exynos5_dmc_init_clks()
1284 return PTR_ERR(dmc->mout_spll); in exynos5_dmc_init_clks()
1290 dmc->curr_rate = clk_get_rate(dmc->mout_mclk_cdrex); in exynos5_dmc_init_clks()
1291 dmc->curr_rate = exynos5_dmc_align_init_freq(dmc, dmc->curr_rate); in exynos5_dmc_init_clks()
1292 exynos5_dmc_df_profile.initial_freq = dmc->curr_rate; in exynos5_dmc_init_clks()
1294 ret = exynos5_dmc_get_volt_freq(dmc, &dmc->curr_rate, &target_rate, in exynos5_dmc_init_clks()
1299 dmc->curr_volt = target_volt; in exynos5_dmc_init_clks()
1301 clk_set_parent(dmc->mout_mx_mspll_ccore, dmc->mout_spll); in exynos5_dmc_init_clks()
1303 clk_prepare_enable(dmc->fout_bpll); in exynos5_dmc_init_clks()
1304 clk_prepare_enable(dmc->mout_bpll); in exynos5_dmc_init_clks()
1310 regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CLKM_SRC, &tmp); in exynos5_dmc_init_clks()
1312 regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CLKM_SRC, tmp); in exynos5_dmc_init_clks()
1318 * exynos5_performance_counters_init() - Initializes performance DMC's counters
1331 dmc->num_counters = devfreq_event_get_edev_count(dmc->dev, in exynos5_performance_counters_init()
1332 "devfreq-events"); in exynos5_performance_counters_init()
1333 if (dmc->num_counters < 0) { in exynos5_performance_counters_init()
1334 dev_err(dmc->dev, "could not get devfreq-event counters\n"); in exynos5_performance_counters_init()
1335 return dmc->num_counters; in exynos5_performance_counters_init()
1338 counters_size = sizeof(struct devfreq_event_dev) * dmc->num_counters; in exynos5_performance_counters_init()
1339 dmc->counter = devm_kzalloc(dmc->dev, counters_size, GFP_KERNEL); in exynos5_performance_counters_init()
1340 if (!dmc->counter) in exynos5_performance_counters_init()
1341 return -ENOMEM; in exynos5_performance_counters_init()
1343 for (i = 0; i < dmc->num_counters; i++) { in exynos5_performance_counters_init()
1344 dmc->counter[i] = in exynos5_performance_counters_init()
1345 devfreq_event_get_edev_by_phandle(dmc->dev, in exynos5_performance_counters_init()
1346 "devfreq-events", i); in exynos5_performance_counters_init()
1347 if (IS_ERR_OR_NULL(dmc->counter[i])) in exynos5_performance_counters_init()
1348 return -EPROBE_DEFER; in exynos5_performance_counters_init()
1353 dev_err(dmc->dev, "could not enable event counter\n"); in exynos5_performance_counters_init()
1360 dev_err(dmc->dev, "could not set event counter\n"); in exynos5_performance_counters_init()
1368 * exynos5_dmc_set_pause_on_switching() - Controls a pause feature in DMC
1381 ret = regmap_read(dmc->clk_regmap, CDREX_PAUSE, &val); in exynos5_dmc_set_pause_on_switching()
1386 regmap_write(dmc->clk_regmap, CDREX_PAUSE, val); in exynos5_dmc_set_pause_on_switching()
1396 mutex_lock(&dmc->df->lock); in dmc_irq_thread()
1398 res = update_devfreq(dmc->df); in dmc_irq_thread()
1399 mutex_unlock(&dmc->df->lock); in dmc_irq_thread()
1402 dev_warn(dmc->dev, "devfreq failed with %d\n", res); in dmc_irq_thread()
1408 * exynos5_dmc_probe() - Probe function for the DMC driver
1420 struct device *dev = &pdev->dev; in exynos5_dmc_probe()
1421 struct device_node *np = dev->of_node; in exynos5_dmc_probe()
1427 return -ENOMEM; in exynos5_dmc_probe()
1429 mutex_init(&dmc->lock); in exynos5_dmc_probe()
1431 dmc->dev = dev; in exynos5_dmc_probe()
1434 dmc->base_drexi0 = devm_platform_ioremap_resource(pdev, 0); in exynos5_dmc_probe()
1435 if (IS_ERR(dmc->base_drexi0)) in exynos5_dmc_probe()
1436 return PTR_ERR(dmc->base_drexi0); in exynos5_dmc_probe()
1438 dmc->base_drexi1 = devm_platform_ioremap_resource(pdev, 1); in exynos5_dmc_probe()
1439 if (IS_ERR(dmc->base_drexi1)) in exynos5_dmc_probe()
1440 return PTR_ERR(dmc->base_drexi1); in exynos5_dmc_probe()
1442 dmc->clk_regmap = syscon_regmap_lookup_by_phandle(np, in exynos5_dmc_probe()
1443 "samsung,syscon-clk"); in exynos5_dmc_probe()
1444 if (IS_ERR(dmc->clk_regmap)) in exynos5_dmc_probe()
1445 return PTR_ERR(dmc->clk_regmap); in exynos5_dmc_probe()
1453 dmc->vdd_mif = devm_regulator_get(dev, "vdd"); in exynos5_dmc_probe()
1454 if (IS_ERR(dmc->vdd_mif)) { in exynos5_dmc_probe()
1455 ret = PTR_ERR(dmc->vdd_mif); in exynos5_dmc_probe()
1499 dmc->gov_data.upthreshold = 55; in exynos5_dmc_probe()
1500 dmc->gov_data.downdifferential = 5; in exynos5_dmc_probe()
1504 dmc->in_irq_mode = 1; in exynos5_dmc_probe()
1516 dmc->gov_data.upthreshold = 10; in exynos5_dmc_probe()
1517 dmc->gov_data.downdifferential = 5; in exynos5_dmc_probe()
1522 dmc->df = devm_devfreq_add_device(dev, &exynos5_dmc_df_profile, in exynos5_dmc_probe()
1524 &dmc->gov_data); in exynos5_dmc_probe()
1526 if (IS_ERR(dmc->df)) { in exynos5_dmc_probe()
1527 ret = PTR_ERR(dmc->df); in exynos5_dmc_probe()
1531 if (dmc->in_irq_mode) in exynos5_dmc_probe()
1534 dev_info(dev, "DMC initialized, in irq mode: %d\n", dmc->in_irq_mode); in exynos5_dmc_probe()
1539 if (dmc->in_irq_mode) in exynos5_dmc_probe()
1544 clk_disable_unprepare(dmc->mout_bpll); in exynos5_dmc_probe()
1545 clk_disable_unprepare(dmc->fout_bpll); in exynos5_dmc_probe()
1551 * exynos5_dmc_remove() - Remove function for the platform device
1560 struct exynos5_dmc *dmc = dev_get_drvdata(&pdev->dev); in exynos5_dmc_remove()
1562 if (dmc->in_irq_mode) in exynos5_dmc_remove()
1567 clk_disable_unprepare(dmc->mout_bpll); in exynos5_dmc_remove()
1568 clk_disable_unprepare(dmc->fout_bpll); in exynos5_dmc_remove()
1570 dev_pm_opp_remove_table(dmc->dev); in exynos5_dmc_remove()
1576 { .compatible = "samsung,exynos5422-dmc", },
1585 .name = "exynos5-dmc",