Lines Matching +full:0 +full:xaa00
53 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
58 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
59 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
60 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
64 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
87 #define PVR2_CTL_WRITE_ENDPOINT 0x01
88 #define PVR2_CTL_READ_ENDPOINT 0x81
90 #define PVR2_GPIO_IN 0x9008
91 #define PVR2_GPIO_OUT 0x900c
92 #define PVR2_GPIO_DIR 0x9020
96 #define PVR2_FIRMWARE_ENDPOINT 0x02
99 #define FIRMWARE_CHUNK_SIZE 0x2000
347 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) { in ctrl_channelfreq_get()
350 *vp = 0; in ctrl_channelfreq_get()
352 return 0; in ctrl_channelfreq_get()
359 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) { in ctrl_channelfreq_set()
366 hdw->freqSlotRadio = 0; in ctrl_channelfreq_set()
370 hdw->freqSlotTelevision = 0; in ctrl_channelfreq_set()
374 return 0; in ctrl_channelfreq_set()
380 return 0; in ctrl_channelprog_get()
386 if ((v >= 0) && (v <= FREQTABLE_SIZE)) { in ctrl_channelprog_set()
389 return 0; in ctrl_channelprog_set()
396 return 0; in ctrl_channel_get()
401 unsigned freq = 0; in ctrl_channel_set()
403 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0; in ctrl_channel_set()
404 if (slotId > 0) { in ctrl_channel_set()
406 if (!freq) return 0; in ctrl_channel_set()
414 return 0; in ctrl_channel_set()
420 return 0; in ctrl_freq_get()
425 return cptr->hdw->freqDirty != 0; in ctrl_freq_is_dirty()
430 cptr->hdw->freqDirty = 0; in ctrl_freq_clear_dirty()
436 return 0; in ctrl_freq_set()
443 if (stat != 0) { in ctrl_cropl_min_get()
447 return 0; in ctrl_cropl_min_get()
454 if (stat != 0) { in ctrl_cropl_max_get()
461 return 0; in ctrl_cropl_max_get()
468 if (stat != 0) { in ctrl_cropt_min_get()
472 return 0; in ctrl_cropt_min_get()
479 if (stat != 0) { in ctrl_cropt_max_get()
486 return 0; in ctrl_cropt_max_get()
495 if (stat != 0) { in ctrl_cropw_max_get()
501 *width = cleft < bleftend ? bleftend-cleft : 0; in ctrl_cropw_max_get()
502 return 0; in ctrl_cropw_max_get()
511 if (stat != 0) { in ctrl_croph_max_get()
517 *height = ctop < btopend ? btopend-ctop : 0; in ctrl_croph_max_get()
518 return 0; in ctrl_croph_max_get()
525 if (stat != 0) { in ctrl_get_cropcapbl()
529 return 0; in ctrl_get_cropcapbl()
536 if (stat != 0) { in ctrl_get_cropcapbt()
540 return 0; in ctrl_get_cropcapbt()
547 if (stat != 0) { in ctrl_get_cropcapbw()
551 return 0; in ctrl_get_cropcapbw()
558 if (stat != 0) { in ctrl_get_cropcapbh()
562 return 0; in ctrl_get_cropcapbh()
569 if (stat != 0) { in ctrl_get_cropcapdl()
573 return 0; in ctrl_get_cropcapdl()
580 if (stat != 0) { in ctrl_get_cropcapdt()
584 return 0; in ctrl_get_cropcapdt()
591 if (stat != 0) { in ctrl_get_cropcapdw()
595 return 0; in ctrl_get_cropcapdw()
602 if (stat != 0) { in ctrl_get_cropcapdh()
606 return 0; in ctrl_get_cropcapdh()
613 if (stat != 0) { in ctrl_get_cropcappan()
617 return 0; in ctrl_get_cropcappan()
624 if (stat != 0) { in ctrl_get_cropcappad()
628 return 0; in ctrl_get_cropcappad()
639 return 0; in ctrl_vres_max_get()
650 return 0; in ctrl_vres_min_get()
656 return 0; in ctrl_get_input()
661 if (v < 0 || v > PVR2_CVAL_INPUT_MAX) in ctrl_check_input()
662 return 0; in ctrl_check_input()
663 return ((1UL << v) & cptr->hdw->input_allowed_mask) != 0; in ctrl_check_input()
673 return cptr->hdw->input_dirty != 0; in ctrl_isdirty_input()
678 cptr->hdw->input_dirty = 0; in ctrl_cleardirty_input()
693 return 0; in ctrl_freq_max_get()
701 return 0; in ctrl_freq_max_get()
715 return 0; in ctrl_freq_min_get()
723 return 0; in ctrl_freq_min_get()
728 return cptr->hdw->enc_stale != 0; in ctrl_cx2341x_is_dirty()
733 cptr->hdw->enc_stale = 0; in ctrl_cx2341x_clear_dirty()
734 cptr->hdw->enc_unsafe_stale = 0; in ctrl_cx2341x_clear_dirty()
742 memset(&cs,0,sizeof(cs)); in ctrl_cx2341x_get()
743 memset(&c1,0,sizeof(c1)); in ctrl_cx2341x_get()
747 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs, in ctrl_cx2341x_get()
751 return 0; in ctrl_cx2341x_get()
760 memset(&cs,0,sizeof(cs)); in ctrl_cx2341x_set()
761 memset(&c1,0,sizeof(c1)); in ctrl_cx2341x_set()
776 0, &cs, in ctrl_cx2341x_set()
778 if (!ret) hdw->enc_unsafe_stale = !0; in ctrl_cx2341x_set()
781 hdw->enc_stale = !0; in ctrl_cx2341x_set()
782 return 0; in ctrl_cx2341x_set()
813 return 0; in ctrl_streamingenabled_get()
819 return 0; in ctrl_masterstate_get()
826 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL; in ctrl_hsm_get()
828 return 0; in ctrl_hsm_get()
834 return 0; in ctrl_stddetect_get()
840 return 0; in ctrl_stdavail_get()
849 if (ns == hdw->std_mask_avail) return 0; in ctrl_stdavail_set()
852 return 0; in ctrl_stdavail_set()
860 return 0; in ctrl_std_val_to_sym()
872 return 0; in ctrl_std_sym_to_val()
878 return 0; in ctrl_stdcur_get()
887 if (ns == hdw->std_mask_cur) return 0; in ctrl_stdcur_set()
889 hdw->std_dirty = !0; in ctrl_stdcur_set()
890 return 0; in ctrl_stdcur_set()
895 return cptr->hdw->std_dirty != 0; in ctrl_stdcur_is_dirty()
900 cptr->hdw->std_dirty = 0; in ctrl_stdcur_clear_dirty()
908 return 0; in ctrl_signal_get()
913 int val = 0; in ctrl_audio_modes_present_get()
931 return 0; in ctrl_audio_modes_present_get()
962 {*vp = cptr->hdw->vname##_val; return 0;} \
964 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
966 {return cptr->hdw->vname##_dirty != 0;} \
968 {cptr->hdw->vname##_dirty = 0;}
996 DEFINT(0,255),
1003 DEFINT(0,127),
1010 DEFINT(0,127),
1015 .default_value = 0,
1024 DEFINT(0,65535),
1029 .default_value = 0,
1036 .default_value = 0,
1043 .default_value = 0,
1050 .default_value = 0,
1057 .default_value = 0,
1067 .default_value = 0,
1079 DEFINT(0, 864),
1088 DEFINT(0, 576),
1165 .default_value = 0,
1170 DEFINT(0,0),
1180 DEFINT(0,FREQTABLE_SIZE),
1186 DEFINT(0,0),
1196 DEFINT(0,FREQTABLE_SIZE),
1216 DEFINT(0,65535),
1234 .skip_init = !0,
1244 .skip_init = !0,
1256 .skip_init = !0,
1316 hdw->freqSelector = 0; in pvr2_hdw_set_cur_freq()
1317 hdw->freqDirty = !0; in pvr2_hdw_set_cur_freq()
1321 hdw->freqSlotRadio = 0; in pvr2_hdw_set_cur_freq()
1322 hdw->freqDirty = !0; in pvr2_hdw_set_cur_freq()
1328 hdw->freqDirty = !0; in pvr2_hdw_set_cur_freq()
1332 hdw->freqSlotTelevision = 0; in pvr2_hdw_set_cur_freq()
1333 hdw->freqDirty = !0; in pvr2_hdw_set_cur_freq()
1345 appropriate to what has been found. The return value will be 0 or
1358 for (idx = 0; idx < fwcount; idx++) { in pvr2_locate_firmware()
1381 fwtypename,fwnames[0]); in pvr2_locate_firmware()
1386 for (idx = 0; idx < fwcount; idx++) { in pvr2_locate_firmware()
1429 if (ret < 0) { in pvr2_upload_firmware1()
1434 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f)); in pvr2_upload_firmware1()
1436 pipe = usb_sndctrlpipe(hdw->usb_dev, 0); in pvr2_upload_firmware1()
1439 if ((fwsize != 0x2000) && in pvr2_upload_firmware1()
1440 (!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) { in pvr2_upload_firmware1()
1454 fw_ptr = kmalloc(0x800, GFP_KERNEL); in pvr2_upload_firmware1()
1463 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes in pvr2_upload_firmware1()
1466 ret = 0; in pvr2_upload_firmware1()
1467 for (address = 0; address < fwsize; address += 0x800) { in pvr2_upload_firmware1()
1468 memcpy(fw_ptr, fw_entry->data + address, 0x800); in pvr2_upload_firmware1()
1469 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address, in pvr2_upload_firmware1()
1470 0, fw_ptr, 0x800, HZ); in pvr2_upload_firmware1()
1476 pvr2_hdw_cpureset_assert(hdw,0); in pvr2_upload_firmware1()
1486 return 0; in pvr2_upload_firmware1()
1506 int ret = 0; in pvr2_upload_firmware2()
1513 return 0; in pvr2_upload_firmware2()
1520 if (ret < 0) return ret; in pvr2_upload_firmware2()
1522 ret = 0; in pvr2_upload_firmware2()
1526 hdw->enc_cur_valid = 0; in pvr2_upload_firmware2()
1532 hdw->state_encoder_runok = 0; in pvr2_upload_firmware2()
1537 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/ in pvr2_upload_firmware2()
1538 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/ in pvr2_upload_firmware2()
1539 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/ in pvr2_upload_firmware2()
1541 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/ in pvr2_upload_firmware2()
1542 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/ in pvr2_upload_firmware2()
1543 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/ in pvr2_upload_firmware2()
1544 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/ in pvr2_upload_firmware2()
1545 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/ in pvr2_upload_firmware2()
1546 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/ in pvr2_upload_firmware2()
1547 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/ in pvr2_upload_firmware2()
1548 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/ in pvr2_upload_firmware2()
1549 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/ in pvr2_upload_firmware2()
1550 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/ in pvr2_upload_firmware2()
1551 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/ in pvr2_upload_firmware2()
1552 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/ in pvr2_upload_firmware2()
1554 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16)); in pvr2_upload_firmware2()
1587 fw_done = 0; in pvr2_upload_firmware2()
1588 for (fw_done = 0; fw_done < fw_len;) { in pvr2_upload_firmware2()
1604 for (icnt = 0; icnt < bcnt/4 ; icnt++) in pvr2_upload_firmware2()
1628 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/ in pvr2_upload_firmware2()
1629 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/ in pvr2_upload_firmware2()
1630 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16)); in pvr2_upload_firmware2()
1642 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0); in pvr2_upload_firmware2()
1664 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl); in pvr2_decoder_enable()
1665 v4l2_device_call_all(&hdw->v4l2_dev, 0, audio, s_stream, enablefl); in pvr2_decoder_enable()
1670 return 0; in pvr2_decoder_enable()
1675 hdw->flag_decoder_missed = !0; in pvr2_decoder_enable()
1691 if (!hdw->flag_tripped) return 0; in pvr2_hdw_untrip_unlocked()
1692 hdw->flag_tripped = 0; in pvr2_hdw_untrip_unlocked()
1695 return !0; in pvr2_hdw_untrip_unlocked()
1704 } while (0); LOCK_GIVE(hdw->big_lock); in pvr2_hdw_untrip()
1706 return 0; in pvr2_hdw_untrip()
1714 return hdw->state_pipeline_req != 0; in pvr2_hdw_get_streaming()
1724 hdw->state_pipeline_req = enable_flag != 0; in pvr2_hdw_set_streaming()
1730 } while (0); LOCK_GIVE(hdw->big_lock); in pvr2_hdw_set_streaming()
1731 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret; in pvr2_hdw_set_streaming()
1735 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret; in pvr2_hdw_set_streaming()
1738 return 0; in pvr2_hdw_set_streaming()
1746 if ((fl = (hdw->desired_stream_type != config)) != 0) { in pvr2_hdw_set_stream_type()
1748 hdw->state_pipeline_config = 0; in pvr2_hdw_set_stream_type()
1754 if (fl) return 0; in pvr2_hdw_set_stream_type()
1755 return pvr2_hdw_wait(hdw,0); in pvr2_hdw_set_stream_type()
1763 if ((unit_number >= 0) && (unit_number < PVR_NUM)) { in get_default_tuner_type()
1766 if (tp < 0) return -EINVAL; in get_default_tuner_type()
1768 hdw->tuner_updated = !0; in get_default_tuner_type()
1769 return 0; in get_default_tuner_type()
1776 int tp = 0; in get_default_standard()
1777 if ((unit_number >= 0) && (unit_number < PVR_NUM)) { in get_default_standard()
1781 return 0; in get_default_standard()
1788 int tp = 0; in get_default_error_tolerance()
1789 if ((unit_number >= 0) && (unit_number < PVR_NUM)) { in get_default_error_tolerance()
1804 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR; in pvr2_hdw_check_firmware()
1805 result = pvr2_send_request_ex(hdw,HZ*1,!0, in pvr2_hdw_check_firmware()
1808 if (result < 0) break; in pvr2_hdw_check_firmware()
1809 } while(0); LOCK_GIVE(hdw->ctl_lock); in pvr2_hdw_check_firmware()
1818 return result == 0; in pvr2_hdw_check_firmware()
1866 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask; in pvr2_hdw_setup_std()
1892 hdw->std_dirty = !0; in pvr2_hdw_setup_std()
1901 hdw->std_dirty = !0; in pvr2_hdw_setup_std()
1907 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) { in pvr2_hdw_setup_std()
1920 hdw->std_dirty = !0; in pvr2_hdw_setup_std()
1932 unsigned int cnt = 0; in pvr2_copy_i2c_addr_list()
1933 if (!src) return 0; in pvr2_copy_i2c_addr_list()
1963 memset(&fmt, 0, sizeof(fmt)); in pvr2_hdw_cx25840_vbi_hack()
1965 fmt.fmt.sliced.service_lines[0][21] = V4L2_SLICED_CAPTION_525; in pvr2_hdw_cx25840_vbi_hack()
2020 "Module ID %u: Setting up with specified i2c address 0x%x", in pvr2_hdw_load_subdev()
2021 mid, i2caddr[0]); in pvr2_hdw_load_subdev()
2023 fname, i2caddr[0], NULL); in pvr2_hdw_load_subdev()
2029 fname, 0, i2caddr); in pvr2_hdw_load_subdev()
2056 return 0; in pvr2_hdw_load_subdev()
2065 int okFl = !0; in pvr2_hdw_load_modules()
2068 for (idx = 0; idx < cm->cnt; idx++) { in pvr2_hdw_load_modules()
2073 for (idx = 0; idx < ct->cnt; idx++) { in pvr2_hdw_load_modules()
2074 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0; in pvr2_hdw_load_modules()
2077 hdw->flag_modulefail = !0; in pvr2_hdw_load_modules()
2088 int reloadFl = 0; in pvr2_hdw_setup_low()
2093 == 0); in pvr2_hdw_setup_low()
2107 if (pvr2_upload_firmware1(hdw) != 0) { in pvr2_hdw_setup_low()
2118 hdw->force_dirty = !0; in pvr2_hdw_setup_low()
2130 ((0) << 16)); in pvr2_hdw_setup_low()
2138 if (le16_to_cpu(hdw->usb_dev->descriptor.idVendor) == 0x2040 && in pvr2_hdw_setup_low()
2139 (le16_to_cpu(hdw->usb_dev->descriptor.idProduct) == 0x7502 || in pvr2_hdw_setup_low()
2140 le16_to_cpu(hdw->usb_dev->descriptor.idProduct) == 0x7510)) { in pvr2_hdw_setup_low()
2146 ((0) << 16)); in pvr2_hdw_setup_low()
2158 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw); in pvr2_hdw_setup_low()
2160 for (idx = 0; idx < CTRLDEF_COUNT; idx++) { in pvr2_hdw_setup_low()
2164 cptr->info->set_value(cptr,~0,cptr->info->default_value); in pvr2_hdw_setup_low()
2184 if (ret < 0) { in pvr2_hdw_setup_low()
2194 hdw->tuner_updated = !0; in pvr2_hdw_setup_low()
2201 } else if (hdw->unit_number >= 0) { in pvr2_hdw_setup_low()
2209 hdw->identifier[idx] = 0; in pvr2_hdw_setup_low()
2226 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0); in pvr2_hdw_setup_low()
2248 hdw->flag_init_ok = !0; in pvr2_hdw_setup_low()
2314 } while (0); in pvr2_hdw_setup()
2339 } while (0); LOCK_GIVE(hdw->big_lock); in pvr2_hdw_initialize()
2388 timer_setup(&hdw->quiescent_timer, pvr2_hdw_quiescent_timeout, 0); in pvr2_hdw_create()
2391 pvr2_hdw_decoder_stabilization_timeout, 0); in pvr2_hdw_create()
2394 0); in pvr2_hdw_create()
2396 timer_setup(&hdw->encoder_run_timer, pvr2_hdw_encoder_run_timeout, 0); in pvr2_hdw_create()
2402 hdw->tuner_signal_stale = !0; in pvr2_hdw_create()
2406 m = 0; in pvr2_hdw_create()
2432 for (idx = 0; idx < hdw->control_cnt; idx++) { in pvr2_hdw_create()
2436 for (idx = 0; idx < 32; idx++) { in pvr2_hdw_create()
2439 for (idx = 0; idx < CTRLDEF_COUNT; idx++) { in pvr2_hdw_create()
2446 if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) { in pvr2_hdw_create()
2457 for (idx = 0; idx < MPEGDEF_COUNT; idx++) { in pvr2_hdw_create()
2463 ciptr->skip_init = !0; in pvr2_hdw_create()
2491 for (cnt1 = 0; in pvr2_hdw_create()
2502 for (idx = 0; idx < 32; idx++) { in pvr2_hdw_create()
2508 hdw->std_mask_names[idx][cnt1] = 0; in pvr2_hdw_create()
2541 hdw->cropcap_stale = !0; in pvr2_hdw_create()
2551 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL); in pvr2_hdw_create()
2553 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL); in pvr2_hdw_create()
2556 if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) { in pvr2_hdw_create()
2563 for (idx = 0; idx < PVR_NUM; idx++) { in pvr2_hdw_create()
2569 } while (0); in pvr2_hdw_create()
2572 cnt1 = 0; in pvr2_hdw_create()
2575 if (hdw->unit_number >= 0) { in pvr2_hdw_create()
2581 hdw->name[cnt1] = 0; in pvr2_hdw_create()
2589 hdw->flag_ok = !0; in pvr2_hdw_create()
2597 usb_set_interface(hdw->usb_dev,ifnum,0); in pvr2_hdw_create()
2646 hdw->flag_disconnected = !0; in pvr2_hdw_remove_usb_stuff()
2684 if ((hdw->unit_number >= 0) && in pvr2_hdw_destroy()
2689 } while (0); in pvr2_hdw_destroy()
2722 /* Retrieve a control handle given its index (0..count-1) */
2731 /* Retrieve a control handle given its index (0..count-1) */
2740 for (idx = 0; idx < hdw->control_cnt; idx++) { in pvr2_hdw_get_ctrl_by_id()
2757 for (idx = 0; idx < hdw->control_cnt; idx++) { in pvr2_hdw_get_ctrl_v4l()
2777 for (idx = 0; idx < hdw->control_cnt; idx++) { in pvr2_hdw_get_ctrl_nextv4l()
2809 memset(&ctrl, 0, sizeof(ctrl)); in pvr2_subdev_set_control()
2826 v4l2_device_call_all(&hdw->v4l2_dev, 0, in pvr2_hdw_get_detected_std()
2845 if (((int)(hdw->tuner_type)) >= 0) { in pvr2_subdev_update()
2846 memset(&setup, 0, sizeof(setup)); in pvr2_subdev_update()
2850 v4l2_device_call_all(&hdw->v4l2_dev, 0, in pvr2_subdev_update()
2858 v4l2_device_call_all(&hdw->v4l2_dev, 0, in pvr2_subdev_update()
2863 v4l2_device_call_all(&hdw->v4l2_dev, 0, in pvr2_subdev_update()
2867 hdw->tuner_signal_stale = !0; in pvr2_subdev_update()
2868 hdw->cropcap_stale = !0; in pvr2_subdev_update()
2883 memset(&vt, 0, sizeof(vt)); in pvr2_subdev_update()
2887 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt); in pvr2_subdev_update()
2896 memset(&freq, 0, sizeof(freq)); in pvr2_subdev_update()
2910 freq.tuner = 0; in pvr2_subdev_update()
2911 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, in pvr2_subdev_update()
2925 v4l2_device_call_all(&hdw->v4l2_dev, 0, pad, set_fmt, in pvr2_subdev_update()
2945 v4l2_device_call_all(&hdw->v4l2_dev, 0, in pvr2_subdev_update()
2978 for (idx = 0; idx < hdw->control_cnt; idx++) { in pvr2_hdw_commit_setup()
2982 commit_flag = !0; in pvr2_hdw_commit_setup()
2987 value = 0; in pvr2_hdw_commit_setup()
2989 pvr2_ctrl_value_to_sym_internal(cptr,~0,value, in pvr2_hdw_commit_setup()
3002 return 0; in pvr2_hdw_commit_setup()
3005 hdw->state_pipeline_config = 0; in pvr2_hdw_commit_setup()
3009 return !0; in pvr2_hdw_commit_setup()
3029 hdw->state_pathway_ok = 0; in pvr2_hdw_commit_execute()
3034 return 0; in pvr2_hdw_commit_execute()
3053 hdw->res_ver_dirty = !0; in pvr2_hdw_commit_execute()
3060 memset(&cs, 0, sizeof(cs)); in pvr2_hdw_commit_execute()
3061 memset(&c1, 0, sizeof(c1)); in pvr2_hdw_commit_execute()
3066 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs, in pvr2_hdw_commit_execute()
3079 hdw->cropw_dirty = !0; in pvr2_hdw_commit_execute()
3081 hdw->res_hor_dirty = !0; /* must rescale */ in pvr2_hdw_commit_execute()
3086 hdw->croph_dirty = !0; in pvr2_hdw_commit_execute()
3089 hdw->res_ver_dirty = !0; in pvr2_hdw_commit_execute()
3111 hdw->state_pipeline_pause = !0; in pvr2_hdw_commit_execute()
3112 return 0; in pvr2_hdw_commit_execute()
3122 memset(&cs,0,sizeof(cs)); in pvr2_hdw_commit_execute()
3123 memset(&c1,0,sizeof(c1)); in pvr2_hdw_commit_execute()
3128 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS); in pvr2_hdw_commit_execute()
3143 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0); in pvr2_hdw_commit_execute()
3146 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0); in pvr2_hdw_commit_execute()
3153 hdw->tuner_updated = 0; in pvr2_hdw_commit_execute()
3154 hdw->force_dirty = 0; in pvr2_hdw_commit_execute()
3155 for (idx = 0; idx < hdw->control_cnt; idx++) { in pvr2_hdw_commit_execute()
3166 if (pvr2_encoder_adjust(hdw) < 0) return !0; in pvr2_hdw_commit_execute()
3169 hdw->state_pipeline_config = !0; in pvr2_hdw_commit_execute()
3174 return !0; in pvr2_hdw_commit_execute()
3184 if (!fl) return 0; in pvr2_hdw_commit_ctl()
3185 return pvr2_hdw_wait(hdw,0); in pvr2_hdw_commit_ctl()
3191 int fl = 0; in pvr2_hdw_worker_poll()
3195 } while (0); LOCK_GIVE(hdw->big_lock); in pvr2_hdw_worker_poll()
3206 (hdw->state_stale == 0) && in pvr2_hdw_wait()
3234 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED; in pvr2_hdw_is_hsm()
3238 if (result < 0) break; in pvr2_hdw_is_hsm()
3239 result = (hdw->cmd_buffer[0] != 0); in pvr2_hdw_is_hsm()
3240 } while(0); LOCK_GIVE(hdw->ctl_lock); in pvr2_hdw_is_hsm()
3250 } while (0); LOCK_GIVE(hdw->big_lock); in pvr2_hdw_execute_tuner_poll()
3257 return 0; in pvr2_hdw_check_cropcap()
3263 return 0; in pvr2_hdw_check_cropcap()
3270 int stat = 0; in pvr2_hdw_get_cropcap()
3289 } while (0); LOCK_GIVE(hdw->big_lock); in pvr2_hdw_get_tuner_status()
3290 return 0; in pvr2_hdw_get_tuner_status()
3307 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status); in pvr2_hdw_trigger_module_log()
3312 } while (0); in pvr2_hdw_trigger_module_log()
3329 int mode16 = 0; in pvr2_full_eeprom_fetch()
3338 trace_eeprom("Value for eeprom addr from controller was 0x%x", in pvr2_full_eeprom_fetch()
3344 if (addr & 0x80) addr >>= 1; in pvr2_full_eeprom_fetch()
3351 trace_eeprom("Examining %d byte eeprom at location 0x%x using %d bit addressing", in pvr2_full_eeprom_fetch()
3355 msg[0].addr = addr; in pvr2_full_eeprom_fetch()
3356 msg[0].flags = 0; in pvr2_full_eeprom_fetch()
3357 msg[0].len = mode16 ? 2 : 1; in pvr2_full_eeprom_fetch()
3358 msg[0].buf = iadd; in pvr2_full_eeprom_fetch()
3366 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) { in pvr2_full_eeprom_fetch()
3371 iadd[0] = offs >> 8; in pvr2_full_eeprom_fetch()
3374 iadd[0] = offs; in pvr2_full_eeprom_fetch()
3405 hdw->fw_size = 0; in pvr2_hdw_cpufw_set_enabled()
3409 pvr2_hdw_cpureset_assert(hdw,0); in pvr2_hdw_cpufw_set_enabled()
3416 hdw->fw_size = (mode == 1) ? 0x4000 : 0x2000; in pvr2_hdw_cpufw_set_enabled()
3422 hdw->fw_size = 0; in pvr2_hdw_cpufw_set_enabled()
3430 (=0x800) bytes chunk. */ in pvr2_hdw_cpufw_set_enabled()
3434 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0); in pvr2_hdw_cpufw_set_enabled()
3435 for(address = 0; address < hdw->fw_size; in pvr2_hdw_cpufw_set_enabled()
3436 address += 0x800) { in pvr2_hdw_cpufw_set_enabled()
3438 0xa0,0xc0, in pvr2_hdw_cpufw_set_enabled()
3439 address,0, in pvr2_hdw_cpufw_set_enabled()
3441 0x800,HZ); in pvr2_hdw_cpufw_set_enabled()
3442 if (ret < 0) break; in pvr2_hdw_cpufw_set_enabled()
3461 } while (0); LOCK_GIVE(hdw->big_lock); in pvr2_hdw_cpufw_set_enabled()
3489 ret = 0; in pvr2_hdw_cpufw_get()
3501 } while (0); LOCK_GIVE(hdw->big_lock); in pvr2_hdw_cpufw_get()
3535 hdw->ctl_write_pend_flag = 0; in pvr2_ctl_write_complete()
3544 hdw->ctl_read_pend_flag = 0; in pvr2_ctl_read_complete()
3560 hdw->ctl_timeout_flag = !0; in pvr2_ctl_timeout()
3579 int status = 0; in pvr2_send_request_ex()
3603 if (!write_data) write_len = 0; in pvr2_send_request_ex()
3604 if (!read_data) read_len = 0; in pvr2_send_request_ex()
3629 hdw->cmd_debug_code = ((unsigned char *)write_data)[0]; in pvr2_send_request_ex()
3631 hdw->cmd_debug_code = 0; in pvr2_send_request_ex()
3637 hdw->ctl_timeout_flag = 0; in pvr2_send_request_ex()
3638 hdw->ctl_write_pend_flag = 0; in pvr2_send_request_ex()
3639 hdw->ctl_read_pend_flag = 0; in pvr2_send_request_ex()
3640 timer_setup_on_stack(&timer.timer, pvr2_ctl_timeout, 0); in pvr2_send_request_ex()
3646 for (idx = 0; idx < write_len; idx++) { in pvr2_send_request_ex()
3659 hdw->ctl_write_urb->actual_length = 0; in pvr2_send_request_ex()
3660 hdw->ctl_write_pend_flag = !0; in pvr2_send_request_ex()
3668 if (status < 0) { in pvr2_send_request_ex()
3672 hdw->ctl_write_pend_flag = 0; in pvr2_send_request_ex()
3679 memset(hdw->ctl_read_buffer,0x43,read_len); in pvr2_send_request_ex()
3689 hdw->ctl_read_urb->actual_length = 0; in pvr2_send_request_ex()
3690 hdw->ctl_read_pend_flag = !0; in pvr2_send_request_ex()
3698 if (status < 0) { in pvr2_send_request_ex()
3702 hdw->ctl_read_pend_flag = 0; in pvr2_send_request_ex()
3721 status = 0; in pvr2_send_request_ex()
3734 if ((hdw->ctl_write_urb->status != 0) && in pvr2_send_request_ex()
3762 if ((hdw->ctl_read_urb->status != 0) && in pvr2_send_request_ex()
3788 for (idx = 0; idx < read_len; idx++) { in pvr2_send_request_ex()
3796 hdw->cmd_debug_state = 0; in pvr2_send_request_ex()
3797 if ((status < 0) && (!probe_fl)) { in pvr2_send_request_ex()
3810 return pvr2_send_request_ex(hdw,HZ*4,0, in pvr2_send_request()
3820 unsigned int args = 0; in pvr2_issue_simple_cmd()
3822 hdw->cmd_buffer[0] = cmdcode & 0xffu; in pvr2_issue_simple_cmd()
3823 args = (cmdcode >> 8) & 0xffu; in pvr2_issue_simple_cmd()
3827 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu; in pvr2_issue_simple_cmd()
3829 hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu; in pvr2_issue_simple_cmd()
3836 cmdcode &= 0xffu; in pvr2_issue_simple_cmd()
3837 bcnt = 0; in pvr2_issue_simple_cmd()
3840 "Sending FX2 command 0x%x",cmdcode); in pvr2_issue_simple_cmd()
3842 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) { in pvr2_issue_simple_cmd()
3870 ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0); in pvr2_issue_simple_cmd()
3882 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */ in pvr2_write_register()
3884 hdw->cmd_buffer[5] = 0; in pvr2_write_register()
3885 hdw->cmd_buffer[6] = (reg >> 8) & 0xff; in pvr2_write_register()
3886 hdw->cmd_buffer[7] = reg & 0xff; in pvr2_write_register()
3889 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0); in pvr2_write_register()
3899 int ret = 0; in pvr2_read_register()
3903 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */ in pvr2_read_register()
3904 hdw->cmd_buffer[1] = 0; in pvr2_read_register()
3905 hdw->cmd_buffer[2] = 0; in pvr2_read_register()
3906 hdw->cmd_buffer[3] = 0; in pvr2_read_register()
3907 hdw->cmd_buffer[4] = 0; in pvr2_read_register()
3908 hdw->cmd_buffer[5] = 0; in pvr2_read_register()
3909 hdw->cmd_buffer[6] = (reg >> 8) & 0xff; in pvr2_read_register()
3910 hdw->cmd_buffer[7] = reg & 0xff; in pvr2_read_register()
3913 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0); in pvr2_read_register()
3927 pvr2_stream_setup(hdw->vid_stream,NULL,0,0); in pvr2_hdw_render_useless()
3929 hdw->flag_ok = 0; in pvr2_hdw_render_useless()
3940 if (ret == 0) { in pvr2_hdw_device_reset()
3975 da[0] = val ? 0x01 : 0x00; in pvr2_hdw_cpureset_assert()
3978 is the reset bit; a 1 asserts reset while a 0 clears it. */ in pvr2_hdw_cpureset_assert()
3979 pipe = usb_sndctrlpipe(hdw->usb_dev, 0); in pvr2_hdw_cpureset_assert()
3980 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ); in pvr2_hdw_cpureset_assert()
3981 if (ret < 0) { in pvr2_hdw_cpureset_assert()
4010 core, reset, 0); in pvr2_hdw_cmd_decoder_reset()
4012 return 0; in pvr2_hdw_cmd_decoder_reset()
4022 hdw->flag_ok = !0; in pvr2_hdw_cmd_hcw_demod_reset()
4025 if (le16_to_cpu(hdw->usb_dev->descriptor.idVendor) == 0x2040 && in pvr2_hdw_cmd_hcw_demod_reset()
4026 (le16_to_cpu(hdw->usb_dev->descriptor.idProduct) == 0x7502 || in pvr2_hdw_cmd_hcw_demod_reset()
4027 le16_to_cpu(hdw->usb_dev->descriptor.idProduct) == 0x7510)) { in pvr2_hdw_cmd_hcw_demod_reset()
4034 ((onoff ? 1 : 0) << 16)); in pvr2_hdw_cmd_hcw_demod_reset()
4040 ((onoff ? 1 : 0) << 16)); in pvr2_hdw_cmd_hcw_demod_reset()
4046 hdw->flag_ok = !0; in pvr2_hdw_cmd_onair_fe_power_ctrl()
4107 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481); in pvr2_led_ctrl_hauppauge()
4109 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401); in pvr2_led_ctrl_hauppauge()
4111 pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000); in pvr2_led_ctrl_hauppauge()
4130 hdw->led_on = onoff != 0; in pvr2_led_ctrl()
4191 return 0; in state_eval_pathway_ok()
4195 return 0; in state_eval_pathway_ok()
4198 hdw->state_pathway_ok = !0; in state_eval_pathway_ok()
4200 return !0; in state_eval_pathway_ok()
4207 if (hdw->state_encoder_ok) return 0; in state_eval_encoder_ok()
4208 if (hdw->flag_tripped) return 0; in state_eval_encoder_ok()
4209 if (hdw->state_encoder_run) return 0; in state_eval_encoder_ok()
4210 if (hdw->state_encoder_config) return 0; in state_eval_encoder_ok()
4211 if (hdw->state_decoder_run) return 0; in state_eval_encoder_ok()
4212 if (hdw->state_usbstream_run) return 0; in state_eval_encoder_ok()
4214 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0; in state_eval_encoder_ok()
4216 return 0; in state_eval_encoder_ok()
4219 if (pvr2_upload_firmware2(hdw) < 0) { in state_eval_encoder_ok()
4220 hdw->flag_tripped = !0; in state_eval_encoder_ok()
4222 return !0; in state_eval_encoder_ok()
4224 hdw->state_encoder_ok = !0; in state_eval_encoder_ok()
4226 return !0; in state_eval_encoder_ok()
4236 !hdw->state_pipeline_pause) return 0; in state_eval_encoder_config()
4238 hdw->state_encoder_config = 0; in state_eval_encoder_config()
4239 hdw->state_encoder_waitok = 0; in state_eval_encoder_config()
4261 hdw->state_encoder_waitok = 0; in state_eval_encoder_config()
4264 return !0; in state_eval_encoder_config()
4266 return 0; in state_eval_encoder_config()
4286 return 0; in state_eval_encoder_config()
4289 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0; in state_eval_encoder_config()
4292 return !0; in state_eval_encoder_config()
4301 return !0; in state_check_disable_encoder_run()
4306 return !0; in state_check_disable_encoder_run()
4315 return !0; in state_check_disable_encoder_run()
4327 return !0; in state_check_disable_encoder_run()
4332 return !0; in state_check_disable_encoder_run()
4337 return 0; in state_check_disable_encoder_run()
4346 return 0; in state_check_enable_encoder_run()
4351 return 0; in state_check_enable_encoder_run()
4359 return !0; in state_check_enable_encoder_run()
4374 return !0; in state_check_enable_encoder_run()
4383 return 0; in state_check_enable_encoder_run()
4391 if (!state_check_disable_encoder_run(hdw)) return 0; in state_eval_encoder_run()
4394 if (pvr2_encoder_stop(hdw) < 0) return !0; in state_eval_encoder_run()
4396 hdw->state_encoder_run = 0; in state_eval_encoder_run()
4398 if (!state_check_enable_encoder_run(hdw)) return 0; in state_eval_encoder_run()
4399 if (pvr2_encoder_start(hdw) < 0) return !0; in state_eval_encoder_run()
4400 hdw->state_encoder_run = !0; in state_eval_encoder_run()
4408 return !0; in state_eval_encoder_run()
4416 hdw->state_decoder_quiescent = !0; in pvr2_hdw_quiescent_timeout()
4418 hdw->state_stale = !0; in pvr2_hdw_quiescent_timeout()
4427 hdw->state_decoder_ready = !0; in pvr2_hdw_decoder_stabilization_timeout()
4429 hdw->state_stale = !0; in pvr2_hdw_decoder_stabilization_timeout()
4438 hdw->state_encoder_waitok = !0; in pvr2_hdw_encoder_wait_timeout()
4440 hdw->state_stale = !0; in pvr2_hdw_encoder_wait_timeout()
4450 hdw->state_encoder_runok = !0; in pvr2_hdw_encoder_run_timeout()
4452 hdw->state_stale = !0; in pvr2_hdw_encoder_run_timeout()
4465 hdw->state_pathway_ok) return 0; in state_eval_decoder_run()
4468 pvr2_decoder_enable(hdw,0); in state_eval_decoder_run()
4470 hdw->state_decoder_quiescent = 0; in state_eval_decoder_run()
4471 hdw->state_decoder_run = 0; in state_eval_decoder_run()
4478 hdw->state_decoder_ready = 0; in state_eval_decoder_run()
4502 return 0; in state_eval_decoder_run()
4510 !hdw->state_encoder_ok) return 0; in state_eval_decoder_run()
4512 if (hdw->flag_decoder_missed) return 0; in state_eval_decoder_run()
4513 if (pvr2_decoder_enable(hdw,!0) < 0) return 0; in state_eval_decoder_run()
4514 hdw->state_decoder_quiescent = 0; in state_eval_decoder_run()
4515 hdw->state_decoder_ready = 0; in state_eval_decoder_run()
4516 hdw->state_decoder_run = !0; in state_eval_decoder_run()
4523 hdw->state_decoder_ready = !0; in state_eval_decoder_run()
4529 return !0; in state_eval_decoder_run()
4537 int fl = !0; in state_eval_usbstream_run()
4549 return 0; in state_eval_usbstream_run()
4551 pvr2_hdw_cmd_usbstream(hdw,0); in state_eval_usbstream_run()
4552 hdw->state_usbstream_run = 0; in state_eval_usbstream_run()
4556 !hdw->state_pathway_ok) return 0; in state_eval_usbstream_run()
4559 !hdw->state_encoder_run) return 0; in state_eval_usbstream_run()
4562 if (!hdw->state_encoder_ok) return 0; in state_eval_usbstream_run()
4563 if (hdw->state_encoder_run) return 0; in state_eval_usbstream_run()
4571 if (!hdw->state_encoder_runok) return 0; in state_eval_usbstream_run()
4574 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0; in state_eval_usbstream_run()
4575 hdw->state_usbstream_run = !0; in state_eval_usbstream_run()
4578 return !0; in state_eval_usbstream_run()
4586 hdw->state_pipeline_pause) return 0; in state_eval_pipeline_config()
4588 return !0; in state_eval_pipeline_config()
4598 int updatedFl = 0; in state_update_pipeline_state()
4606 updatedFl = !0; in state_update_pipeline_state()
4609 hdw->state_pipeline_pause = 0; in state_update_pipeline_state()
4610 updatedFl = !0; in state_update_pipeline_state()
4634 int state_updated = 0; in pvr2_hdw_state_update()
4637 if (!hdw->state_stale) return 0; in pvr2_hdw_state_update()
4640 hdw->state_stale = 0; in pvr2_hdw_state_update()
4641 return !0; in pvr2_hdw_state_update()
4651 check_flag = 0; in pvr2_hdw_state_update()
4654 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) { in pvr2_hdw_state_update()
4656 check_flag = !0; in pvr2_hdw_state_update()
4657 state_updated = !0; in pvr2_hdw_state_update()
4662 hdw->state_stale = 0; in pvr2_hdw_state_update()
4672 unsigned int tcnt = 0; in print_input_mask()
4673 for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) { in print_input_mask()
4700 case 0: in pvr2_hdw_report_unlocked()
4755 unsigned int tcnt = 0; in pvr2_hdw_report_unlocked()
4781 0); in pvr2_hdw_report_unlocked()
4800 return 0; in pvr2_hdw_report_unlocked()
4811 unsigned int tcnt = 0; in pvr2_hdw_report_clients()
4851 bcnt = 0; in pvr2_hdw_state_report()
4853 for (idx = 0; ; idx++) { in pvr2_hdw_state_report()
4858 buf[0] = '\n'; ccnt = 1; in pvr2_hdw_state_report()
4874 for (idx = 0; ; idx++) { in pvr2_hdw_state_log_state()
4883 ucnt = 0; in pvr2_hdw_state_log_state()
4885 lcnt = 0; in pvr2_hdw_state_log_state()
4900 int state_updated = 0; in pvr2_hdw_state_eval()
4901 int callback_flag = 0; in pvr2_hdw_state_eval()
4941 state_updated = !0; in pvr2_hdw_state_eval()
4942 callback_flag = !0; in pvr2_hdw_state_eval()
4963 hdw->state_stale = !0; in pvr2_hdw_state_sched()
4996 "GPIO direction changing 0x%x:0x%x from 0x%x to 0x%x", in pvr2_hdw_gpio_chg_dir()
5001 "GPIO direction changing to 0x%x",nval); in pvr2_hdw_gpio_chg_dir()
5016 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x", in pvr2_hdw_gpio_chg_out()
5021 "GPIO output changing to 0x%x",nval); in pvr2_hdw_gpio_chg_out()
5030 memset(vtp, 0, sizeof(*vtp)); in pvr2_hdw_status_poll()
5033 hdw->tuner_signal_stale = 0; in pvr2_hdw_status_poll()
5038 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner, vtp); in pvr2_hdw_status_poll()
5039 …pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll type=%u strength=%u audio=0x%x cap=0x%x low=%u hi… in pvr2_hdw_status_poll()
5046 hdw->cropcap_stale = 0; in pvr2_hdw_status_poll()
5066 hdw->input_dirty = !0; in pvr2_hdw_set_input()
5073 hdw->freqSelector = 0; in pvr2_hdw_set_input()
5074 hdw->freqDirty = !0; in pvr2_hdw_set_input()
5078 hdw->freqDirty = !0; in pvr2_hdw_set_input()
5080 return 0; in pvr2_hdw_set_input()
5088 int ret = 0; in pvr2_hdw_set_input_allowed()
5113 for (idx = 0; idx < (sizeof(m) << 3); idx++) { in pvr2_hdw_set_input_allowed()
5118 } while (0); in pvr2_hdw_set_input_allowed()
5129 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR; in pvr2_hdw_get_eeprom_addr()
5133 if (result < 0) break; in pvr2_hdw_get_eeprom_addr()
5134 result = hdw->cmd_buffer[0]; in pvr2_hdw_get_eeprom_addr()
5135 } while(0); LOCK_GIVE(hdw->ctl_lock); in pvr2_hdw_get_eeprom_addr()