Lines Matching +full:output +full:- +full:enable
1 // SPDX-License-Identifier: GPL-2.0
3 * camss-vfe-4-7.c
5 * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v4.7
7 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
8 * Copyright (C) 2015-2018 Linaro Ltd.
15 #include "camss-vfe.h"
244 u32 hw_version = readl_relaxed(vfe->base + VFE_0_HW_VERSION); in vfe_hw_version_read()
261 u32 bits = readl_relaxed(vfe->base + reg); in vfe_reg_clr()
263 writel_relaxed(bits & ~clr_bits, vfe->base + reg); in vfe_reg_clr()
268 u32 bits = readl_relaxed(vfe->base + reg); in vfe_reg_set()
270 writel_relaxed(bits | set_bits, vfe->base + reg); in vfe_reg_set()
286 writel_relaxed(BIT(31), vfe->base + VFE_0_IRQ_MASK_0); in vfe_global_reset()
288 writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD); in vfe_global_reset()
294 vfe->base + VFE_0_BUS_BDG_CMD); in vfe_halt_request()
299 writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD); in vfe_halt_clear()
302 static void vfe_wm_enable(struct vfe_device *vfe, u8 wm, u8 enable) in vfe_wm_enable() argument
304 if (enable) in vfe_wm_enable()
312 static void vfe_wm_frame_based(struct vfe_device *vfe, u8 wm, u8 enable) in vfe_wm_frame_based() argument
314 if (enable) in vfe_wm_frame_based()
322 #define CALC_WORD(width, M, N) (((width) * (M) + (N) - 1) / (N))
354 switch (pix->pixelformat) { in vfe_get_wm_sizes()
357 *width = pix->width; in vfe_get_wm_sizes()
358 *height = pix->height; in vfe_get_wm_sizes()
359 *bytesperline = pix->plane_fmt[0].bytesperline; in vfe_get_wm_sizes()
365 *width = pix->width; in vfe_get_wm_sizes()
366 *height = pix->height; in vfe_get_wm_sizes()
367 *bytesperline = pix->plane_fmt[0].bytesperline; in vfe_get_wm_sizes()
373 *width = pix->width; in vfe_get_wm_sizes()
374 *height = pix->height; in vfe_get_wm_sizes()
375 *bytesperline = pix->plane_fmt[plane].bytesperline; in vfe_get_wm_sizes()
383 u8 plane, u32 enable) in vfe_wm_line_based() argument
387 if (enable) { in vfe_wm_line_based()
392 wpl = vfe_word_per_line_by_pixel(pix->pixelformat, width); in vfe_wm_line_based()
394 reg = height - 1; in vfe_wm_line_based()
395 reg |= ((wpl + 3) / 4 - 1) << 16; in vfe_wm_line_based()
397 writel_relaxed(reg, vfe->base + in vfe_wm_line_based()
403 reg |= (height - 1) << 2; in vfe_wm_line_based()
406 writel_relaxed(reg, vfe->base + in vfe_wm_line_based()
409 writel_relaxed(0, vfe->base + in vfe_wm_line_based()
411 writel_relaxed(0, vfe->base + in vfe_wm_line_based()
420 reg = readl_relaxed(vfe->base + in vfe_wm_set_framedrop_period()
429 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); in vfe_wm_set_framedrop_period()
436 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(wm)); in vfe_wm_set_framedrop_pattern()
446 writel_relaxed(reg, vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(wm)); in vfe_wm_set_ub_cfg()
452 writel_relaxed(VFE_0_BUS_CMD_Mx_RLD_CMD(wm), vfe->base + VFE_0_BUS_CMD); in vfe_bus_reload_wm()
459 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(wm)); in vfe_wm_set_ping_addr()
465 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(wm)); in vfe_wm_set_pong_addr()
472 reg = readl_relaxed(vfe->base + VFE_0_BUS_PING_PONG_STATUS); in vfe_wm_get_ping_pong_status()
477 static void vfe_bus_enable_wr_if(struct vfe_device *vfe, u8 enable) in vfe_bus_enable_wr_if() argument
479 if (enable) in vfe_bus_enable_wr_if()
480 writel_relaxed(0x101, vfe->base + VFE_0_BUS_CFG); in vfe_bus_enable_wr_if()
482 writel_relaxed(0, vfe->base + VFE_0_BUS_CFG); in vfe_bus_enable_wr_if()
523 vfe->base + in vfe_wm_set_subsample()
557 static void vfe_set_xbar_cfg(struct vfe_device *vfe, struct vfe_output *output, in vfe_set_xbar_cfg() argument
558 u8 enable) in vfe_set_xbar_cfg() argument
560 struct vfe_line *line = container_of(output, struct vfe_line, output); in vfe_set_xbar_cfg()
561 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; in vfe_set_xbar_cfg()
572 if (output->wm_idx[0] % 2 == 1) in vfe_set_xbar_cfg()
575 if (enable) in vfe_set_xbar_cfg()
577 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]), in vfe_set_xbar_cfg()
581 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]), in vfe_set_xbar_cfg()
588 if (output->wm_idx[1] % 2 == 1) in vfe_set_xbar_cfg()
591 if (enable) in vfe_set_xbar_cfg()
593 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[1]), in vfe_set_xbar_cfg()
597 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[1]), in vfe_set_xbar_cfg()
610 if (output->wm_idx[0] % 2 == 1) in vfe_set_xbar_cfg()
613 if (enable) in vfe_set_xbar_cfg()
615 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]), in vfe_set_xbar_cfg()
619 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]), in vfe_set_xbar_cfg()
628 u8 enable) in vfe_set_realign_cfg() argument
630 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; in vfe_set_realign_cfg()
637 if (enable) { in vfe_set_realign_cfg()
651 writel_relaxed(val, vfe->base + VFE_0_REALIGN_BUF_CFG); in vfe_set_realign_cfg()
665 vfe->reg_update |= VFE_0_REG_UPDATE_line_n(line_id); in vfe_reg_update()
667 writel_relaxed(vfe->reg_update, vfe->base + VFE_0_REG_UPDATE); in vfe_reg_update()
674 vfe->reg_update &= ~VFE_0_REG_UPDATE_line_n(line_id); in vfe_reg_update_clear()
678 enum vfe_line_id line_id, u8 enable) in vfe_enable_irq_wm_line() argument
685 if (enable) { in vfe_enable_irq_wm_line()
695 enum vfe_line_id line_id, u8 enable) in vfe_enable_irq_pix_line() argument
697 struct vfe_output *output = &vfe->line[line_id].output; in vfe_enable_irq_pix_line() local
708 for (i = 0; i < output->wm_num; i++) { in vfe_enable_irq_pix_line()
710 output->wm_idx[i]); in vfe_enable_irq_pix_line()
711 comp_mask |= (1 << output->wm_idx[i]) << comp * 8; in vfe_enable_irq_pix_line()
714 if (enable) { in vfe_enable_irq_pix_line()
739 writel_relaxed(VFE_0_DEMUX_CFG_PERIOD, vfe->base + VFE_0_DEMUX_CFG); in vfe_set_demux_cfg()
742 writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_0); in vfe_set_demux_cfg()
745 writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_1); in vfe_set_demux_cfg()
747 switch (line->fmt[MSM_VFE_PAD_SINK].code) { in vfe_set_demux_cfg()
767 writel_relaxed(even_cfg, vfe->base + VFE_0_DEMUX_EVEN_CFG); in vfe_set_demux_cfg()
768 writel_relaxed(odd_cfg, vfe->base + VFE_0_DEMUX_ODD_CFG); in vfe_set_demux_cfg()
771 static inline u8 vfe_calc_interp_reso(u16 input, u16 output) in vfe_calc_interp_reso() argument
773 if (input / output >= 16) in vfe_calc_interp_reso()
776 if (input / output >= 8) in vfe_calc_interp_reso()
779 if (input / output >= 4) in vfe_calc_interp_reso()
787 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; in vfe_set_scale_cfg()
789 u16 input, output; in vfe_set_scale_cfg() local
793 writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_Y_CFG); in vfe_set_scale_cfg()
795 input = line->fmt[MSM_VFE_PAD_SINK].width - 1; in vfe_set_scale_cfg()
796 output = line->compose.width - 1; in vfe_set_scale_cfg()
797 reg = (output << 16) | input; in vfe_set_scale_cfg()
798 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE); in vfe_set_scale_cfg()
800 interp_reso = vfe_calc_interp_reso(input, output); in vfe_set_scale_cfg()
801 phase_mult = input * (1 << (14 + interp_reso)) / output; in vfe_set_scale_cfg()
803 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_PHASE); in vfe_set_scale_cfg()
805 input = line->fmt[MSM_VFE_PAD_SINK].height - 1; in vfe_set_scale_cfg()
806 output = line->compose.height - 1; in vfe_set_scale_cfg()
807 reg = (output << 16) | input; in vfe_set_scale_cfg()
808 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE); in vfe_set_scale_cfg()
810 interp_reso = vfe_calc_interp_reso(input, output); in vfe_set_scale_cfg()
811 phase_mult = input * (1 << (14 + interp_reso)) / output; in vfe_set_scale_cfg()
813 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_PHASE); in vfe_set_scale_cfg()
815 writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_CBCR_CFG); in vfe_set_scale_cfg()
817 input = line->fmt[MSM_VFE_PAD_SINK].width - 1; in vfe_set_scale_cfg()
818 output = line->compose.width / 2 - 1; in vfe_set_scale_cfg()
819 reg = (output << 16) | input; in vfe_set_scale_cfg()
820 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE); in vfe_set_scale_cfg()
822 interp_reso = vfe_calc_interp_reso(input, output); in vfe_set_scale_cfg()
823 phase_mult = input * (1 << (14 + interp_reso)) / output; in vfe_set_scale_cfg()
825 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_PHASE); in vfe_set_scale_cfg()
827 input = line->fmt[MSM_VFE_PAD_SINK].height - 1; in vfe_set_scale_cfg()
828 output = line->compose.height - 1; in vfe_set_scale_cfg()
830 output = line->compose.height / 2 - 1; in vfe_set_scale_cfg()
831 reg = (output << 16) | input; in vfe_set_scale_cfg()
832 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE); in vfe_set_scale_cfg()
834 interp_reso = vfe_calc_interp_reso(input, output); in vfe_set_scale_cfg()
835 phase_mult = input * (1 << (14 + interp_reso)) / output; in vfe_set_scale_cfg()
837 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_PHASE); in vfe_set_scale_cfg()
842 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; in vfe_set_crop_cfg()
846 first = line->crop.left; in vfe_set_crop_cfg()
847 last = line->crop.left + line->crop.width - 1; in vfe_set_crop_cfg()
849 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_WIDTH); in vfe_set_crop_cfg()
851 first = line->crop.top; in vfe_set_crop_cfg()
852 last = line->crop.top + line->crop.height - 1; in vfe_set_crop_cfg()
854 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_HEIGHT); in vfe_set_crop_cfg()
856 first = line->crop.left / 2; in vfe_set_crop_cfg()
857 last = line->crop.left / 2 + line->crop.width / 2 - 1; in vfe_set_crop_cfg()
859 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_WIDTH); in vfe_set_crop_cfg()
861 first = line->crop.top; in vfe_set_crop_cfg()
862 last = line->crop.top + line->crop.height - 1; in vfe_set_crop_cfg()
864 first = line->crop.top / 2; in vfe_set_crop_cfg()
865 last = line->crop.top / 2 + line->crop.height / 2 - 1; in vfe_set_crop_cfg()
868 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_HEIGHT); in vfe_set_crop_cfg()
877 writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MAX_CFG); in vfe_set_clamp_cfg()
883 writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MIN_CFG); in vfe_set_clamp_cfg()
891 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_0); in vfe_set_qos()
892 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_1); in vfe_set_qos()
893 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_2); in vfe_set_qos()
894 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_3); in vfe_set_qos()
895 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_4); in vfe_set_qos()
896 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_5); in vfe_set_qos()
897 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_6); in vfe_set_qos()
898 writel_relaxed(val7, vfe->base + VFE_0_BUS_BDG_QOS_CFG_7); in vfe_set_qos()
906 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_0); in vfe_set_ds()
907 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_1); in vfe_set_ds()
908 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_2); in vfe_set_ds()
909 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_3); in vfe_set_ds()
910 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_4); in vfe_set_ds()
911 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_5); in vfe_set_ds()
912 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_6); in vfe_set_ds()
913 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_7); in vfe_set_ds()
914 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_8); in vfe_set_ds()
915 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_9); in vfe_set_ds()
916 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_10); in vfe_set_ds()
917 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_11); in vfe_set_ds()
918 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_12); in vfe_set_ds()
919 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_13); in vfe_set_ds()
920 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_14); in vfe_set_ds()
921 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_15); in vfe_set_ds()
922 writel_relaxed(val16, vfe->base + VFE_0_BUS_BDG_DS_CFG_16); in vfe_set_ds()
925 static void vfe_set_cgc_override(struct vfe_device *vfe, u8 wm, u8 enable) in vfe_set_cgc_override() argument
934 switch (line->fmt[MSM_VFE_PAD_SINK].code) { in vfe_set_camif_cfg()
951 writel_relaxed(val, vfe->base + VFE_0_CORE_CFG); in vfe_set_camif_cfg()
953 val = line->fmt[MSM_VFE_PAD_SINK].width * 2 - 1; in vfe_set_camif_cfg()
954 val |= (line->fmt[MSM_VFE_PAD_SINK].height - 1) << 16; in vfe_set_camif_cfg()
955 writel_relaxed(val, vfe->base + VFE_0_CAMIF_FRAME_CFG); in vfe_set_camif_cfg()
957 val = line->fmt[MSM_VFE_PAD_SINK].width * 2 - 1; in vfe_set_camif_cfg()
958 writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_WIDTH_CFG); in vfe_set_camif_cfg()
960 val = line->fmt[MSM_VFE_PAD_SINK].height - 1; in vfe_set_camif_cfg()
961 writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_HEIGHT_CFG); in vfe_set_camif_cfg()
964 writel_relaxed(val, vfe->base + VFE_0_CAMIF_SUBSAMPLE_CFG); in vfe_set_camif_cfg()
967 writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_FRAMEDROP_PATTERN); in vfe_set_camif_cfg()
970 writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN); in vfe_set_camif_cfg()
976 writel_relaxed(val, vfe->base + VFE_0_CAMIF_CFG); in vfe_set_camif_cfg()
979 static void vfe_set_camif_cmd(struct vfe_device *vfe, u8 enable) in vfe_set_camif_cmd() argument
984 writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); in vfe_set_camif_cmd()
987 if (enable) in vfe_set_camif_cmd()
992 writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); in vfe_set_camif_cmd()
995 static void vfe_set_module_cfg(struct vfe_device *vfe, u8 enable) in vfe_set_module_cfg() argument
1002 if (enable) { in vfe_set_module_cfg()
1016 ret = readl_poll_timeout(vfe->base + VFE_0_CAMIF_STATUS, in vfe_camif_wait_for_stop()
1029 *value0 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_0); in vfe_isr_read()
1030 *value1 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_1); in vfe_isr_read()
1032 writel_relaxed(*value0, vfe->base + VFE_0_IRQ_CLEAR_0); in vfe_isr_read()
1033 writel_relaxed(*value1, vfe->base + VFE_0_IRQ_CLEAR_1); in vfe_isr_read()
1036 writel_relaxed(VFE_0_IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_0_IRQ_CMD); in vfe_isr_read()
1041 u32 violation = readl_relaxed(vfe->base + VFE_0_VIOLATION_STATUS); in vfe_violation_read()
1047 * vfe_isr - ISPIF module interrupt handler
1059 vfe->ops->isr_read(vfe, &value0, &value1); in vfe_isr()
1065 vfe->isr_ops.reset_ack(vfe); in vfe_isr()
1068 vfe->ops->violation_read(vfe); in vfe_isr()
1071 vfe->isr_ops.halt_ack(vfe); in vfe_isr()
1075 vfe->isr_ops.reg_update(vfe, i); in vfe_isr()
1078 vfe->isr_ops.sof(vfe, VFE_LINE_PIX); in vfe_isr()
1082 vfe->isr_ops.sof(vfe, i); in vfe_isr()
1086 vfe->isr_ops.comp_done(vfe, i); in vfe_isr()
1087 for (j = 0; j < ARRAY_SIZE(vfe->wm_output_map); j++) in vfe_isr()
1088 if (vfe->wm_output_map[j] == VFE_LINE_PIX) in vfe_isr()
1094 vfe->isr_ops.wm_done(vfe, i); in vfe_isr()