Lines Matching +full:0 +full:- +full:9
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2012-2015 Cisco Systems, Inc. and/or its affiliates.
11 #include "cobalt-cpld.h"
17 return cobalt_bus_read32(cobalt->bar1, ADRS(offset)); in cpld_read()
22 return cobalt_bus_write32(cobalt->bar1, ADRS(offset), val); in cpld_write()
31 cobalt_info("\t\tSystem control: 0x%04x (0x0f00)\n", in cpld_info_ver3()
32 cpld_read(cobalt, 0)); in cpld_info_ver3()
34 cobalt_info("\t\tClock control: 0x%04x (0x0000)\n", in cpld_info_ver3()
35 cpld_read(cobalt, 0x04)); in cpld_info_ver3()
36 …cobalt_info("CPLD HSMA Clk Osc register (read/write) - Must set wr trigger to load default values\… in cpld_info_ver3()
37 cobalt_info("\t\tRegister #7:\t0x%04x (0x0022)\n", in cpld_info_ver3()
38 cpld_read(cobalt, 0x08)); in cpld_info_ver3()
39 cobalt_info("\t\tRegister #8:\t0x%04x (0x0047)\n", in cpld_info_ver3()
40 cpld_read(cobalt, 0x0c)); in cpld_info_ver3()
41 cobalt_info("\t\tRegister #9:\t0x%04x (0x00fa)\n", in cpld_info_ver3()
42 cpld_read(cobalt, 0x10)); in cpld_info_ver3()
43 cobalt_info("\t\tRegister #10:\t0x%04x (0x0061)\n", in cpld_info_ver3()
44 cpld_read(cobalt, 0x14)); in cpld_info_ver3()
45 cobalt_info("\t\tRegister #11:\t0x%04x (0x001e)\n", in cpld_info_ver3()
46 cpld_read(cobalt, 0x18)); in cpld_info_ver3()
47 cobalt_info("\t\tRegister #12:\t0x%04x (0x0045)\n", in cpld_info_ver3()
48 cpld_read(cobalt, 0x1c)); in cpld_info_ver3()
50 cpld_read(cobalt, 0x20)); in cpld_info_ver3()
52 cpld_read(cobalt, 0x24)); in cpld_info_ver3()
54 cobalt_info("\t\tSystem status: 0x%04x\n", in cpld_info_ver3()
55 cpld_read(cobalt, 0x28)); in cpld_info_ver3()
57 cobalt_info("\t\tBoard serial number: 0x%04x\n", in cpld_info_ver3()
58 cpld_read(cobalt, 0x2c)); in cpld_info_ver3()
59 cobalt_info("\t\tMAXII program revision: 0x%04x\n", in cpld_info_ver3()
60 cpld_read(cobalt, 0x30)); in cpld_info_ver3()
63 cpld_read(cobalt, 0x34) / 4); in cpld_info_ver3()
65 cpld_read(cobalt, 0x38) / 4); in cpld_info_ver3()
66 rd = cpld_read(cobalt, 0x3c); in cpld_info_ver3()
69 rd = cpld_read(cobalt, 0x40); in cpld_info_ver3()
72 rd = cpld_read(cobalt, 0x44); in cpld_info_ver3()
75 rd = cpld_read(cobalt, 0x48); in cpld_info_ver3()
78 rd = cpld_read(cobalt, 0x4c); in cpld_info_ver3()
81 rd = cpld_read(cobalt, 0x50); in cpld_info_ver3()
84 rd = cpld_read(cobalt, 0x54); in cpld_info_ver3()
86 cobalt_info("\t\tADC ch8 0V9: %u,%03uV\n", tmp / 1000, tmp % 1000); in cpld_info_ver3()
91 u32 rev = cpld_read(cobalt, 0x30); in cobalt_cpld_status()
108 #define SI570_CLOCK_CTRL 0x04
109 #define S01755_REG_CLOCK_CTRL_BITMAP_CLKHSMA_WR_TRIGGER 0x200
110 #define S01755_REG_CLOCK_CTRL_BITMAP_CLKHSMA_RST_TRIGGER 0x100
111 #define S01755_REG_CLOCK_CTRL_BITMAP_CLKHSMA_FPGA_CTRL 0x80
112 #define S01755_REG_CLOCK_CTRL_BITMAP_CLKHSMA_EN 0x40
114 #define SI570_REG7 0x08
115 #define SI570_REG8 0x0c
116 #define SI570_REG9 0x10
117 #define SI570_REG10 0x14
118 #define SI570_REG11 0x18
119 #define SI570_REG12 0x1c
120 #define SI570_REG135 0x20
121 #define SI570_REG137 0x24
133 { 7, 7, 1 }, { 8, 4, 2 }, { 9, 9, 1 },
135 { 14, 7, 2 }, { 16, 4, 4 }, { 18, 9, 2 },
140 { 54, 9, 6 }, { 56, 4, 14 }, { 60, 5, 12 },
150 { 160, 4, 40 }, { 162, 9, 18 }, { 168, 4, 42 },
154 { 198, 9, 22 }, { 200, 4, 50 }, { 204, 6, 34 },
157 { 230, 5, 46 }, { 232, 4, 58 }, { 234, 9, 26 },
165 { 306, 9, 34 }, { 308, 11, 28 }, { 310, 5, 62 },
168 { 336, 4, 84 }, { 340, 5, 68 }, { 342, 9, 38 },
176 { 414, 9, 46 }, { 416, 4, 104 }, { 418, 11, 38 },
183 { 484, 11, 44 }, { 486, 9, 54 }, { 488, 4, 122 },
187 { 518, 7, 74 }, { 520, 5, 104 }, { 522, 9, 58 },
190 { 552, 6, 92 }, { 558, 9, 62 }, { 560, 5, 112 },
199 { 666, 9, 74 }, { 672, 6, 112 }, { 682, 11, 62 },
201 { 700, 7, 100 }, { 702, 9, 78 }, { 704, 11, 64 },
204 { 738, 9, 82 }, { 742, 7, 106 }, { 744, 6, 124 },
206 { 770, 11, 70 }, { 774, 9, 86 }, { 784, 7, 112 },
207 { 792, 11, 72 }, { 798, 7, 114 }, { 810, 9, 90 },
209 { 828, 9, 92 }, { 836, 11, 76 }, { 840, 7, 120 },
210 { 846, 9, 94 }, { 854, 7, 122 }, { 858, 11, 78 },
211 { 864, 9, 96 }, { 868, 7, 124 }, { 880, 11, 80 },
212 { 882, 7, 126 }, { 896, 7, 128 }, { 900, 9, 100 },
213 { 902, 11, 82 }, { 918, 9, 102 }, { 924, 11, 84 },
214 { 936, 9, 104 }, { 946, 11, 86 }, { 954, 9, 106 },
215 { 968, 11, 88 }, { 972, 9, 108 }, { 990, 11, 90 },
216 { 1008, 9, 112 }, { 1012, 11, 92 }, { 1026, 9, 114 },
217 { 1034, 11, 94 }, { 1044, 9, 116 }, { 1056, 11, 96 },
218 { 1062, 9, 118 }, { 1078, 11, 98 }, { 1080, 9, 120 },
219 { 1098, 9, 122 }, { 1100, 11, 100 }, { 1116, 9, 124 },
220 { 1122, 11, 102 }, { 1134, 9, 126 }, { 1144, 11, 104 },
221 { 1152, 9, 128 }, { 1166, 11, 106 }, { 1188, 11, 108 },
233 unsigned delta = 0xffffffff; in cobalt_cpld_set_freq()
234 unsigned i_best = 0; in cobalt_cpld_set_freq()
238 int found = 0; in cobalt_cpld_set_freq()
242 for (i = 0; i < ARRAY_SIZE(multipliers); i++) { in cobalt_cpld_set_freq()
259 n1 = multipliers[i_best].n1 - 1; in cobalt_cpld_set_freq()
260 hsdiv = multipliers[i_best].hsdiv - 4; in cobalt_cpld_set_freq()
267 regs[0] = (hsdiv << 5) | (n1 >> 2); in cobalt_cpld_set_freq()
268 regs[1] = ((n1 & 0x3) << 6) | (rfreq >> 32); in cobalt_cpld_set_freq()
269 regs[2] = (rfreq >> 24) & 0xff; in cobalt_cpld_set_freq()
270 regs[3] = (rfreq >> 16) & 0xff; in cobalt_cpld_set_freq()
271 regs[4] = (rfreq >> 8) & 0xff; in cobalt_cpld_set_freq()
272 regs[5] = rfreq & 0xff; in cobalt_cpld_set_freq()
278 0x01, 0xc7, 0xfc, 0x7f, 0x53, 0x62). in cobalt_cpld_set_freq()
283 while (retries--) { in cobalt_cpld_set_freq()
290 cpld_write(cobalt, SI570_REG7, regs[0]); in cobalt_cpld_set_freq()
304 read_regs[0] = cpld_read(cobalt, SI570_REG7); in cobalt_cpld_set_freq()
323 if (2 - retries) in cobalt_cpld_set_freq()
324 cobalt_info("Needed %d retries\n", 2 - retries); in cobalt_cpld_set_freq()