Lines Matching +full:adc +full:- +full:alt +full:- +full:channel
1 // SPDX-License-Identifier: GPL-2.0-only
3 * adv7842 - Analog Devices ADV7842 video decoder driver
10 * REF_01 - Analog devices, ADV7842,
12 * REF_02 - Analog devices, Software User Guide, UG-206,
14 * REF_03 - Analog devices, Hardware User Guide, UG-214,
15 * ADV7842 Fast Switching 2:1 HDMI 1.4 Receiver with 3D-Comb
27 #include <linux/v4l2-dv-timings.h>
30 #include <media/v4l2-device.h>
31 #include <media/v4l2-event.h>
32 #include <media/v4l2-ctrls.h>
33 #include <media/v4l2-dv-timings.h>
38 MODULE_PARM_DESC(debug, "debug level (0-2)");
245 /* ----------------------------------------------------------------------- */
254 return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd; in to_sd()
278 /* ----------------------------------------------------------------------- */
285 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags, in adv_smbus_read_byte_data_check()
291 client->addr, command); in adv_smbus_read_byte_data_check()
292 return -EIO; in adv_smbus_read_byte_data_check()
309 return -EIO; in adv_smbus_read_byte_data()
321 err = i2c_smbus_xfer(client->adapter, client->addr, in adv_smbus_write_byte_data()
322 client->flags, in adv_smbus_write_byte_data()
330 client->addr, command, value); in adv_smbus_write_byte_data()
340 i2c_smbus_xfer(client->adapter, client->addr, in adv_smbus_write_byte_no_check()
341 client->flags, in adv_smbus_write_byte_no_check()
355 return i2c_smbus_xfer(client->adapter, client->addr, client->flags, in adv_smbus_write_i2c_block_data()
360 /* ----------------------------------------------------------------------- */
391 return adv_smbus_read_byte_data(state->i2c_avlink, reg); in avlink_read()
398 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val); in avlink_write()
405 return adv_smbus_read_byte_data(state->i2c_cec, reg); in cec_read()
412 return adv_smbus_write_byte_data(state->i2c_cec, reg, val); in cec_write()
424 return adv_smbus_read_byte_data(state->i2c_infoframe, reg); in infoframe_read()
431 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val); in infoframe_write()
438 return adv_smbus_read_byte_data(state->i2c_sdp_io, reg); in sdp_io_read()
445 return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val); in sdp_io_write()
457 return adv_smbus_read_byte_data(state->i2c_sdp, reg); in sdp_read()
464 return adv_smbus_write_byte_data(state->i2c_sdp, reg, val); in sdp_write()
476 return adv_smbus_read_byte_data(state->i2c_afe, reg); in afe_read()
483 return adv_smbus_write_byte_data(state->i2c_afe, reg, val); in afe_write()
495 return adv_smbus_read_byte_data(state->i2c_repeater, reg); in rep_read()
502 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val); in rep_write()
514 return adv_smbus_read_byte_data(state->i2c_edid, reg); in edid_read()
521 return adv_smbus_write_byte_data(state->i2c_edid, reg, val); in edid_write()
528 return adv_smbus_read_byte_data(state->i2c_hdmi, reg); in hdmi_read()
535 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val); in hdmi_write()
547 return adv_smbus_read_byte_data(state->i2c_cp, reg); in cp_read()
554 return adv_smbus_write_byte_data(state->i2c_cp, reg, val); in cp_write()
566 return adv_smbus_read_byte_data(state->i2c_vdp, reg); in vdp_read()
573 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val); in vdp_write()
587 /* -----------------------------------------------------------------------------
645 /* ----------------------------------------------------------------------- */
651 return ((state->mode == ADV7842_MODE_RGB) || in is_analog_input()
652 (state->mode == ADV7842_MODE_COMP)); in is_analog_input()
659 return state->mode == ADV7842_MODE_HDMI; in is_digital_input()
691 /* ----------------------------------------------------------------------- */
710 struct v4l2_subdev *sd = &state->sd; in adv7842_delayed_work_enable_hotplug()
711 int present = state->hdmi_edid.present; in adv7842_delayed_work_enable_hotplug()
728 const u8 *val = state->vga_edid.edid; in edid_write_vga_segment()
744 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i, in edid_write_vga_segment()
761 return -EIO; in edid_write_vga_segment()
765 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 5); in edid_write_vga_segment()
774 const u8 *edid = state->hdmi_edid.edid; in edid_write_hdmi_segment()
789 if (!state->hdmi_edid.present) { in edid_write_hdmi_segment()
790 cec_phys_addr_invalidate(state->cec_adap); in edid_write_hdmi_segment()
804 return -EINVAL; in edid_write_hdmi_segment()
810 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i, in edid_write_hdmi_segment()
828 rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present); in edid_write_hdmi_segment()
831 if (rep_read(sd, 0x7d) & state->hdmi_edid.present) in edid_write_hdmi_segment()
838 return -EIO; in edid_write_hdmi_segment()
840 cec_s_phys_addr(state->cec_adap, pa, false); in edid_write_hdmi_segment()
843 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 5); in edid_write_hdmi_segment()
848 /* ----------------------------------------------------------------------- */
853 v4l2_info(sd, "0x000-0x0ff: IO Map\n"); in adv7842_inv_register()
854 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); in adv7842_inv_register()
855 v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); in adv7842_inv_register()
856 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); in adv7842_inv_register()
857 v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n"); in adv7842_inv_register()
858 v4l2_info(sd, "0x500-0x5ff: SDP Map\n"); in adv7842_inv_register()
859 v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); in adv7842_inv_register()
860 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); in adv7842_inv_register()
861 v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); in adv7842_inv_register()
862 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); in adv7842_inv_register()
863 v4l2_info(sd, "0xa00-0xaff: CP Map\n"); in adv7842_inv_register()
864 v4l2_info(sd, "0xb00-0xbff: VDP Map\n"); in adv7842_inv_register()
870 reg->size = 1; in adv7842_g_register()
871 switch (reg->reg >> 8) { in adv7842_g_register()
873 reg->val = io_read(sd, reg->reg & 0xff); in adv7842_g_register()
876 reg->val = avlink_read(sd, reg->reg & 0xff); in adv7842_g_register()
879 reg->val = cec_read(sd, reg->reg & 0xff); in adv7842_g_register()
882 reg->val = infoframe_read(sd, reg->reg & 0xff); in adv7842_g_register()
885 reg->val = sdp_io_read(sd, reg->reg & 0xff); in adv7842_g_register()
888 reg->val = sdp_read(sd, reg->reg & 0xff); in adv7842_g_register()
891 reg->val = afe_read(sd, reg->reg & 0xff); in adv7842_g_register()
894 reg->val = rep_read(sd, reg->reg & 0xff); in adv7842_g_register()
897 reg->val = edid_read(sd, reg->reg & 0xff); in adv7842_g_register()
900 reg->val = hdmi_read(sd, reg->reg & 0xff); in adv7842_g_register()
903 reg->val = cp_read(sd, reg->reg & 0xff); in adv7842_g_register()
906 reg->val = vdp_read(sd, reg->reg & 0xff); in adv7842_g_register()
909 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); in adv7842_g_register()
919 u8 val = reg->val & 0xff; in adv7842_s_register()
921 switch (reg->reg >> 8) { in adv7842_s_register()
923 io_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
926 avlink_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
929 cec_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
932 infoframe_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
935 sdp_io_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
938 sdp_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
941 afe_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
944 rep_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
947 edid_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
950 hdmi_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
953 cp_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
956 vdp_write(sd, reg->reg & 0xff, val); in adv7842_s_register()
959 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); in adv7842_s_register()
974 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det); in adv7842_s_detect_tx_5v_ctrl()
995 return -1; in find_and_set_predefined_video_timings()
1023 switch (state->mode) { in configure_predefined_video_timings()
1041 __func__, state->mode); in configure_predefined_video_timings()
1042 err = -1; in configure_predefined_video_timings()
1057 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; in configure_custom_video_timings()
1058 u16 cp_start_eav = width - bt->hfrontporch; in configure_custom_video_timings()
1059 u16 cp_start_vbi = height - bt->vfrontporch + 1; in configure_custom_video_timings()
1060 u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1; in configure_custom_video_timings()
1061 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? in configure_custom_video_timings()
1062 ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0; in configure_custom_video_timings()
1070 switch (state->mode) { in configure_custom_video_timings()
1079 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ in configure_custom_video_timings()
1081 /* IO-map reg. 0x16 and 0x17 should be written in sequence */ in configure_custom_video_timings()
1087 /* active video - horizontal timing */ in configure_custom_video_timings()
1093 /* active video - vertical timing */ in configure_custom_video_timings()
1107 __func__, state->mode); in configure_custom_video_timings()
1138 if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x77, 4, offset_buf)) in adv7842_set_offset()
1167 if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x73, 4, gain_buf)) in adv7842_set_gain()
1182 __func__, state->rgb_quantization_range, in set_rgb_quantization_range()
1189 switch (state->rgb_quantization_range) { in set_rgb_quantization_range()
1191 if (state->mode == ADV7842_MODE_RGB) { in set_rgb_quantization_range()
1193 * Set RGB full range (0-255) */ in set_rgb_quantization_range()
1198 if (state->mode == ADV7842_MODE_COMP) { in set_rgb_quantization_range()
1212 /* Receiving DVI-D signal in set_rgb_quantization_range()
1215 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) { in set_rgb_quantization_range()
1216 /* RGB limited range (16-235) */ in set_rgb_quantization_range()
1219 /* RGB full range (0-255) */ in set_rgb_quantization_range()
1231 if (state->mode == ADV7842_MODE_COMP) { in set_rgb_quantization_range()
1232 /* YCrCb limited range (16-235) */ in set_rgb_quantization_range()
1240 /* RGB limited range (16-235) */ in set_rgb_quantization_range()
1245 if (state->mode == ADV7842_MODE_COMP) { in set_rgb_quantization_range()
1246 /* YCrCb full range (0-255) */ in set_rgb_quantization_range()
1254 /* RGB full range (0-255) */ in set_rgb_quantization_range()
1260 /* Adjust gain/offset for DVI-D signals only */ in set_rgb_quantization_range()
1280 switch (ctrl->id) { in adv7842_s_ctrl()
1283 cp_write(sd, 0x3c, ctrl->val); in adv7842_s_ctrl()
1284 sdp_write(sd, 0x14, ctrl->val); in adv7842_s_ctrl()
1288 cp_write(sd, 0x3a, ctrl->val); in adv7842_s_ctrl()
1289 sdp_write(sd, 0x13, ctrl->val); in adv7842_s_ctrl()
1293 cp_write(sd, 0x3b, ctrl->val); in adv7842_s_ctrl()
1294 sdp_write(sd, 0x15, ctrl->val); in adv7842_s_ctrl()
1298 cp_write(sd, 0x3d, ctrl->val); in adv7842_s_ctrl()
1299 sdp_write(sd, 0x16, ctrl->val); in adv7842_s_ctrl()
1304 afe_write(sd, 0xc8, ctrl->val); in adv7842_s_ctrl()
1307 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2)); in adv7842_s_ctrl()
1308 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2)); in adv7842_s_ctrl()
1311 u8 R = (ctrl->val & 0xff0000) >> 16; in adv7842_s_ctrl()
1312 u8 G = (ctrl->val & 0x00ff00) >> 8; in adv7842_s_ctrl()
1313 u8 B = (ctrl->val & 0x0000ff); in adv7842_s_ctrl()
1314 /* RGB -> YUV, numerical approximation */ in adv7842_s_ctrl()
1316 int U = -38 * R - 74 * G + 112 * B; in adv7842_s_ctrl()
1317 int V = 112 * R - 94 * G - 18 * B; in adv7842_s_ctrl()
1341 state->rgb_quantization_range = ctrl->val; in adv7842_s_ctrl()
1345 return -EINVAL; in adv7842_s_ctrl()
1352 if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) { in adv7842_g_volatile_ctrl()
1353 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC; in adv7842_g_volatile_ctrl()
1355 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3; in adv7842_g_volatile_ctrl()
1358 return -EINVAL; in adv7842_g_volatile_ctrl()
1385 if (state->mode == ADV7842_MODE_SDP) { in adv7842_g_input_status()
1397 /* TODO channel 2 */ in adv7842_g_input_status()
1420 u32 hfreq = (ADV7842_fsc * 8) / stdi->bl; in stdi2dv_timings()
1431 if (vtotal(bt) != stdi->lcf + 1) in stdi2dv_timings()
1433 if (bt->vsync != stdi->lcvs) in stdi2dv_timings()
1438 if ((pix_clk < bt->pixelclock + 1000000) && in stdi2dv_timings()
1439 (pix_clk > bt->pixelclock - 1000000)) { in stdi2dv_timings()
1445 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0, in stdi2dv_timings()
1446 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | in stdi2dv_timings()
1447 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), in stdi2dv_timings()
1450 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, in stdi2dv_timings()
1451 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | in stdi2dv_timings()
1452 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), in stdi2dv_timings()
1453 false, state->aspect_ratio, timings)) in stdi2dv_timings()
1458 __func__, stdi->lcvs, stdi->lcf, stdi->bl, in stdi2dv_timings()
1459 stdi->hs_pol, stdi->vs_pol); in stdi2dv_timings()
1460 return -1; in stdi2dv_timings()
1470 return -ENOLINK; in read_stdi()
1473 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2); in read_stdi()
1474 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4); in read_stdi()
1475 stdi->lcvs = cp_read(sd, 0xb3) >> 3; in read_stdi()
1478 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ? in read_stdi()
1479 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x'); in read_stdi()
1480 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ? in read_stdi()
1481 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x'); in read_stdi()
1483 stdi->hs_pol = 'x'; in read_stdi()
1484 stdi->vs_pol = 'x'; in read_stdi()
1486 stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false; in read_stdi()
1488 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { in read_stdi()
1490 return -ENOLINK; in read_stdi()
1494 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", in read_stdi()
1495 __func__, stdi->lcf, stdi->bl, stdi->lcvs, in read_stdi()
1496 stdi->hs_pol, stdi->vs_pol, in read_stdi()
1497 stdi->interlaced ? "interlaced" : "progressive"); in read_stdi()
1505 if (timings->pad != 0) in adv7842_enum_dv_timings()
1506 return -EINVAL; in adv7842_enum_dv_timings()
1515 if (cap->pad != 0) in adv7842_dv_timings_cap()
1516 return -EINVAL; in adv7842_dv_timings_cap()
1530 timings->bt.flags |= V4L2_DV_FL_CAN_DETECT_REDUCED_FPS; in adv7842_fill_optional_dv_timings_fields()
1537 struct v4l2_bt_timings *bt = &timings->bt; in adv7842_query_dv_timings()
1545 if (state->mode == ADV7842_MODE_SDP) in adv7842_query_dv_timings()
1546 return -ENODATA; in adv7842_query_dv_timings()
1550 state->restart_stdi_once = true; in adv7842_query_dv_timings()
1552 return -ENOLINK; in adv7842_query_dv_timings()
1554 bt->interlaced = stdi.interlaced ? in adv7842_query_dv_timings()
1556 bt->standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | in adv7842_query_dv_timings()
1562 timings->type = V4L2_DV_BT_656_1120; in adv7842_query_dv_timings()
1564 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08); in adv7842_query_dv_timings()
1565 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a); in adv7842_query_dv_timings()
1572 bt->pixelclock = freq; in adv7842_query_dv_timings()
1573 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 + in adv7842_query_dv_timings()
1575 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 + in adv7842_query_dv_timings()
1577 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 + in adv7842_query_dv_timings()
1579 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 + in adv7842_query_dv_timings()
1581 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 + in adv7842_query_dv_timings()
1583 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 + in adv7842_query_dv_timings()
1585 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | in adv7842_query_dv_timings()
1587 if (bt->interlaced == V4L2_DV_INTERLACED) { in adv7842_query_dv_timings()
1588 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 + in adv7842_query_dv_timings()
1590 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 + in adv7842_query_dv_timings()
1592 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 + in adv7842_query_dv_timings()
1594 bt->il_vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 + in adv7842_query_dv_timings()
1597 bt->il_vfrontporch = 0; in adv7842_query_dv_timings()
1598 bt->il_vsync = 0; in adv7842_query_dv_timings()
1599 bt->il_vbackporch = 0; in adv7842_query_dv_timings()
1602 if ((timings->bt.flags & V4L2_DV_FL_CAN_REDUCE_FPS) && in adv7842_query_dv_timings()
1603 freq < bt->pixelclock) { in adv7842_query_dv_timings()
1604 u32 reduced_freq = ((u32)bt->pixelclock / 1001) * 1000; in adv7842_query_dv_timings()
1605 u32 delta_freq = abs(freq - reduced_freq); in adv7842_query_dv_timings()
1607 if (delta_freq < ((u32)bt->pixelclock - reduced_freq) / 2) in adv7842_query_dv_timings()
1608 timings->bt.flags |= V4L2_DV_FL_REDUCED_FPS; in adv7842_query_dv_timings()
1612 * Since LCVS values are inaccurate [REF_03, p. 339-340], in adv7842_query_dv_timings()
1613 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. in adv7842_query_dv_timings()
1621 stdi.lcvs -= 2; in adv7842_query_dv_timings()
1622 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); in adv7842_query_dv_timings()
1633 if (state->restart_stdi_once) { in adv7842_query_dv_timings()
1635 /* TODO restart STDI for Sync Channel 2 */ in adv7842_query_dv_timings()
1636 /* enter one-shot mode */ in adv7842_query_dv_timings()
1642 state->restart_stdi_once = false; in adv7842_query_dv_timings()
1643 return -ENOLINK; in adv7842_query_dv_timings()
1646 return -ERANGE; in adv7842_query_dv_timings()
1648 state->restart_stdi_once = true; in adv7842_query_dv_timings()
1653 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings:", in adv7842_query_dv_timings()
1667 if (state->mode == ADV7842_MODE_SDP) in adv7842_s_dv_timings()
1668 return -ENODATA; in adv7842_s_dv_timings()
1670 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) { in adv7842_s_dv_timings()
1675 bt = &timings->bt; in adv7842_s_dv_timings()
1679 return -ERANGE; in adv7842_s_dv_timings()
1683 state->timings = *timings; in adv7842_s_dv_timings()
1685 cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00); in adv7842_s_dv_timings()
1699 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ", in adv7842_s_dv_timings()
1709 if (state->mode == ADV7842_MODE_SDP) in adv7842_g_dv_timings()
1710 return -ENODATA; in adv7842_g_dv_timings()
1711 *timings = state->timings; in adv7842_g_dv_timings()
1720 switch (state->mode) { in enable_input()
1733 __func__, state->mode); in enable_input()
1750 sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40); in sdp_csc_coeff()
1752 if (!c->manual) in sdp_csc_coeff()
1756 sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00); in sdp_csc_coeff()
1759 sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8); in sdp_csc_coeff()
1760 sdp_io_write(sd, 0xe1, c->A1); in sdp_csc_coeff()
1761 sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8); in sdp_csc_coeff()
1762 sdp_io_write(sd, 0xe3, c->A2); in sdp_csc_coeff()
1763 sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8); in sdp_csc_coeff()
1764 sdp_io_write(sd, 0xe5, c->A3); in sdp_csc_coeff()
1767 sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8); in sdp_csc_coeff()
1768 sdp_io_write(sd, 0xe7, c->A4); in sdp_csc_coeff()
1771 sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8); in sdp_csc_coeff()
1772 sdp_io_write(sd, 0xe9, c->B1); in sdp_csc_coeff()
1773 sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8); in sdp_csc_coeff()
1774 sdp_io_write(sd, 0xeb, c->B2); in sdp_csc_coeff()
1775 sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8); in sdp_csc_coeff()
1776 sdp_io_write(sd, 0xed, c->B3); in sdp_csc_coeff()
1779 sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8); in sdp_csc_coeff()
1780 sdp_io_write(sd, 0xef, c->B4); in sdp_csc_coeff()
1783 sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8); in sdp_csc_coeff()
1784 sdp_io_write(sd, 0xf1, c->C1); in sdp_csc_coeff()
1785 sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8); in sdp_csc_coeff()
1786 sdp_io_write(sd, 0xf3, c->C2); in sdp_csc_coeff()
1787 sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8); in sdp_csc_coeff()
1788 sdp_io_write(sd, 0xf5, c->C3); in sdp_csc_coeff()
1791 sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8); in sdp_csc_coeff()
1792 sdp_io_write(sd, 0xf7, c->C4); in sdp_csc_coeff()
1800 switch (state->mode) { in select_input()
1807 afe_write(sd, 0x00, 0x00); /* power up ADC */ in select_input()
1855 afe_write(sd, 0x00, 0x00); /* power up ADC */ in select_input()
1857 if (state->mode == ADV7842_MODE_COMP) { in select_input()
1868 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */ in select_input()
1869 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */ in select_input()
1877 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */ in select_input()
1879 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */ in select_input()
1886 if (state->hdmi_port_a) in select_input()
1920 afe_write(sd, 0x00, 0xff); /* power down ADC */ in select_input()
1932 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */ in select_input()
1934 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ in select_input()
1945 __func__, state->mode); in select_input()
1959 state->mode = ADV7842_MODE_HDMI; in adv7842_s_routing()
1960 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P; in adv7842_s_routing()
1961 state->hdmi_port_a = true; in adv7842_s_routing()
1964 state->mode = ADV7842_MODE_HDMI; in adv7842_s_routing()
1965 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P; in adv7842_s_routing()
1966 state->hdmi_port_a = false; in adv7842_s_routing()
1969 state->mode = ADV7842_MODE_COMP; in adv7842_s_routing()
1970 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE; in adv7842_s_routing()
1973 state->mode = ADV7842_MODE_RGB; in adv7842_s_routing()
1974 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE; in adv7842_s_routing()
1977 state->mode = ADV7842_MODE_SDP; in adv7842_s_routing()
1978 state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1; in adv7842_s_routing()
1981 state->mode = ADV7842_MODE_SDP; in adv7842_s_routing()
1982 state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1; in adv7842_s_routing()
1985 return -EINVAL; in adv7842_s_routing()
1989 select_input(sd, state->vid_std_select); in adv7842_s_routing()
2001 if (code->index >= ARRAY_SIZE(adv7842_formats)) in adv7842_enum_mbus_code()
2002 return -EINVAL; in adv7842_enum_mbus_code()
2003 code->code = adv7842_formats[code->index].code; in adv7842_enum_mbus_code()
2012 format->width = state->timings.bt.width; in adv7842_fill_format()
2013 format->height = state->timings.bt.height; in adv7842_fill_format()
2014 format->field = V4L2_FIELD_NONE; in adv7842_fill_format()
2015 format->colorspace = V4L2_COLORSPACE_SRGB; in adv7842_fill_format()
2017 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) in adv7842_fill_format()
2018 format->colorspace = (state->timings.bt.height <= 576) ? in adv7842_fill_format()
2032 * ----------+-------------------------------------------------
2034 * GRB (1-2) | BGR RGB GBR GRB RBG BRG
2035 * RBG (2-3) | GRB GBR BRG RBG BGR RGB
2036 * BGR (1-3) | RBG BRG RGB BGR GRB GBR
2049 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG), in adv7842_op_ch_sel()
2050 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB), in adv7842_op_ch_sel()
2051 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR), in adv7842_op_ch_sel()
2056 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5]; in adv7842_op_ch_sel()
2061 struct v4l2_subdev *sd = &state->sd; in adv7842_setup_format()
2064 state->format->rgb_out ? ADV7842_RGB_OUT : 0); in adv7842_setup_format()
2065 io_write(sd, 0x03, state->format->op_format_sel | in adv7842_setup_format()
2066 state->pdata.op_format_mode_sel); in adv7842_setup_format()
2069 state->format->swap_cb_cr ? ADV7842_OP_SWAP_CB_CR : 0); in adv7842_setup_format()
2079 if (format->pad != ADV7842_PAD_SOURCE) in adv7842_get_format()
2080 return -EINVAL; in adv7842_get_format()
2082 if (state->mode == ADV7842_MODE_SDP) { in adv7842_get_format()
2085 return -EINVAL; in adv7842_get_format()
2086 format->format.code = MEDIA_BUS_FMT_YUYV8_2X8; in adv7842_get_format()
2087 format->format.width = 720; in adv7842_get_format()
2089 if (state->norm & V4L2_STD_525_60) in adv7842_get_format()
2090 format->format.height = 480; in adv7842_get_format()
2092 format->format.height = 576; in adv7842_get_format()
2093 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M; in adv7842_get_format()
2097 adv7842_fill_format(state, &format->format); in adv7842_get_format()
2099 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { in adv7842_get_format()
2102 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); in adv7842_get_format()
2103 format->format.code = fmt->code; in adv7842_get_format()
2105 format->format.code = state->format->code; in adv7842_get_format()
2118 if (format->pad != ADV7842_PAD_SOURCE) in adv7842_set_format()
2119 return -EINVAL; in adv7842_set_format()
2121 if (state->mode == ADV7842_MODE_SDP) in adv7842_set_format()
2124 info = adv7842_format_info(state, format->format.code); in adv7842_set_format()
2128 adv7842_fill_format(state, &format->format); in adv7842_set_format()
2129 format->format.code = info->code; in adv7842_set_format()
2131 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { in adv7842_set_format()
2134 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); in adv7842_set_format()
2135 fmt->code = format->format.code; in adv7842_set_format()
2137 state->format = info; in adv7842_set_format()
2182 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST, in adv7842_cec_tx_raw_status()
2203 cec_transmit_done(state->cec_adap, status, in adv7842_cec_tx_raw_status()
2209 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0); in adv7842_cec_tx_raw_status()
2238 cec_write(sd, 0x26, 0x01); /* re-enable rx */ in adv7842_cec_isr()
2239 cec_received_msg(state->cec_adap, &msg); in adv7842_cec_isr()
2252 struct v4l2_subdev *sd = &state->sd; in adv7842_cec_adap_enable()
2254 if (!state->cec_enabled_adap && enable) { in adv7842_cec_adap_enable()
2265 } else if (state->cec_enabled_adap && !enable) { in adv7842_cec_adap_enable()
2268 /* disable address mask 1-3 */ in adv7842_cec_adap_enable()
2272 state->cec_valid_addrs = 0; in adv7842_cec_adap_enable()
2274 state->cec_enabled_adap = enable; in adv7842_cec_adap_enable()
2281 struct v4l2_subdev *sd = &state->sd; in adv7842_cec_adap_log_addr()
2284 if (!state->cec_enabled_adap) in adv7842_cec_adap_log_addr()
2285 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO; in adv7842_cec_adap_log_addr()
2289 state->cec_valid_addrs = 0; in adv7842_cec_adap_log_addr()
2294 bool is_valid = state->cec_valid_addrs & (1 << i); in adv7842_cec_adap_log_addr()
2298 if (is_valid && state->cec_addr[i] == addr) in adv7842_cec_adap_log_addr()
2304 return -ENXIO; in adv7842_cec_adap_log_addr()
2306 state->cec_addr[i] = addr; in adv7842_cec_adap_log_addr()
2307 state->cec_valid_addrs |= 1 << i; in adv7842_cec_adap_log_addr()
2336 struct v4l2_subdev *sd = &state->sd; in adv7842_cec_adap_transmit()
2337 u8 len = msg->len; in adv7842_cec_adap_transmit()
2341 * The number of retries is the number of attempts - 1, but retry in adv7842_cec_adap_transmit()
2345 cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4); in adv7842_cec_adap_transmit()
2349 return -EINVAL; in adv7842_cec_adap_transmit()
2354 cec_write(sd, i, msg->msg[i]); in adv7842_cec_adap_transmit()
2410 if (state->mode == ADV7842_MODE_SDP) in adv7842_isr()
2461 memset(edid->reserved, 0, sizeof(edid->reserved)); in adv7842_get_edid()
2463 switch (edid->pad) { in adv7842_get_edid()
2466 if (state->hdmi_edid.present & (0x04 << edid->pad)) in adv7842_get_edid()
2467 data = state->hdmi_edid.edid; in adv7842_get_edid()
2470 if (state->vga_edid.present) in adv7842_get_edid()
2471 data = state->vga_edid.edid; in adv7842_get_edid()
2474 return -EINVAL; in adv7842_get_edid()
2477 if (edid->start_block == 0 && edid->blocks == 0) { in adv7842_get_edid()
2478 edid->blocks = data ? 2 : 0; in adv7842_get_edid()
2483 return -ENODATA; in adv7842_get_edid()
2485 if (edid->start_block >= 2) in adv7842_get_edid()
2486 return -EINVAL; in adv7842_get_edid()
2488 if (edid->start_block + edid->blocks > 2) in adv7842_get_edid()
2489 edid->blocks = 2 - edid->start_block; in adv7842_get_edid()
2491 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128); in adv7842_get_edid()
2501 memset(e->reserved, 0, sizeof(e->reserved)); in adv7842_set_edid()
2503 if (e->pad > ADV7842_EDID_PORT_VGA) in adv7842_set_edid()
2504 return -EINVAL; in adv7842_set_edid()
2505 if (e->start_block != 0) in adv7842_set_edid()
2506 return -EINVAL; in adv7842_set_edid()
2507 if (e->blocks > 2) { in adv7842_set_edid()
2508 e->blocks = 2; in adv7842_set_edid()
2509 return -E2BIG; in adv7842_set_edid()
2513 state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15], in adv7842_set_edid()
2514 e->edid[0x16]); in adv7842_set_edid()
2516 switch (e->pad) { in adv7842_set_edid()
2518 memset(&state->vga_edid.edid, 0, 256); in adv7842_set_edid()
2519 state->vga_edid.present = e->blocks ? 0x1 : 0x0; in adv7842_set_edid()
2520 memcpy(&state->vga_edid.edid, e->edid, 128 * e->blocks); in adv7842_set_edid()
2525 memset(&state->hdmi_edid.edid, 0, 256); in adv7842_set_edid()
2526 if (e->blocks) { in adv7842_set_edid()
2527 state->hdmi_edid.present |= 0x04 << e->pad; in adv7842_set_edid()
2529 state->hdmi_edid.present &= ~(0x04 << e->pad); in adv7842_set_edid()
2532 memcpy(&state->hdmi_edid.edid, e->edid, 128 * e->blocks); in adv7842_set_edid()
2533 err = edid_write_hdmi_segment(sd, e->pad); in adv7842_set_edid()
2536 return -EINVAL; in adv7842_set_edid()
2539 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad); in adv7842_set_edid()
2557 struct device *dev = &client->dev; in log_infoframe()
2559 if (!(io_read(sd, 0x60) & cri->present_mask)) { in log_infoframe()
2560 v4l2_info(sd, "%s infoframe not received\n", cri->desc); in log_infoframe()
2565 buffer[i] = infoframe_read(sd, cri->head_addr + i); in log_infoframe()
2570 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, cri->desc, len); in log_infoframe()
2575 buffer[i + 3] = infoframe_read(sd, cri->payload_addr + i); in log_infoframe()
2578 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, cri->desc); in log_infoframe()
2596 v4l2_info(sd, "receive DVI-D signal, no infoframes\n"); in adv7842_log_infoframes()
2612 "HDMI-Comp",
2613 "HDMI-GR",
2632 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n", in adv7842_sdp_log_status()
2641 "NTSC-M/J", in adv7842_sdp_log_status()
2643 "NTSC-443", in adv7842_sdp_log_status()
2645 "PAL-M", in adv7842_sdp_log_status()
2647 "PAL-60", in adv7842_sdp_log_status()
2649 "PAL-CombN", in adv7842_sdp_log_status()
2651 "PAL-BGHID", in adv7842_sdp_log_status()
2682 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", in adv7842_cp_log_status()
2683 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", in adv7842_cp_log_status()
2684 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", in adv7842_cp_log_status()
2688 "RGB limited range (16-235)", "RGB full range (0-255)", in adv7842_cp_log_status()
2689 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", in adv7842_cp_log_status()
2691 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", in adv7842_cp_log_status()
2697 "RGB limited range (16-235)", in adv7842_cp_log_status()
2698 "RGB full range (0-255)", in adv7842_cp_log_status()
2701 "8-bits per channel", in adv7842_cp_log_status()
2702 "10-bits per channel", in adv7842_cp_log_status()
2703 "12-bits per channel", in adv7842_cp_log_status()
2704 "16-bits per channel (not supported)" in adv7842_cp_log_status()
2707 v4l2_info(sd, "-----Chip status-----\n"); in adv7842_cp_log_status()
2709 v4l2_info(sd, "HDMI/DVI-D port selected: %s\n", in adv7842_cp_log_status()
2710 state->hdmi_port_a ? "A" : "B"); in adv7842_cp_log_status()
2719 v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ? in adv7842_cp_log_status()
2721 if (state->cec_enabled_adap) { in adv7842_cp_log_status()
2725 bool is_valid = state->cec_valid_addrs & (1 << i); in adv7842_cp_log_status()
2729 state->cec_addr[i]); in adv7842_cp_log_status()
2733 v4l2_info(sd, "-----Signal status-----\n"); in adv7842_cp_log_status()
2734 if (state->hdmi_port_a) { in adv7842_cp_log_status()
2751 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", in adv7842_cp_log_status()
2755 v4l2_info(sd, "-----Video Timings-----\n"); in adv7842_cp_log_status()
2764 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x'); in adv7842_cp_log_status()
2766 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x'); in adv7842_cp_log_status()
2768 … "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n", in adv7842_cp_log_status()
2777 v4l2_print_dv_timings(sd->name, "Detected format: ", in adv7842_cp_log_status()
2779 v4l2_print_dv_timings(sd->name, "Configured format: ", in adv7842_cp_log_status()
2780 &state->timings, true); in adv7842_cp_log_status()
2785 v4l2_info(sd, "-----Color space-----\n"); in adv7842_cp_log_status()
2787 rgb_quantization_range_txt[state->rgb_quantization_range]); in adv7842_cp_log_status()
2790 v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n", in adv7842_cp_log_status()
2793 "(16-235)" : "(0-255)", in adv7842_cp_log_status()
2801 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); in adv7842_cp_log_status()
2816 (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo"); in adv7842_cp_log_status()
2838 if (state->mode == ADV7842_MODE_SDP) in adv7842_log_status()
2849 if (state->mode != ADV7842_MODE_SDP) in adv7842_querystd()
2850 return -ENODATA; in adv7842_querystd()
2860 /* NTSC-M/J */ in adv7842_querystd()
2864 /* NTSC-443 */ in adv7842_querystd()
2872 /* PAL-M */ in adv7842_querystd()
2876 /* PAL-60 */ in adv7842_querystd()
2880 /* PAL-CombN */ in adv7842_querystd()
2884 /* PAL-BGHID */ in adv7842_querystd()
2900 if (s && s->adjust) { in adv7842_s_sdp_io()
2901 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf); in adv7842_s_sdp_io()
2902 sdp_io_write(sd, 0x95, s->hs_beg & 0xff); in adv7842_s_sdp_io()
2903 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf); in adv7842_s_sdp_io()
2904 sdp_io_write(sd, 0x97, s->hs_width & 0xff); in adv7842_s_sdp_io()
2905 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf); in adv7842_s_sdp_io()
2906 sdp_io_write(sd, 0x99, s->de_beg & 0xff); in adv7842_s_sdp_io()
2907 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf); in adv7842_s_sdp_io()
2908 sdp_io_write(sd, 0x9b, s->de_end & 0xff); in adv7842_s_sdp_io()
2909 sdp_io_write(sd, 0xa8, s->vs_beg_o); in adv7842_s_sdp_io()
2910 sdp_io_write(sd, 0xa9, s->vs_beg_e); in adv7842_s_sdp_io()
2911 sdp_io_write(sd, 0xaa, s->vs_end_o); in adv7842_s_sdp_io()
2912 sdp_io_write(sd, 0xab, s->vs_end_e); in adv7842_s_sdp_io()
2913 sdp_io_write(sd, 0xac, s->de_v_beg_o); in adv7842_s_sdp_io()
2914 sdp_io_write(sd, 0xad, s->de_v_beg_e); in adv7842_s_sdp_io()
2915 sdp_io_write(sd, 0xae, s->de_v_end_o); in adv7842_s_sdp_io()
2916 sdp_io_write(sd, 0xaf, s->de_v_end_e); in adv7842_s_sdp_io()
2941 struct adv7842_platform_data *pdata = &state->pdata; in adv7842_s_std()
2945 if (state->mode != ADV7842_MODE_SDP) in adv7842_s_std()
2946 return -ENODATA; in adv7842_s_std()
2949 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625); in adv7842_s_std()
2951 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525); in adv7842_s_std()
2956 state->norm = norm; in adv7842_s_std()
2959 return -EINVAL; in adv7842_s_std()
2968 if (state->mode != ADV7842_MODE_SDP) in adv7842_g_std()
2969 return -ENODATA; in adv7842_g_std()
2971 *norm = state->norm; in adv7842_g_std()
2975 /* ----------------------------------------------------------------------- */
2980 struct adv7842_platform_data *pdata = &state->pdata; in adv7842_core_init()
2982 (pdata->disable_pwrdnb ? 0x80 : 0) | in adv7842_core_init()
2983 (pdata->disable_cable_det_rst ? 0x40 : 0)); in adv7842_core_init()
2998 io_write(sd, 0x02, 0xf0 | pdata->alt_gamma << 3); in adv7842_core_init()
2999 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 | in adv7842_core_init()
3000 pdata->insert_av_codes << 2 | in adv7842_core_init()
3001 pdata->replicate_av_codes << 1); in adv7842_core_init()
3009 pdata->dr_str_data << 4 | in adv7842_core_init()
3010 pdata->dr_str_clk << 2 | in adv7842_core_init()
3011 pdata->dr_str_sync); in adv7842_core_init()
3014 cp_write_and_or(sd, 0xba, 0xfc, pdata->hdmi_free_run_enable | in adv7842_core_init()
3015 (pdata->hdmi_free_run_mode << 1)); in adv7842_core_init()
3018 sdp_write_and_or(sd, 0xdd, 0xf0, pdata->sdp_free_run_force | in adv7842_core_init()
3019 (pdata->sdp_free_run_cbar_en << 1) | in adv7842_core_init()
3020 (pdata->sdp_free_run_man_col_en << 2) | in adv7842_core_init()
3021 (pdata->sdp_free_run_auto << 3)); in adv7842_core_init()
3029 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ in adv7842_core_init()
3030 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4); in adv7842_core_init()
3032 sdp_csc_coeff(sd, &pdata->sdp_csc_coeff); in adv7842_core_init()
3035 if (pdata->sd_ram_size >= 128) { in adv7842_core_init()
3037 if (pdata->sd_ram_ddr) { in adv7842_core_init()
3056 * Manual UG-214, rev 0 is bit confusing on this bit in adv7842_core_init()
3062 select_input(sd, pdata->vid_std_select); in adv7842_core_init()
3066 if (pdata->hpa_auto) { in adv7842_core_init()
3077 io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase); in adv7842_core_init()
3085 return v4l2_ctrl_handler_setup(sd->ctrl_handler); in adv7842_core_init()
3088 /* ----------------------------------------------------------------------- */
3154 return -EIO; in adv7842_ddr_ram_test()
3161 io_write(sd, 0xf1, pdata->i2c_sdp << 1); in adv7842_rewrite_i2c_addresses()
3162 io_write(sd, 0xf2, pdata->i2c_sdp_io << 1); in adv7842_rewrite_i2c_addresses()
3163 io_write(sd, 0xf3, pdata->i2c_avlink << 1); in adv7842_rewrite_i2c_addresses()
3164 io_write(sd, 0xf4, pdata->i2c_cec << 1); in adv7842_rewrite_i2c_addresses()
3165 io_write(sd, 0xf5, pdata->i2c_infoframe << 1); in adv7842_rewrite_i2c_addresses()
3167 io_write(sd, 0xf8, pdata->i2c_afe << 1); in adv7842_rewrite_i2c_addresses()
3168 io_write(sd, 0xf9, pdata->i2c_repeater << 1); in adv7842_rewrite_i2c_addresses()
3169 io_write(sd, 0xfa, pdata->i2c_edid << 1); in adv7842_rewrite_i2c_addresses()
3170 io_write(sd, 0xfb, pdata->i2c_hdmi << 1); in adv7842_rewrite_i2c_addresses()
3172 io_write(sd, 0xfd, pdata->i2c_cp << 1); in adv7842_rewrite_i2c_addresses()
3173 io_write(sd, 0xfe, pdata->i2c_vdp << 1); in adv7842_rewrite_i2c_addresses()
3180 struct adv7842_platform_data *pdata = client->dev.platform_data; in adv7842_command_ram_test()
3185 return -ENODEV; in adv7842_command_ram_test()
3187 if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) { in adv7842_command_ram_test()
3189 return -EINVAL; in adv7842_command_ram_test()
3203 /* and re-init chip and state */ in adv7842_command_ram_test()
3208 select_input(sd, state->vid_std_select); in adv7842_command_ram_test()
3216 timings = state->timings; in adv7842_command_ram_test()
3218 memset(&state->timings, 0, sizeof(struct v4l2_dv_timings)); in adv7842_command_ram_test()
3231 return -ENOTTY; in adv7842_ioctl()
3238 switch (sub->type) { in adv7842_subscribe_event()
3244 return -EINVAL; in adv7842_subscribe_event()
3254 err = cec_register_adapter(state->cec_adap, &client->dev); in adv7842_registered()
3256 cec_delete_adapter(state->cec_adap); in adv7842_registered()
3264 cec_unregister_adapter(state->cec_adap); in adv7842_unregistered()
3267 /* ----------------------------------------------------------------------- */
3318 /* -------------------------- custom ctrls ---------------------------------- */
3354 i2c_unregister_device(state->i2c_avlink); in adv7842_unregister_clients()
3355 i2c_unregister_device(state->i2c_cec); in adv7842_unregister_clients()
3356 i2c_unregister_device(state->i2c_infoframe); in adv7842_unregister_clients()
3357 i2c_unregister_device(state->i2c_sdp_io); in adv7842_unregister_clients()
3358 i2c_unregister_device(state->i2c_sdp); in adv7842_unregister_clients()
3359 i2c_unregister_device(state->i2c_afe); in adv7842_unregister_clients()
3360 i2c_unregister_device(state->i2c_repeater); in adv7842_unregister_clients()
3361 i2c_unregister_device(state->i2c_edid); in adv7842_unregister_clients()
3362 i2c_unregister_device(state->i2c_hdmi); in adv7842_unregister_clients()
3363 i2c_unregister_device(state->i2c_cp); in adv7842_unregister_clients()
3364 i2c_unregister_device(state->i2c_vdp); in adv7842_unregister_clients()
3366 state->i2c_avlink = NULL; in adv7842_unregister_clients()
3367 state->i2c_cec = NULL; in adv7842_unregister_clients()
3368 state->i2c_infoframe = NULL; in adv7842_unregister_clients()
3369 state->i2c_sdp_io = NULL; in adv7842_unregister_clients()
3370 state->i2c_sdp = NULL; in adv7842_unregister_clients()
3371 state->i2c_afe = NULL; in adv7842_unregister_clients()
3372 state->i2c_repeater = NULL; in adv7842_unregister_clients()
3373 state->i2c_edid = NULL; in adv7842_unregister_clients()
3374 state->i2c_hdmi = NULL; in adv7842_unregister_clients()
3375 state->i2c_cp = NULL; in adv7842_unregister_clients()
3376 state->i2c_vdp = NULL; in adv7842_unregister_clients()
3392 cp = i2c_new_dummy_device(client->adapter, io_read(sd, io_reg) >> 1); in adv7842_dummy_client()
3405 struct adv7842_platform_data *pdata = &state->pdata; in adv7842_register_clients()
3407 state->i2c_avlink = adv7842_dummy_client(sd, "avlink", pdata->i2c_avlink, 0xf3); in adv7842_register_clients()
3408 state->i2c_cec = adv7842_dummy_client(sd, "cec", pdata->i2c_cec, 0xf4); in adv7842_register_clients()
3409 state->i2c_infoframe = adv7842_dummy_client(sd, "infoframe", pdata->i2c_infoframe, 0xf5); in adv7842_register_clients()
3410 state->i2c_sdp_io = adv7842_dummy_client(sd, "sdp_io", pdata->i2c_sdp_io, 0xf2); in adv7842_register_clients()
3411 state->i2c_sdp = adv7842_dummy_client(sd, "sdp", pdata->i2c_sdp, 0xf1); in adv7842_register_clients()
3412 state->i2c_afe = adv7842_dummy_client(sd, "afe", pdata->i2c_afe, 0xf8); in adv7842_register_clients()
3413 state->i2c_repeater = adv7842_dummy_client(sd, "repeater", pdata->i2c_repeater, 0xf9); in adv7842_register_clients()
3414 state->i2c_edid = adv7842_dummy_client(sd, "edid", pdata->i2c_edid, 0xfa); in adv7842_register_clients()
3415 state->i2c_hdmi = adv7842_dummy_client(sd, "hdmi", pdata->i2c_hdmi, 0xfb); in adv7842_register_clients()
3416 state->i2c_cp = adv7842_dummy_client(sd, "cp", pdata->i2c_cp, 0xfd); in adv7842_register_clients()
3417 state->i2c_vdp = adv7842_dummy_client(sd, "vdp", pdata->i2c_vdp, 0xfe); in adv7842_register_clients()
3419 if (!state->i2c_avlink || in adv7842_register_clients()
3420 !state->i2c_cec || in adv7842_register_clients()
3421 !state->i2c_infoframe || in adv7842_register_clients()
3422 !state->i2c_sdp_io || in adv7842_register_clients()
3423 !state->i2c_sdp || in adv7842_register_clients()
3424 !state->i2c_afe || in adv7842_register_clients()
3425 !state->i2c_repeater || in adv7842_register_clients()
3426 !state->i2c_edid || in adv7842_register_clients()
3427 !state->i2c_hdmi || in adv7842_register_clients()
3428 !state->i2c_cp || in adv7842_register_clients()
3429 !state->i2c_vdp) in adv7842_register_clients()
3430 return -1; in adv7842_register_clients()
3441 struct adv7842_platform_data *pdata = client->dev.platform_data; in adv7842_probe()
3449 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) in adv7842_probe()
3450 return -EIO; in adv7842_probe()
3453 client->addr << 1); in adv7842_probe()
3457 return -ENODEV; in adv7842_probe()
3460 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); in adv7842_probe()
3462 return -ENOMEM; in adv7842_probe()
3465 state->pdata = *pdata; in adv7842_probe()
3466 state->timings = cea640x480; in adv7842_probe()
3467 state->format = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); in adv7842_probe()
3469 sd = &state->sd; in adv7842_probe()
3471 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; in adv7842_probe()
3472 sd->internal_ops = &adv7842_int_ops; in adv7842_probe()
3473 state->mode = pdata->mode; in adv7842_probe()
3475 state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A; in adv7842_probe()
3476 state->restart_stdi_once = true; in adv7842_probe()
3488 client->addr << 1, rev); in adv7842_probe()
3489 return -ENODEV; in adv7842_probe()
3492 if (pdata->chip_reset) in adv7842_probe()
3496 hdl = &state->hdl; in adv7842_probe()
3501 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); in adv7842_probe()
3512 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE; in adv7842_probe()
3515 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, in adv7842_probe()
3517 state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl, in adv7842_probe()
3519 state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl, in adv7842_probe()
3521 state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl, in adv7842_probe()
3523 state->rgb_quantization_range_ctrl = in adv7842_probe()
3527 sd->ctrl_handler = hdl; in adv7842_probe()
3528 if (hdl->error) { in adv7842_probe()
3529 err = hdl->error; in adv7842_probe()
3533 err = -ENODEV; in adv7842_probe()
3538 err = -ENOMEM; in adv7842_probe()
3544 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, in adv7842_probe()
3547 sd->entity.function = MEDIA_ENT_F_DV_DECODER; in adv7842_probe()
3548 state->pad.flags = MEDIA_PAD_FL_SOURCE; in adv7842_probe()
3549 err = media_entity_pads_init(&sd->entity, 1, &state->pad); in adv7842_probe()
3558 state->cec_adap = cec_allocate_adapter(&adv7842_cec_adap_ops, in adv7842_probe()
3559 state, dev_name(&client->dev), in adv7842_probe()
3561 err = PTR_ERR_OR_ZERO(state->cec_adap); in adv7842_probe()
3566 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, in adv7842_probe()
3567 client->addr << 1, client->adapter->name); in adv7842_probe()
3571 media_entity_cleanup(&sd->entity); in adv7842_probe()
3573 cancel_delayed_work(&state->delayed_work_enable_hotplug); in adv7842_probe()
3581 /* ----------------------------------------------------------------------- */
3589 cancel_delayed_work(&state->delayed_work_enable_hotplug); in adv7842_remove()
3591 media_entity_cleanup(&sd->entity); in adv7842_remove()
3593 v4l2_ctrl_handler_free(sd->ctrl_handler); in adv7842_remove()
3597 /* ----------------------------------------------------------------------- */
3605 /* ----------------------------------------------------------------------- */