Lines Matching +full:adc +full:- +full:alt +full:- +full:channel
1 // SPDX-License-Identifier: GPL-2.0-only
3 * adv7604 - Analog Devices ADV7604 video decoder driver
11 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
13 * REF_02 - Analog devices, Register map documentation, Documentation of
15 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
26 #include <linux/v4l2-dv-timings.h>
34 #include <media/v4l2-ctrls.h>
35 #include <media/v4l2-device.h>
36 #include <media/v4l2-event.h>
37 #include <media/v4l2-dv-timings.h>
38 #include <media/v4l2-fwnode.h>
42 MODULE_PARM_DESC(debug, "debug level (0-2)");
211 return state->info->has_afe; in adv76xx_has_afe()
318 /* ----------------------------------------------------------------------- */
335 /* ----------------------------------------------------------------------- */
340 struct i2c_client *client = state->i2c_clients[client_page]; in adv76xx_read_check()
344 err = regmap_read(state->regmap[client_page], reg, &val); in adv76xx_read_check()
348 client->addr, reg); in adv76xx_read_check()
364 struct regmap *regmap = state->regmap[client_page]; in adv76xx_write_block()
372 /* ----------------------------------------------------------------------- */
385 return regmap_write(state->regmap[ADV76XX_PAGE_IO], reg, val); in io_write()
405 return regmap_write(state->regmap[ADV7604_PAGE_AVLINK], reg, val); in avlink_write()
419 return regmap_write(state->regmap[ADV76XX_PAGE_CEC], reg, val); in cec_write()
439 return regmap_write(state->regmap[ADV76XX_PAGE_INFOFRAME], reg, val); in infoframe_write()
453 return regmap_write(state->regmap[ADV76XX_PAGE_AFE], reg, val); in afe_write()
467 return regmap_write(state->regmap[ADV76XX_PAGE_REP], reg, val); in rep_write()
486 return regmap_write(state->regmap[ADV76XX_PAGE_EDID], reg, val); in edid_write()
501 len = (total_len - i) > I2C_SMBUS_BLOCK_MAX ? in edid_write_block()
503 (total_len - i); in edid_write_block()
517 for (i = 0; i < state->info->num_dv_ports; ++i) in adv76xx_set_hpd()
518 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i)); in adv76xx_set_hpd()
520 v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd); in adv76xx_set_hpd()
528 struct v4l2_subdev *sd = &state->sd; in adv76xx_delayed_work_enable_hotplug()
532 adv76xx_set_hpd(state, state->edid.present); in adv76xx_delayed_work_enable_hotplug()
551 return regmap_write(state->regmap[ADV76XX_PAGE_HDMI], reg, val); in hdmi_write()
563 return regmap_write(state->regmap[ADV76XX_PAGE_TEST], reg, val); in test_write()
582 return regmap_write(state->regmap[ADV76XX_PAGE_CP], reg, val); in cp_write()
601 return regmap_write(state->regmap[ADV7604_PAGE_VDP], reg, val); in vdp_write()
615 if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask)) in adv76xx_read_reg()
616 return -EINVAL; in adv76xx_read_reg()
619 err = regmap_read(state->regmap[page], reg, &val); in adv76xx_read_reg()
630 if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask)) in adv76xx_write_reg()
631 return -EINVAL; in adv76xx_write_reg()
635 return regmap_write(state->regmap[page], reg, val); in adv76xx_write_reg()
647 /* -----------------------------------------------------------------------------
743 for (i = 0; i < state->info->nformats; ++i) { in adv76xx_format_info()
744 if (state->info->formats[i].code == code) in adv76xx_format_info()
745 return &state->info->formats[i]; in adv76xx_format_info()
751 /* ----------------------------------------------------------------------- */
757 return state->selected_input == ADV7604_PAD_VGA_RGB || in is_analog_input()
758 state->selected_input == ADV7604_PAD_VGA_COMP; in is_analog_input()
765 return state->selected_input == ADV76XX_PAD_HDMI_PORT_A || in is_digital_input()
766 state->selected_input == ADV7604_PAD_HDMI_PORT_B || in is_digital_input()
767 state->selected_input == ADV7604_PAD_HDMI_PORT_C || in is_digital_input()
768 state->selected_input == ADV7604_PAD_HDMI_PORT_D; in is_digital_input()
795 * case, pad value -1 returns the capabilities for the currently selected input.
800 if (pad == -1) { in adv76xx_get_dv_timings_cap()
803 pad = state->selected_input; in adv76xx_get_dv_timings_cap()
821 /* ----------------------------------------------------------------------- */
826 v4l2_info(sd, "0x000-0x0ff: IO Map\n"); in adv76xx_inv_register()
827 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); in adv76xx_inv_register()
828 v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); in adv76xx_inv_register()
829 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); in adv76xx_inv_register()
830 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n"); in adv76xx_inv_register()
831 v4l2_info(sd, "0x500-0x5ff: DPP Map\n"); in adv76xx_inv_register()
832 v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); in adv76xx_inv_register()
833 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); in adv76xx_inv_register()
834 v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); in adv76xx_inv_register()
835 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); in adv76xx_inv_register()
836 v4l2_info(sd, "0xa00-0xaff: Test Map\n"); in adv76xx_inv_register()
837 v4l2_info(sd, "0xb00-0xbff: CP Map\n"); in adv76xx_inv_register()
838 v4l2_info(sd, "0xc00-0xcff: VDP Map\n"); in adv76xx_inv_register()
846 ret = adv76xx_read_reg(sd, reg->reg); in adv76xx_g_register()
848 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); in adv76xx_g_register()
853 reg->size = 1; in adv76xx_g_register()
854 reg->val = ret; in adv76xx_g_register()
864 ret = adv76xx_write_reg(sd, reg->reg, reg->val); in adv76xx_s_register()
866 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); in adv76xx_s_register()
905 const struct adv76xx_chip_info *info = state->info; in adv76xx_s_detect_tx_5v_ctrl()
906 u16 cable_det = info->read_cable_det(sd); in adv76xx_s_detect_tx_5v_ctrl()
908 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det); in adv76xx_s_detect_tx_5v_ctrl()
928 return -1; in find_and_set_predefined_video_timings()
971 __func__, state->selected_input); in configure_predefined_video_timings()
972 err = -1; in configure_predefined_video_timings()
985 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; in configure_custom_video_timings()
986 u16 cp_start_eav = width - bt->hfrontporch; in configure_custom_video_timings()
987 u16 cp_start_vbi = height - bt->vfrontporch; in configure_custom_video_timings()
988 u16 cp_end_vbi = bt->vsync + bt->vbackporch; in configure_custom_video_timings()
989 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? in configure_custom_video_timings()
990 ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0; in configure_custom_video_timings()
1005 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ in configure_custom_video_timings()
1007 /* IO-map reg. 0x16 and 0x17 should be written in sequence */ in configure_custom_video_timings()
1008 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_IO], in configure_custom_video_timings()
1012 /* active video - horizontal timing */ in configure_custom_video_timings()
1018 /* active video - vertical timing */ in configure_custom_video_timings()
1030 __func__, state->selected_input); in configure_custom_video_timings()
1060 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP], in adv76xx_set_offset()
1090 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP], in adv76xx_set_gain()
1106 __func__, state->rgb_quantization_range, in set_rgb_quantization_range()
1113 switch (state->rgb_quantization_range) { in set_rgb_quantization_range()
1115 if (state->selected_input == ADV7604_PAD_VGA_RGB) { in set_rgb_quantization_range()
1117 * Set RGB full range (0-255) */ in set_rgb_quantization_range()
1122 if (state->selected_input == ADV7604_PAD_VGA_COMP) { in set_rgb_quantization_range()
1136 /* Receiving DVI-D signal in set_rgb_quantization_range()
1139 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) { in set_rgb_quantization_range()
1140 /* RGB limited range (16-235) */ in set_rgb_quantization_range()
1143 /* RGB full range (0-255) */ in set_rgb_quantization_range()
1155 if (state->selected_input == ADV7604_PAD_VGA_COMP) { in set_rgb_quantization_range()
1156 /* YCrCb limited range (16-235) */ in set_rgb_quantization_range()
1164 /* RGB limited range (16-235) */ in set_rgb_quantization_range()
1169 if (state->selected_input == ADV7604_PAD_VGA_COMP) { in set_rgb_quantization_range()
1170 /* YCrCb full range (0-255) */ in set_rgb_quantization_range()
1178 /* RGB full range (0-255) */ in set_rgb_quantization_range()
1184 /* Adjust gain/offset for DVI-D signals only */ in set_rgb_quantization_range()
1198 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd; in adv76xx_s_ctrl()
1202 switch (ctrl->id) { in adv76xx_s_ctrl()
1204 cp_write(sd, 0x3c, ctrl->val); in adv76xx_s_ctrl()
1207 cp_write(sd, 0x3a, ctrl->val); in adv76xx_s_ctrl()
1210 cp_write(sd, 0x3b, ctrl->val); in adv76xx_s_ctrl()
1213 cp_write(sd, 0x3d, ctrl->val); in adv76xx_s_ctrl()
1216 state->rgb_quantization_range = ctrl->val; in adv76xx_s_ctrl()
1221 return -EINVAL; in adv76xx_s_ctrl()
1226 afe_write(sd, 0xc8, ctrl->val); in adv76xx_s_ctrl()
1231 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2); in adv76xx_s_ctrl()
1234 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16); in adv76xx_s_ctrl()
1235 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8); in adv76xx_s_ctrl()
1236 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff)); in adv76xx_s_ctrl()
1239 return -EINVAL; in adv76xx_s_ctrl()
1245 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd; in adv76xx_g_volatile_ctrl()
1247 if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) { in adv76xx_g_volatile_ctrl()
1248 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC; in adv76xx_g_volatile_ctrl()
1250 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3; in adv76xx_g_volatile_ctrl()
1253 return -EINVAL; in adv76xx_g_volatile_ctrl()
1256 /* ----------------------------------------------------------------------- */
1268 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input)); in no_signal_tmds()
1274 const struct adv76xx_chip_info *info = state->info; in no_lock_tmds()
1276 return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask; in no_lock_tmds()
1295 /* TODO channel 2 */ in no_lock_sspd()
1301 /* TODO channel 2 */ in no_lock_stdi()
1353 /* ----------------------------------------------------------------------- */
1366 u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl; in stdi2dv_timings()
1374 adv76xx_get_dv_timings_cap(sd, -1), in stdi2dv_timings()
1377 if (vtotal(bt) != stdi->lcf + 1) in stdi2dv_timings()
1379 if (bt->vsync != stdi->lcvs) in stdi2dv_timings()
1384 if ((pix_clk < bt->pixelclock + 1000000) && in stdi2dv_timings()
1385 (pix_clk > bt->pixelclock - 1000000)) { in stdi2dv_timings()
1391 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0, in stdi2dv_timings()
1392 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | in stdi2dv_timings()
1393 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), in stdi2dv_timings()
1396 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, in stdi2dv_timings()
1397 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | in stdi2dv_timings()
1398 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), in stdi2dv_timings()
1399 false, state->aspect_ratio, timings)) in stdi2dv_timings()
1404 __func__, stdi->lcvs, stdi->lcf, stdi->bl, in stdi2dv_timings()
1405 stdi->hs_pol, stdi->vs_pol); in stdi2dv_timings()
1406 return -1; in stdi2dv_timings()
1413 const struct adv76xx_chip_info *info = state->info; in read_stdi()
1418 return -1; in read_stdi()
1422 stdi->bl = cp_read16(sd, 0xb1, 0x3fff); in read_stdi()
1423 stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff); in read_stdi()
1424 stdi->lcvs = cp_read(sd, 0xb3) >> 3; in read_stdi()
1425 stdi->interlaced = io_read(sd, 0x12) & 0x10; in read_stdi()
1431 stdi->hs_pol = polarity & 0x10 in read_stdi()
1432 ? (polarity & 0x08 ? '+' : '-') : 'x'; in read_stdi()
1433 stdi->vs_pol = polarity & 0x40 in read_stdi()
1434 ? (polarity & 0x20 ? '+' : '-') : 'x'; in read_stdi()
1436 stdi->hs_pol = 'x'; in read_stdi()
1437 stdi->vs_pol = 'x'; in read_stdi()
1441 stdi->hs_pol = polarity & 0x20 ? '+' : '-'; in read_stdi()
1442 stdi->vs_pol = polarity & 0x10 ? '+' : '-'; in read_stdi()
1448 return -1; in read_stdi()
1451 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { in read_stdi()
1454 return -1; in read_stdi()
1458 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", in read_stdi()
1459 __func__, stdi->lcf, stdi->bl, stdi->lcvs, in read_stdi()
1460 stdi->hs_pol, stdi->vs_pol, in read_stdi()
1461 stdi->interlaced ? "interlaced" : "progressive"); in read_stdi()
1471 if (timings->pad >= state->source_pad) in adv76xx_enum_dv_timings()
1472 return -EINVAL; in adv76xx_enum_dv_timings()
1475 adv76xx_get_dv_timings_cap(sd, timings->pad), in adv76xx_enum_dv_timings()
1483 unsigned int pad = cap->pad; in adv76xx_dv_timings_cap()
1485 if (cap->pad >= state->source_pad) in adv76xx_dv_timings_cap()
1486 return -EINVAL; in adv76xx_dv_timings_cap()
1489 cap->pad = pad; in adv76xx_dv_timings_cap()
1499 v4l2_find_dv_timings_cap(timings, adv76xx_get_dv_timings_cap(sd, -1), in adv76xx_fill_optional_dv_timings_fields()
1531 const struct adv76xx_chip_info *info = state->info; in adv76xx_read_hdmi_pixelclock()
1534 freq = info->read_hdmi_pixelclock(sd); in adv76xx_read_hdmi_pixelclock()
1550 const struct adv76xx_chip_info *info = state->info; in adv76xx_query_dv_timings()
1551 struct v4l2_bt_timings *bt = &timings->bt; in adv76xx_query_dv_timings()
1555 return -EINVAL; in adv76xx_query_dv_timings()
1560 state->restart_stdi_once = true; in adv76xx_query_dv_timings()
1562 return -ENOLINK; in adv76xx_query_dv_timings()
1568 return -ENOLINK; in adv76xx_query_dv_timings()
1570 bt->interlaced = stdi.interlaced ? in adv76xx_query_dv_timings()
1578 w = hdmi_read16(sd, 0x07, info->linewidth_mask); in adv76xx_query_dv_timings()
1579 h = hdmi_read16(sd, 0x09, info->field0_height_mask); in adv76xx_query_dv_timings()
1585 bt->width == w && bt->height == h) in adv76xx_query_dv_timings()
1588 timings->type = V4L2_DV_BT_656_1120; in adv76xx_query_dv_timings()
1590 bt->width = w; in adv76xx_query_dv_timings()
1591 bt->height = h; in adv76xx_query_dv_timings()
1592 bt->pixelclock = adv76xx_read_hdmi_pixelclock(sd); in adv76xx_query_dv_timings()
1593 bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask); in adv76xx_query_dv_timings()
1594 bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask); in adv76xx_query_dv_timings()
1595 bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask); in adv76xx_query_dv_timings()
1596 bt->vfrontporch = hdmi_read16(sd, 0x2a, in adv76xx_query_dv_timings()
1597 info->field0_vfrontporch_mask) / 2; in adv76xx_query_dv_timings()
1598 bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2; in adv76xx_query_dv_timings()
1599 bt->vbackporch = hdmi_read16(sd, 0x32, in adv76xx_query_dv_timings()
1600 info->field0_vbackporch_mask) / 2; in adv76xx_query_dv_timings()
1601 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | in adv76xx_query_dv_timings()
1603 if (bt->interlaced == V4L2_DV_INTERLACED) { in adv76xx_query_dv_timings()
1604 bt->height += hdmi_read16(sd, 0x0b, in adv76xx_query_dv_timings()
1605 info->field1_height_mask); in adv76xx_query_dv_timings()
1606 bt->il_vfrontporch = hdmi_read16(sd, 0x2c, in adv76xx_query_dv_timings()
1607 info->field1_vfrontporch_mask) / 2; in adv76xx_query_dv_timings()
1608 bt->il_vsync = hdmi_read16(sd, 0x30, in adv76xx_query_dv_timings()
1609 info->field1_vsync_mask) / 2; in adv76xx_query_dv_timings()
1610 bt->il_vbackporch = hdmi_read16(sd, 0x34, in adv76xx_query_dv_timings()
1611 info->field1_vbackporch_mask) / 2; in adv76xx_query_dv_timings()
1616 * Since LCVS values are inaccurate [REF_03, p. 275-276], in adv76xx_query_dv_timings()
1617 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. in adv76xx_query_dv_timings()
1625 stdi.lcvs -= 2; in adv76xx_query_dv_timings()
1626 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); in adv76xx_query_dv_timings()
1637 if (state->restart_stdi_once) { in adv76xx_query_dv_timings()
1639 /* TODO restart STDI for Sync Channel 2 */ in adv76xx_query_dv_timings()
1640 /* enter one-shot mode */ in adv76xx_query_dv_timings()
1646 state->restart_stdi_once = false; in adv76xx_query_dv_timings()
1647 return -ENOLINK; in adv76xx_query_dv_timings()
1650 return -ERANGE; in adv76xx_query_dv_timings()
1652 state->restart_stdi_once = true; in adv76xx_query_dv_timings()
1659 return -ENOLINK; in adv76xx_query_dv_timings()
1662 if ((is_analog_input(sd) && bt->pixelclock > 170000000) || in adv76xx_query_dv_timings()
1663 (is_digital_input(sd) && bt->pixelclock > 225000000)) { in adv76xx_query_dv_timings()
1665 __func__, (u32)bt->pixelclock); in adv76xx_query_dv_timings()
1666 return -ERANGE; in adv76xx_query_dv_timings()
1670 v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ", in adv76xx_query_dv_timings()
1684 return -EINVAL; in adv76xx_s_dv_timings()
1686 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) { in adv76xx_s_dv_timings()
1691 bt = &timings->bt; in adv76xx_s_dv_timings()
1693 if (!v4l2_valid_dv_timings(timings, adv76xx_get_dv_timings_cap(sd, -1), in adv76xx_s_dv_timings()
1695 return -ERANGE; in adv76xx_s_dv_timings()
1699 state->timings = *timings; in adv76xx_s_dv_timings()
1701 cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00); in adv76xx_s_dv_timings()
1714 v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ", in adv76xx_s_dv_timings()
1724 *timings = state->timings; in adv76xx_g_dv_timings()
1745 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input); in enable_input()
1746 state->info->set_termination(sd, true); in enable_input()
1751 __func__, state->selected_input); in enable_input()
1762 state->info->set_termination(sd, false); in disable_input()
1768 const struct adv76xx_chip_info *info = state->info; in select_input()
1771 adv76xx_write_reg_seq(sd, info->recommended_settings[0]); in select_input()
1773 afe_write(sd, 0x00, 0x08); /* power up ADC */ in select_input()
1777 hdmi_write(sd, 0x00, state->selected_input & 0x03); in select_input()
1779 adv76xx_write_reg_seq(sd, info->recommended_settings[1]); in select_input()
1782 afe_write(sd, 0x00, 0xff); /* power down ADC */ in select_input()
1787 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ in select_input()
1789 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */ in select_input()
1792 __func__, state->selected_input); in select_input()
1802 __func__, input, state->selected_input); in adv76xx_s_routing()
1804 if (input == state->selected_input) in adv76xx_s_routing()
1807 if (input > state->info->max_port) in adv76xx_s_routing()
1808 return -EINVAL; in adv76xx_s_routing()
1810 state->selected_input = input; in adv76xx_s_routing()
1827 if (code->index >= state->info->nformats) in adv76xx_enum_mbus_code()
1828 return -EINVAL; in adv76xx_enum_mbus_code()
1830 code->code = state->info->formats[code->index].code; in adv76xx_enum_mbus_code()
1840 format->width = state->timings.bt.width; in adv76xx_fill_format()
1841 format->height = state->timings.bt.height; in adv76xx_fill_format()
1842 format->field = V4L2_FIELD_NONE; in adv76xx_fill_format()
1843 format->colorspace = V4L2_COLORSPACE_SRGB; in adv76xx_fill_format()
1845 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) in adv76xx_fill_format()
1846 format->colorspace = (state->timings.bt.height <= 576) ? in adv76xx_fill_format()
1860 * ----------+-------------------------------------------------
1862 * GRB (1-2) | BGR RGB GBR GRB RBG BRG
1863 * RBG (2-3) | GRB GBR BRG RBG BGR RGB
1864 * BGR (1-3) | RBG BRG RGB BGR GRB GBR
1877 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG), in adv76xx_op_ch_sel()
1878 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB), in adv76xx_op_ch_sel()
1879 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR), in adv76xx_op_ch_sel()
1884 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5]; in adv76xx_op_ch_sel()
1889 struct v4l2_subdev *sd = &state->sd; in adv76xx_setup_format()
1892 state->format->rgb_out ? ADV76XX_RGB_OUT : 0); in adv76xx_setup_format()
1893 io_write(sd, 0x03, state->format->op_format_sel | in adv76xx_setup_format()
1894 state->pdata.op_format_mode_sel); in adv76xx_setup_format()
1897 state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0); in adv76xx_setup_format()
1907 if (format->pad != state->source_pad) in adv76xx_get_format()
1908 return -EINVAL; in adv76xx_get_format()
1910 adv76xx_fill_format(state, &format->format); in adv76xx_get_format()
1912 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { in adv76xx_get_format()
1915 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); in adv76xx_get_format()
1916 format->format.code = fmt->code; in adv76xx_get_format()
1918 format->format.code = state->format->code; in adv76xx_get_format()
1930 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) in adv76xx_get_selection()
1931 return -EINVAL; in adv76xx_get_selection()
1933 if (sel->target > V4L2_SEL_TGT_CROP_BOUNDS) in adv76xx_get_selection()
1934 return -EINVAL; in adv76xx_get_selection()
1936 sel->r.left = 0; in adv76xx_get_selection()
1937 sel->r.top = 0; in adv76xx_get_selection()
1938 sel->r.width = state->timings.bt.width; in adv76xx_get_selection()
1939 sel->r.height = state->timings.bt.height; in adv76xx_get_selection()
1951 if (format->pad != state->source_pad) in adv76xx_set_format()
1952 return -EINVAL; in adv76xx_set_format()
1954 info = adv76xx_format_info(state, format->format.code); in adv76xx_set_format()
1958 adv76xx_fill_format(state, &format->format); in adv76xx_set_format()
1959 format->format.code = info->code; in adv76xx_set_format()
1961 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { in adv76xx_set_format()
1964 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); in adv76xx_set_format()
1965 fmt->code = format->format.code; in adv76xx_set_format()
1967 state->format = info; in adv76xx_set_format()
1987 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST, in adv76xx_cec_tx_raw_status()
2008 cec_transmit_done(state->cec_adap, status, in adv76xx_cec_tx_raw_status()
2014 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0); in adv76xx_cec_tx_raw_status()
2022 const struct adv76xx_chip_info *info = state->info; in adv76xx_cec_isr()
2026 cec_irq = io_read(sd, info->cec_irq_status) & 0x0f; in adv76xx_cec_isr()
2044 cec_write(sd, info->cec_rx_enable, in adv76xx_cec_isr()
2045 info->cec_rx_enable_mask); /* re-enable rx */ in adv76xx_cec_isr()
2046 cec_received_msg(state->cec_adap, &msg); in adv76xx_cec_isr()
2050 if (info->cec_irq_swap) { in adv76xx_cec_isr()
2058 io_write(sd, info->cec_irq_status + 1, cec_irq); in adv76xx_cec_isr()
2067 const struct adv76xx_chip_info *info = state->info; in adv76xx_cec_adap_enable()
2068 struct v4l2_subdev *sd = &state->sd; in adv76xx_cec_adap_enable()
2070 if (!state->cec_enabled_adap && enable) { in adv76xx_cec_adap_enable()
2079 io_write_clr_set(sd, info->cec_irq_status + 3, 0x0f, 0x0f); in adv76xx_cec_adap_enable()
2080 cec_write(sd, info->cec_rx_enable, info->cec_rx_enable_mask); in adv76xx_cec_adap_enable()
2081 } else if (state->cec_enabled_adap && !enable) { in adv76xx_cec_adap_enable()
2083 io_write_clr_set(sd, info->cec_irq_status + 3, 0x0f, 0x00); in adv76xx_cec_adap_enable()
2084 /* disable address mask 1-3 */ in adv76xx_cec_adap_enable()
2088 state->cec_valid_addrs = 0; in adv76xx_cec_adap_enable()
2090 state->cec_enabled_adap = enable; in adv76xx_cec_adap_enable()
2098 struct v4l2_subdev *sd = &state->sd; in adv76xx_cec_adap_log_addr()
2101 if (!state->cec_enabled_adap) in adv76xx_cec_adap_log_addr()
2102 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO; in adv76xx_cec_adap_log_addr()
2106 state->cec_valid_addrs = 0; in adv76xx_cec_adap_log_addr()
2111 bool is_valid = state->cec_valid_addrs & (1 << i); in adv76xx_cec_adap_log_addr()
2115 if (is_valid && state->cec_addr[i] == addr) in adv76xx_cec_adap_log_addr()
2121 return -ENXIO; in adv76xx_cec_adap_log_addr()
2123 state->cec_addr[i] = addr; in adv76xx_cec_adap_log_addr()
2124 state->cec_valid_addrs |= 1 << i; in adv76xx_cec_adap_log_addr()
2153 struct v4l2_subdev *sd = &state->sd; in adv76xx_cec_adap_transmit()
2154 u8 len = msg->len; in adv76xx_cec_adap_transmit()
2158 * The number of retries is the number of attempts - 1, but retry in adv76xx_cec_adap_transmit()
2162 cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4); in adv76xx_cec_adap_transmit()
2166 return -EINVAL; in adv76xx_cec_adap_transmit()
2171 cec_write(sd, i, msg->msg[i]); in adv76xx_cec_adap_transmit()
2190 const struct adv76xx_chip_info *info = state->info; in adv76xx_isr()
2210 ? irq_reg_0x6b & info->fmt_change_digital_mask in adv76xx_isr()
2238 tx_5v = irq_reg_0x70 & info->cable_det_mask; in adv76xx_isr()
2253 adv76xx_isr(&state->sd, 0, &handled); in adv76xx_irq_handler()
2263 memset(edid->reserved, 0, sizeof(edid->reserved)); in adv76xx_get_edid()
2265 switch (edid->pad) { in adv76xx_get_edid()
2270 if (state->edid.present & (1 << edid->pad)) in adv76xx_get_edid()
2271 data = state->edid.edid; in adv76xx_get_edid()
2274 return -EINVAL; in adv76xx_get_edid()
2277 if (edid->start_block == 0 && edid->blocks == 0) { in adv76xx_get_edid()
2278 edid->blocks = data ? state->edid.blocks : 0; in adv76xx_get_edid()
2283 return -ENODATA; in adv76xx_get_edid()
2285 if (edid->start_block >= state->edid.blocks) in adv76xx_get_edid()
2286 return -EINVAL; in adv76xx_get_edid()
2288 if (edid->start_block + edid->blocks > state->edid.blocks) in adv76xx_get_edid()
2289 edid->blocks = state->edid.blocks - edid->start_block; in adv76xx_get_edid()
2291 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128); in adv76xx_get_edid()
2299 const struct adv76xx_chip_info *info = state->info; in adv76xx_set_edid()
2305 memset(edid->reserved, 0, sizeof(edid->reserved)); in adv76xx_set_edid()
2307 if (edid->pad > ADV7604_PAD_HDMI_PORT_D) in adv76xx_set_edid()
2308 return -EINVAL; in adv76xx_set_edid()
2309 if (edid->start_block != 0) in adv76xx_set_edid()
2310 return -EINVAL; in adv76xx_set_edid()
2311 if (edid->blocks == 0) { in adv76xx_set_edid()
2313 state->edid.present &= ~(1 << edid->pad); in adv76xx_set_edid()
2314 adv76xx_set_hpd(state, state->edid.present); in adv76xx_set_edid()
2315 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); in adv76xx_set_edid()
2318 state->aspect_ratio.numerator = 16; in adv76xx_set_edid()
2319 state->aspect_ratio.denominator = 9; in adv76xx_set_edid()
2321 if (!state->edid.present) { in adv76xx_set_edid()
2322 state->edid.blocks = 0; in adv76xx_set_edid()
2323 cec_phys_addr_invalidate(state->cec_adap); in adv76xx_set_edid()
2327 __func__, edid->pad, state->edid.present); in adv76xx_set_edid()
2330 if (edid->blocks > 2) { in adv76xx_set_edid()
2331 edid->blocks = 2; in adv76xx_set_edid()
2332 return -E2BIG; in adv76xx_set_edid()
2334 pa = v4l2_get_edid_phys_addr(edid->edid, edid->blocks * 128, &spa_loc); in adv76xx_set_edid()
2340 __func__, edid->pad, state->edid.present); in adv76xx_set_edid()
2343 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); in adv76xx_set_edid()
2345 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00); in adv76xx_set_edid()
2352 return -EINVAL; in adv76xx_set_edid()
2354 switch (edid->pad) { in adv76xx_set_edid()
2356 state->spa_port_a[0] = edid->edid[spa_loc]; in adv76xx_set_edid()
2357 state->spa_port_a[1] = edid->edid[spa_loc + 1]; in adv76xx_set_edid()
2360 rep_write(sd, 0x70, edid->edid[spa_loc]); in adv76xx_set_edid()
2361 rep_write(sd, 0x71, edid->edid[spa_loc + 1]); in adv76xx_set_edid()
2364 rep_write(sd, 0x72, edid->edid[spa_loc]); in adv76xx_set_edid()
2365 rep_write(sd, 0x73, edid->edid[spa_loc + 1]); in adv76xx_set_edid()
2368 rep_write(sd, 0x74, edid->edid[spa_loc]); in adv76xx_set_edid()
2369 rep_write(sd, 0x75, edid->edid[spa_loc + 1]); in adv76xx_set_edid()
2372 return -EINVAL; in adv76xx_set_edid()
2375 if (info->type == ADV7604) { in adv76xx_set_edid()
2384 edid->edid[spa_loc] = state->spa_port_a[0]; in adv76xx_set_edid()
2385 edid->edid[spa_loc + 1] = state->spa_port_a[1]; in adv76xx_set_edid()
2387 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks); in adv76xx_set_edid()
2388 state->edid.blocks = edid->blocks; in adv76xx_set_edid()
2389 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15], in adv76xx_set_edid()
2390 edid->edid[0x16]); in adv76xx_set_edid()
2391 state->edid.present |= 1 << edid->pad; in adv76xx_set_edid()
2393 err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid); in adv76xx_set_edid()
2395 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad); in adv76xx_set_edid()
2401 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); in adv76xx_set_edid()
2404 if (rep_read(sd, info->edid_status_reg) & state->edid.present) in adv76xx_set_edid()
2409 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present); in adv76xx_set_edid()
2410 return -EIO; in adv76xx_set_edid()
2412 cec_s_phys_addr(state->cec_adap, pa, false); in adv76xx_set_edid()
2415 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10); in adv76xx_set_edid()
2419 /*********** avi info frame CEA-861-E **************/
2438 return -ENOENT; in adv76xx_read_infoframe()
2450 return -ENOENT; in adv76xx_read_infoframe()
2460 return -ENOENT; in adv76xx_read_infoframe()
2470 v4l2_info(sd, "receive DVI-D signal, no infoframes\n"); in adv76xx_log_infoframes()
2480 hdmi_infoframe_log(KERN_INFO, &client->dev, &frame); in adv76xx_log_infoframes()
2487 const struct adv76xx_chip_info *info = state->info; in adv76xx_log_status()
2495 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", in adv76xx_log_status()
2496 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", in adv76xx_log_status()
2497 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", in adv76xx_log_status()
2501 "RGB limited range (16-235)", "RGB full range (0-255)", in adv76xx_log_status()
2502 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", in adv76xx_log_status()
2504 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", in adv76xx_log_status()
2509 "RGB limited range (16-235)", "RGB full range (0-255)", in adv76xx_log_status()
2510 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", in adv76xx_log_status()
2512 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", in adv76xx_log_status()
2518 "RGB limited range (16-235)", in adv76xx_log_status()
2519 "RGB full range (0-255)", in adv76xx_log_status()
2522 "8-bits per channel", in adv76xx_log_status()
2523 "10-bits per channel", in adv76xx_log_status()
2524 "12-bits per channel", in adv76xx_log_status()
2525 "16-bits per channel (not supported)" in adv76xx_log_status()
2528 v4l2_info(sd, "-----Chip status-----\n"); in adv76xx_log_status()
2530 edid_enabled = rep_read(sd, info->edid_status_reg); in adv76xx_log_status()
2536 v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ? in adv76xx_log_status()
2538 if (state->cec_enabled_adap) { in adv76xx_log_status()
2542 bool is_valid = state->cec_valid_addrs & (1 << i); in adv76xx_log_status()
2546 state->cec_addr[i]); in adv76xx_log_status()
2550 v4l2_info(sd, "-----Signal status-----\n"); in adv76xx_log_status()
2551 cable_det = info->read_cable_det(sd); in adv76xx_log_status()
2566 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", in adv76xx_log_status()
2570 v4l2_info(sd, "-----Video Timings-----\n"); in adv76xx_log_status()
2574 …v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync… in adv76xx_log_status()
2581 v4l2_print_dv_timings(sd->name, "Detected format: ", in adv76xx_log_status()
2583 v4l2_print_dv_timings(sd->name, "Configured format: ", in adv76xx_log_status()
2584 &state->timings, true); in adv76xx_log_status()
2589 v4l2_info(sd, "-----Color space-----\n"); in adv76xx_log_status()
2591 rgb_quantization_range_txt[state->rgb_quantization_range]); in adv76xx_log_status()
2594 v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n", in adv76xx_log_status()
2597 "(16-235)" : "(0-255)", in adv76xx_log_status()
2600 csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]); in adv76xx_log_status()
2605 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); in adv76xx_log_status()
2624 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo"); in adv76xx_log_status()
2647 switch (sub->type) { in adv76xx_subscribe_event()
2653 return -EINVAL; in adv76xx_subscribe_event()
2663 err = cec_register_adapter(state->cec_adap, &client->dev); in adv76xx_registered()
2665 cec_delete_adapter(state->cec_adap); in adv76xx_registered()
2673 cec_unregister_adapter(state->cec_adap); in adv76xx_unregistered()
2676 /* ----------------------------------------------------------------------- */
2724 /* -------------------------- custom ctrls ---------------------------------- */
2759 /* ----------------------------------------------------------------------- */
2785 const struct adv76xx_chip_info *info = state->info; in adv76xx_core_init()
2786 struct adv76xx_platform_data *pdata = &state->pdata; in adv76xx_core_init()
2789 (pdata->disable_pwrdnb ? 0x80 : 0) | in adv76xx_core_init()
2790 (pdata->disable_cable_det_rst ? 0x40 : 0)); in adv76xx_core_init()
2794 if (pdata->default_input >= 0 && in adv76xx_core_init()
2795 pdata->default_input < state->source_pad) { in adv76xx_core_init()
2796 state->selected_input = pdata->default_input; in adv76xx_core_init()
2807 io_write_clr_set(sd, 0x02, 0x0f, pdata->alt_gamma << 3); in adv76xx_core_init()
2808 io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 | in adv76xx_core_init()
2809 pdata->insert_av_codes << 2 | in adv76xx_core_init()
2810 pdata->replicate_av_codes << 1); in adv76xx_core_init()
2816 io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 | in adv76xx_core_init()
2817 pdata->inv_hs_pol << 1 | pdata->inv_llc_pol); in adv76xx_core_init()
2820 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 | in adv76xx_core_init()
2821 pdata->dr_str_clk << 2 | in adv76xx_core_init()
2822 pdata->dr_str_sync); in adv76xx_core_init()
2824 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */ in adv76xx_core_init()
2826 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold - in adv76xx_core_init()
2828 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold - in adv76xx_core_init()
2834 hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */ in adv76xx_core_init()
2836 hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */ in adv76xx_core_init()
2842 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ in adv76xx_core_init()
2843 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4); in adv76xx_core_init()
2847 io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */ in adv76xx_core_init()
2849 …io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts … in adv76xx_core_init()
2850 io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */ in adv76xx_core_init()
2851 info->setup_irqs(sd); in adv76xx_core_init()
2853 return v4l2_ctrl_handler_setup(sd->ctrl_handler); in adv76xx_core_init()
2875 for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) in adv76xx_unregister_clients()
2876 i2c_unregister_device(state->i2c_clients[i]); in adv76xx_unregister_clients()
2884 struct adv76xx_platform_data *pdata = &state->pdata; in adv76xx_dummy_client()
2888 if (pdata && pdata->i2c_addresses[page]) in adv76xx_dummy_client()
2889 new_client = i2c_new_dummy_device(client->adapter, in adv76xx_dummy_client()
2890 pdata->i2c_addresses[page]); in adv76xx_dummy_client()
2897 io_write(sd, io_reg, new_client->addr << 1); in adv76xx_dummy_client()
2907 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
2920 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
2922 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
2924 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
2933 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
2946 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
3147 np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node; in adv76xx_parse_dt()
3152 return -EINVAL; in adv76xx_parse_dt()
3159 if (!of_property_read_u32(np, "default-input", &v)) in adv76xx_parse_dt()
3160 state->pdata.default_input = v; in adv76xx_parse_dt()
3162 state->pdata.default_input = -1; in adv76xx_parse_dt()
3167 state->pdata.inv_hs_pol = 1; in adv76xx_parse_dt()
3170 state->pdata.inv_vs_pol = 1; in adv76xx_parse_dt()
3173 state->pdata.inv_llc_pol = 1; in adv76xx_parse_dt()
3176 state->pdata.insert_av_codes = 1; in adv76xx_parse_dt()
3178 /* Disable the interrupt for now as no DT-based board uses it. */ in adv76xx_parse_dt()
3179 state->pdata.int1_config = ADV76XX_INT1_CONFIG_ACTIVE_HIGH; in adv76xx_parse_dt()
3182 state->pdata.disable_pwrdnb = 0; in adv76xx_parse_dt()
3183 state->pdata.disable_cable_det_rst = 0; in adv76xx_parse_dt()
3184 state->pdata.blank_data = 1; in adv76xx_parse_dt()
3185 state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0; in adv76xx_parse_dt()
3186 state->pdata.bus_order = ADV7604_BUS_ORDER_RGB; in adv76xx_parse_dt()
3187 state->pdata.dr_str_data = ADV76XX_DR_STR_MEDIUM_HIGH; in adv76xx_parse_dt()
3188 state->pdata.dr_str_clk = ADV76XX_DR_STR_MEDIUM_HIGH; in adv76xx_parse_dt()
3189 state->pdata.dr_str_sync = ADV76XX_DR_STR_MEDIUM_HIGH; in adv76xx_parse_dt()
3306 if (!state->i2c_clients[region]) in configure_regmap()
3307 return -ENODEV; in configure_regmap()
3309 state->regmap[region] = in configure_regmap()
3310 devm_regmap_init_i2c(state->i2c_clients[region], in configure_regmap()
3313 if (IS_ERR(state->regmap[region])) { in configure_regmap()
3314 err = PTR_ERR(state->regmap[region]); in configure_regmap()
3315 v4l_err(state->i2c_clients[region], in configure_regmap()
3318 return -EINVAL; in configure_regmap()
3330 if (err && (err != -ENODEV)) in configure_regmaps()
3338 if (state->reset_gpio) { in adv76xx_reset()
3340 gpiod_set_value_cansleep(state->reset_gpio, 0); in adv76xx_reset()
3342 gpiod_set_value_cansleep(state->reset_gpio, 1); in adv76xx_reset()
3363 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) in adv76xx_probe()
3364 return -EIO; in adv76xx_probe()
3366 client->addr << 1); in adv76xx_probe()
3368 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); in adv76xx_probe()
3370 return -ENOMEM; in adv76xx_probe()
3372 state->i2c_clients[ADV76XX_PAGE_IO] = client; in adv76xx_probe()
3375 state->restart_stdi_once = true; in adv76xx_probe()
3376 state->selected_input = ~0; in adv76xx_probe()
3378 if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) { in adv76xx_probe()
3381 oid = of_match_node(adv76xx_of_id, client->dev.of_node); in adv76xx_probe()
3382 state->info = oid->data; in adv76xx_probe()
3389 } else if (client->dev.platform_data) { in adv76xx_probe()
3390 struct adv76xx_platform_data *pdata = client->dev.platform_data; in adv76xx_probe()
3392 state->info = (const struct adv76xx_chip_info *)id->driver_data; in adv76xx_probe()
3393 state->pdata = *pdata; in adv76xx_probe()
3396 return -ENODEV; in adv76xx_probe()
3400 for (i = 0; i < state->info->num_dv_ports; ++i) { in adv76xx_probe()
3401 state->hpd_gpio[i] = in adv76xx_probe()
3402 devm_gpiod_get_index_optional(&client->dev, "hpd", i, in adv76xx_probe()
3404 if (IS_ERR(state->hpd_gpio[i])) in adv76xx_probe()
3405 return PTR_ERR(state->hpd_gpio[i]); in adv76xx_probe()
3407 if (state->hpd_gpio[i]) in adv76xx_probe()
3410 state->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", in adv76xx_probe()
3412 if (IS_ERR(state->reset_gpio)) in adv76xx_probe()
3413 return PTR_ERR(state->reset_gpio); in adv76xx_probe()
3417 state->timings = cea640x480; in adv76xx_probe()
3418 state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); in adv76xx_probe()
3420 sd = &state->sd; in adv76xx_probe()
3422 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x", in adv76xx_probe()
3423 id->name, i2c_adapter_id(client->adapter), in adv76xx_probe()
3424 client->addr); in adv76xx_probe()
3425 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; in adv76xx_probe()
3426 sd->internal_ops = &adv76xx_int_ops; in adv76xx_probe()
3433 return -ENODEV; in adv76xx_probe()
3441 switch (state->info->type) { in adv76xx_probe()
3443 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 0xfb, &val); in adv76xx_probe()
3446 return -ENODEV; in adv76xx_probe()
3450 client->addr << 1); in adv76xx_probe()
3451 return -ENODEV; in adv76xx_probe()
3456 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], in adv76xx_probe()
3461 return -ENODEV; in adv76xx_probe()
3464 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], in adv76xx_probe()
3469 return -ENODEV; in adv76xx_probe()
3472 if ((state->info->type == ADV7611 && val != 0x2051) || in adv76xx_probe()
3473 (state->info->type == ADV7612 && val != 0x2041)) { in adv76xx_probe()
3475 client->addr << 1); in adv76xx_probe()
3476 return -ENODEV; in adv76xx_probe()
3482 hdl = &state->hdl; in adv76xx_probe()
3486 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); in adv76xx_probe()
3497 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE; in adv76xx_probe()
3499 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, in adv76xx_probe()
3501 (1 << state->info->num_dv_ports) - 1, 0, 0); in adv76xx_probe()
3502 state->rgb_quantization_range_ctrl = in adv76xx_probe()
3509 state->analog_sampling_phase_ctrl = in adv76xx_probe()
3511 state->free_run_color_manual_ctrl = in adv76xx_probe()
3513 state->free_run_color_ctrl = in adv76xx_probe()
3516 sd->ctrl_handler = hdl; in adv76xx_probe()
3517 if (hdl->error) { in adv76xx_probe()
3518 err = hdl->error; in adv76xx_probe()
3522 err = -ENODEV; in adv76xx_probe()
3529 if (!(BIT(i) & state->info->page_mask)) in adv76xx_probe()
3539 state->i2c_clients[i] = dummy_client; in adv76xx_probe()
3542 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, in adv76xx_probe()
3545 state->source_pad = state->info->num_dv_ports in adv76xx_probe()
3546 + (state->info->has_afe ? 2 : 0); in adv76xx_probe()
3547 for (i = 0; i < state->source_pad; ++i) in adv76xx_probe()
3548 state->pads[i].flags = MEDIA_PAD_FL_SINK; in adv76xx_probe()
3549 state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE; in adv76xx_probe()
3550 sd->entity.function = MEDIA_ENT_F_DV_DECODER; in adv76xx_probe()
3552 err = media_entity_pads_init(&sd->entity, state->source_pad + 1, in adv76xx_probe()
3553 state->pads); in adv76xx_probe()
3566 if (client->irq) { in adv76xx_probe()
3567 err = devm_request_threaded_irq(&client->dev, in adv76xx_probe()
3568 client->irq, in adv76xx_probe()
3571 client->name, state); in adv76xx_probe()
3577 state->cec_adap = cec_allocate_adapter(&adv76xx_cec_adap_ops, in adv76xx_probe()
3578 state, dev_name(&client->dev), in adv76xx_probe()
3580 err = PTR_ERR_OR_ZERO(state->cec_adap); in adv76xx_probe()
3585 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, in adv76xx_probe()
3586 client->addr << 1, client->adapter->name); in adv76xx_probe()
3595 media_entity_cleanup(&sd->entity); in adv76xx_probe()
3597 cancel_delayed_work(&state->delayed_work_enable_hotplug); in adv76xx_probe()
3605 /* ----------------------------------------------------------------------- */
3619 cancel_delayed_work(&state->delayed_work_enable_hotplug); in adv76xx_remove()
3621 media_entity_cleanup(&sd->entity); in adv76xx_remove()
3623 v4l2_ctrl_handler_free(sd->ctrl_handler); in adv76xx_remove()
3627 /* ----------------------------------------------------------------------- */