Lines Matching +full:reg +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0-only
3 * drxd_hard.c: DVB-T Demodulator Micronas DRX3975D-A2,DRX397xD-B1
5 * Copyright (C) 2003-2007 Micronas
21 #define DRX_FW_FILENAME_A2 "drxd-a2-1.1.fw"
22 #define DRX_FW_FILENAME_B1 "drxd-b1-1.1.fw"
194 return -1; in i2c_write()
211 return -1; in i2c_read()
225 static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags) in Read16() argument
227 u8 adr = state->config.demod_address; in Read16()
228 u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff, in Read16()
229 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff in Read16()
232 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0) in Read16()
233 return -1; in Read16()
239 static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags) in Read32() argument
241 u8 adr = state->config.demod_address; in Read32()
242 u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff, in Read32()
243 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff in Read32()
247 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0) in Read32()
248 return -1; in Read32()
255 static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags) in Write16() argument
257 u8 adr = state->config.demod_address; in Write16()
258 u8 mm[6] = { reg & 0xff, (reg >> 16) & 0xff, in Write16()
259 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff, in Write16()
263 if (i2c_write(state->i2c, adr, mm, 6) < 0) in Write16()
264 return -1; in Write16()
268 static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags) in Write32() argument
270 u8 adr = state->config.demod_address; in Write32()
271 u8 mm[8] = { reg & 0xff, (reg >> 16) & 0xff, in Write32()
272 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff, in Write32()
277 if (i2c_write(state->i2c, adr, mm, 8) < 0) in Write32()
278 return -1; in Write32()
283 u32 reg, u8 *data, u32 len, u8 flags) in write_chunk() argument
285 u8 adr = state->config.demod_address; in write_chunk()
286 u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff, in write_chunk()
287 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff in write_chunk()
293 if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) { in write_chunk()
295 return -1; in write_chunk()
307 return -1; in WriteBlock()
310 BlockSize -= Chunk; in WriteBlock()
347 return WriteTable(state, state->m_ResetCEFR); in ResetCEFR()
352 return WriteTable(state, state->m_InitCP); in InitCP()
358 enum app_env AppEnv = state->app_env_default; in InitCE()
361 status = WriteTable(state, state->m_InitCE); in InitCE()
365 if (state->operation_mode == OM_DVBT_Diversity_Front || in InitCE()
366 state->operation_mode == OM_DVBT_Diversity_End) { in InitCE()
367 AppEnv = state->app_env_diversity; in InitCE()
377 } else if (AppEnv == APPENV_MOBILE && state->type_A) { in InitCE()
381 } else if (AppEnv == APPENV_MOBILE && !state->type_A) { in InitCE()
399 u16 ocModeLop = state->m_EcOcRegOcModeLop; in StopOC()
409 state->m_EcOcRegSncSncLvl = ocSyncLvl; in StopOC()
412 /* Flush FIFO (byte-boundary) at fixed rate */ in StopOC()
447 ocModeLop |= 0x2; /* Magically-out-of-sync */ in StopOC()
473 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0); in StartOC()
476 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0); in StartOC()
495 return WriteTable(state, state->m_InitEQ); in InitEQ()
500 return WriteTable(state, state->m_InitEC); in InitEC()
505 return WriteTable(state, state->m_InitSC); in InitSC()
510 return WriteTable(state, state->m_InitAtomicRead); in InitAtomicRead()
535 if (state->drxd_state != DRXD_STARTED) in DRX_GetLockStatus()
557 if (cfg->outputLevel > DRXD_FE_CTRL_MAX) in SetCfgIfAgc()
558 return -1; in SetCfgIfAgc()
560 if (cfg->ctrlMode == AGC_CTRL_USER) { in SetCfgIfAgc()
574 FeAgRegPm1AgcWri = (u16) (cfg->outputLevel & in SetCfgIfAgc()
580 } else if (cfg->ctrlMode == AGC_CTRL_AUTO) { in SetCfgIfAgc()
581 if (((cfg->maxOutputLevel) < (cfg->minOutputLevel)) || in SetCfgIfAgc()
582 ((cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX) || in SetCfgIfAgc()
583 ((cfg->speed) > DRXD_FE_CTRL_MAX) || in SetCfgIfAgc()
584 ((cfg->settleLevel) > DRXD_FE_CTRL_MAX) in SetCfgIfAgc()
586 return -1; in SetCfgIfAgc()
606 FeAgRegEgcSetLvl = (u16) ((cfg->settleLevel >> 1) & in SetCfgIfAgc()
614 slope = (u16) ((cfg->maxOutputLevel - in SetCfgIfAgc()
615 cfg->minOutputLevel) / 2); in SetCfgIfAgc()
616 offset = (u16) ((cfg->maxOutputLevel + in SetCfgIfAgc()
617 cfg->minOutputLevel) / 2 - 511); in SetCfgIfAgc()
641 u16 fineSpeed = (u16) (cfg->speed - in SetCfgIfAgc()
642 ((cfg->speed / in SetCfgIfAgc()
645 u16 invRurCount = (u16) (cfg->speed / in SetCfgIfAgc()
652 rurCount = maxRur - invRurCount; in SetCfgIfAgc()
693 return -1; in SetCfgIfAgc()
702 if (cfg->outputLevel > DRXD_FE_CTRL_MAX) in SetCfgRfAgc()
703 return -1; in SetCfgRfAgc()
705 if (cfg->ctrlMode == AGC_CTRL_USER) { in SetCfgRfAgc()
708 u16 level = (cfg->outputLevel); in SetCfgRfAgc()
720 state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M); in SetCfgRfAgc()
721 state->m_FeAgRegAgPwd |= in SetCfgRfAgc()
723 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); in SetCfgRfAgc()
754 } else if (cfg->ctrlMode == AGC_CTRL_AUTO) { in SetCfgRfAgc()
761 (state->m_FeAgRegAgPwd) &= in SetCfgRfAgc()
763 (state->m_FeAgRegAgPwd) |= in SetCfgRfAgc()
765 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); in SetCfgRfAgc()
780 level = (((cfg->settleLevel) >> 4) & in SetCfgRfAgc()
812 (state->m_FeAgRegAgPwd) &= in SetCfgRfAgc()
814 (state->m_FeAgRegAgPwd) |= in SetCfgRfAgc()
816 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); in SetCfgRfAgc()
855 if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) { in ReadIFAgc()
864 Vin - R3 - * -- Vout in ReadIFAgc()
870 u32 R1 = state->if_agc_cfg.R1; in ReadIFAgc()
871 u32 R2 = state->if_agc_cfg.R2; in ReadIFAgc()
872 u32 R3 = state->if_agc_cfg.R3; in ReadIFAgc()
882 Vout = Vmin + ((Vmax - Vmin) * Value) / 1024; in ReadIFAgc()
894 if (request_firmware(&fw, fw_name, state->dev) < 0) { in load_firmware()
896 return -EIO; in load_firmware()
899 state->microcode = kmemdup(fw->data, fw->size, GFP_KERNEL); in load_firmware()
900 if (!state->microcode) { in load_firmware()
902 return -ENOMEM; in load_firmware()
905 state->microcode_length = fw->size; in load_firmware()
972 status = -1; in HI_Command()
987 mutex_lock(&state->mutex); in HI_CfgCommand()
989 Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0); in HI_CfgCommand()
990 Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0); in HI_CfgCommand()
991 Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0); in HI_CfgCommand()
992 Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0); in HI_CfgCommand()
996 if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) == in HI_CfgCommand()
1002 mutex_unlock(&state->mutex); in HI_CfgCommand()
1008 state->hi_cfg_wakeup_key = (state->chip_adr); in InitHI()
1010 state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON; in InitHI()
1018 mutex_lock(&state->mutex); in HI_ResetCommand()
1023 mutex_unlock(&state->mutex); in HI_ResetCommand()
1030 state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M); in DRX_ConfigureI2CBridge()
1032 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON; in DRX_ConfigureI2CBridge()
1034 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF; in DRX_ConfigureI2CBridge()
1053 return -1;
1055 mutex_lock(&state->mutex);
1059 /* TODO use proper names forthese egisters */
1069 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
1094 mutex_unlock(&state->mutex);
1105 return -1;
1122 if (state->type_A) { in EnableAndResetMB()
1137 if (state->osc_clock_freq == 0 || in InitCC()
1138 state->osc_clock_freq > 20000 || in InitCC()
1139 (state->osc_clock_freq % 4000) != 0) { in InitCC()
1140 printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq); in InitCC()
1141 return -1; in InitCC()
1149 state->osc_clock_freq / 4000, 0); in InitCC()
1161 if (state->type_A) in ResetECOD()
1167 status = WriteTable(state, state->m_ResetECRAM); in ResetECOD()
1246 status = WriteTable(state, state->m_InitFE_1); in InitFE()
1250 if (state->type_A) { in InitFE()
1255 if (state->PGA) in InitFE()
1266 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000); in InitFE()
1269 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); in InitFE()
1273 status = WriteTable(state, state->m_InitFE_2); in InitFE()
1300 return -1; in SC_WaitForReady()
1318 status = -1; in SC_SendCommand()
1330 mutex_lock(&state->mutex); in SC_ProcStartCommand()
1334 status = -1; in SC_ProcStartCommand()
1344 mutex_unlock(&state->mutex); in SC_ProcStartCommand()
1353 mutex_lock(&state->mutex); in SC_SetPrefParamCommand()
1372 mutex_unlock(&state->mutex); in SC_SetPrefParamCommand()
1381 mutex_lock(&state->mutex);
1393 mutex_unlock(&state->mutex);
1410 if (state->operation_mode == OM_DVBT_Diversity_Front) { in ConfigureMPEGOutput()
1419 EcOcRegOcModeLop = state->m_EcOcRegOcModeLop; in ConfigureMPEGOutput()
1427 if (state->insert_rs_byte) { in ConfigureMPEGOutput()
1444 if (state->enable_parallel) in ConfigureMPEGOutput()
1503 state->type_A = 0; in SetDeviceTypeId()
1504 state->PGA = 0; in SetDeviceTypeId()
1505 state->diversity = 0; in SetDeviceTypeId()
1507 state->type_A = 1; in SetDeviceTypeId()
1508 printk(KERN_INFO "DRX3975D-A2\n"); in SetDeviceTypeId()
1511 printk(KERN_INFO "DRX397%dD-B1\n", deviceId); in SetDeviceTypeId()
1514 state->diversity = 1; in SetDeviceTypeId()
1518 state->PGA = 1; in SetDeviceTypeId()
1521 state->diversity = 1; in SetDeviceTypeId()
1527 status = -1; in SetDeviceTypeId()
1537 state->m_InitAtomicRead = DRXD_InitAtomicRead; in SetDeviceTypeId()
1538 state->m_InitSC = DRXD_InitSC; in SetDeviceTypeId()
1539 state->m_ResetECRAM = DRXD_ResetECRAM; in SetDeviceTypeId()
1540 if (state->type_A) { in SetDeviceTypeId()
1541 state->m_ResetCEFR = DRXD_ResetCEFR; in SetDeviceTypeId()
1542 state->m_InitFE_1 = DRXD_InitFEA2_1; in SetDeviceTypeId()
1543 state->m_InitFE_2 = DRXD_InitFEA2_2; in SetDeviceTypeId()
1544 state->m_InitCP = DRXD_InitCPA2; in SetDeviceTypeId()
1545 state->m_InitCE = DRXD_InitCEA2; in SetDeviceTypeId()
1546 state->m_InitEQ = DRXD_InitEQA2; in SetDeviceTypeId()
1547 state->m_InitEC = DRXD_InitECA2; in SetDeviceTypeId()
1549 return -EIO; in SetDeviceTypeId()
1551 state->m_ResetCEFR = NULL; in SetDeviceTypeId()
1552 state->m_InitFE_1 = DRXD_InitFEB1_1; in SetDeviceTypeId()
1553 state->m_InitFE_2 = DRXD_InitFEB1_2; in SetDeviceTypeId()
1554 state->m_InitCP = DRXD_InitCPB1; in SetDeviceTypeId()
1555 state->m_InitCE = DRXD_InitCEB1; in SetDeviceTypeId()
1556 state->m_InitEQ = DRXD_InitEQB1; in SetDeviceTypeId()
1557 state->m_InitEC = DRXD_InitECB1; in SetDeviceTypeId()
1559 return -EIO; in SetDeviceTypeId()
1561 if (state->diversity) { in SetDeviceTypeId()
1562 state->m_InitDiversityFront = DRXD_InitDiversityFront; in SetDeviceTypeId()
1563 state->m_InitDiversityEnd = DRXD_InitDiversityEnd; in SetDeviceTypeId()
1564 state->m_DisableDiversity = DRXD_DisableDiversity; in SetDeviceTypeId()
1565 state->m_StartDiversityFront = DRXD_StartDiversityFront; in SetDeviceTypeId()
1566 state->m_StartDiversityEnd = DRXD_StartDiversityEnd; in SetDeviceTypeId()
1567 state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ; in SetDeviceTypeId()
1568 state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ; in SetDeviceTypeId()
1570 state->m_InitDiversityFront = NULL; in SetDeviceTypeId()
1571 state->m_InitDiversityEnd = NULL; in SetDeviceTypeId()
1572 state->m_DisableDiversity = NULL; in SetDeviceTypeId()
1573 state->m_StartDiversityFront = NULL; in SetDeviceTypeId()
1574 state->m_StartDiversityEnd = NULL; in SetDeviceTypeId()
1575 state->m_DiversityDelay8MHZ = NULL; in SetDeviceTypeId()
1576 state->m_DiversityDelay6MHZ = NULL; in SetDeviceTypeId()
1605 if (state->type_A) { in CorrectSysClockDeviation()
1606 if ((nomincr - incr < -500) || (nomincr - incr > 500)) in CorrectSysClockDeviation()
1609 if ((nomincr - incr < -2000) || (nomincr - incr > 2000)) in CorrectSysClockDeviation()
1613 switch (state->props.bandwidth_hz) { in CorrectSysClockDeviation()
1624 return -1; in CorrectSysClockDeviation()
1638 oscClockDeviation = (u16) ((((s32) (sysClockFreq) - in CorrectSysClockDeviation()
1640 (state->expected_sys_clock_freq)) * in CorrectSysClockDeviation()
1643 (state->expected_sys_clock_freq)); in CorrectSysClockDeviation()
1645 Diff = oscClockDeviation - state->osc_clock_deviation; in CorrectSysClockDeviation()
1647 if (Diff >= -200 && Diff <= 200) { in CorrectSysClockDeviation()
1648 state->sys_clock_freq = (u16) sysClockFreq; in CorrectSysClockDeviation()
1649 if (oscClockDeviation != state->osc_clock_deviation) { in CorrectSysClockDeviation()
1650 if (state->config.osc_deviation) { in CorrectSysClockDeviation()
1651 state->config.osc_deviation(state->priv, in CorrectSysClockDeviation()
1654 state->osc_clock_deviation = in CorrectSysClockDeviation()
1663 proper re-locking */ in CorrectSysClockDeviation()
1664 status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0); in CorrectSysClockDeviation()
1667 state->cscd_state = CSCD_SAVED; in CorrectSysClockDeviation()
1678 if (state->drxd_state != DRXD_STARTED) in DRX_Stop()
1682 if (state->cscd_state != CSCD_SAVED) { in DRX_Stop()
1693 state->drxd_state = DRXD_STOPPED; in DRX_Stop()
1699 if (state->type_A) { in DRX_Stop()
1746 if (state->drxd_state != DRXD_STOPPED) {
1747 status = -1;
1751 if (oMode == state->operation_mode) {
1756 if (oMode != OM_Default && !state->diversity) {
1757 status = -1;
1763 status = WriteTable(state, state->m_InitDiversityFront);
1766 status = WriteTable(state, state->m_InitDiversityEnd);
1772 status = WriteTable(state, state->m_DisableDiversity);
1778 state->operation_mode = oMode;
1789 if (state->operation_mode == OM_DVBT_Diversity_Front) { in StartDiversity()
1790 status = WriteTable(state, state->m_StartDiversityFront); in StartDiversity()
1793 } else if (state->operation_mode == OM_DVBT_Diversity_End) { in StartDiversity()
1794 status = WriteTable(state, state->m_StartDiversityEnd); in StartDiversity()
1797 if (state->props.bandwidth_hz == 8000000) { in StartDiversity()
1798 status = WriteTable(state, state->m_DiversityDelay8MHZ); in StartDiversity()
1802 status = WriteTable(state, state->m_DiversityDelay6MHZ); in StartDiversity()
1827 int negativeShift = (state->tuner_mirrors == channelMirrored); in SetFrequencyShift()
1840 state->fe_fs_add_incr = MulDiv32(state->intermediate_freq + in SetFrequencyShift()
1842 1 << 28, state->sys_clock_freq); in SetFrequencyShift()
1844 state->fe_fs_add_incr &= 0x0FFFFFFFL; in SetFrequencyShift()
1846 state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr); in SetFrequencyShift()
1850 state->org_fe_fs_add_incr = MulDiv32(state->intermediate_freq, in SetFrequencyShift()
1851 1 << 28, state->sys_clock_freq); in SetFrequencyShift()
1853 state->org_fe_fs_add_incr &= 0x0FFFFFFFL; in SetFrequencyShift()
1855 state->org_fe_fs_add_incr = ((1L << 28) - in SetFrequencyShift()
1856 state->org_fe_fs_add_incr); in SetFrequencyShift()
1859 state->fe_fs_add_incr, 0); in SetFrequencyShift()
1872 if (noiseCal->cpOpt) { in SetCfgNoiseCalibration()
1876 status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0); in SetCfgNoiseCalibration()
1884 if (!state->type_A) { in SetCfgNoiseCalibration()
1885 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0); in SetCfgNoiseCalibration()
1888 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0); in SetCfgNoiseCalibration()
1899 struct dtv_frontend_properties *p = &state->props; in DRX_Start()
1923 off = (off - 500) / 1000; in DRX_Start()
1928 if (state->drxd_state != DRXD_STOPPED) in DRX_Start()
1929 return -1; in DRX_Start()
1933 if (state->type_A) { in DRX_Start()
1957 status = SetCfgIfAgc(state, &state->if_agc_cfg); in DRX_Start()
1960 status = SetCfgRfAgc(state, &state->rf_agc_cfg); in DRX_Start()
1964 mirrorFreqSpect = (state->props.inversion == INVERSION_ON); in DRX_Start()
1966 switch (p->transmission_mode) { in DRX_Start()
1972 if (state->type_A) { in DRX_Start()
1983 if (state->type_A) { in DRX_Start()
1994 switch (p->guard_interval) { in DRX_Start()
2014 switch (p->hierarchy) { in DRX_Start()
2017 if (state->type_A) { in DRX_Start()
2047 if (state->type_A) { in DRX_Start()
2076 if (state->type_A) { in DRX_Start()
2108 if (state->type_A) { in DRX_Start()
2139 switch (p->modulation) { in DRX_Start()
2145 if (state->type_A) { in DRX_Start()
2178 if (state->type_A) { in DRX_Start()
2212 if (state->type_A) { in DRX_Start()
2261 switch (p->code_rate_HP) { in DRX_Start()
2264 if (state->type_A) in DRX_Start()
2272 if (state->type_A) in DRX_Start()
2277 if (state->type_A) in DRX_Start()
2282 if (state->type_A) in DRX_Start()
2287 if (state->type_A) in DRX_Start()
2301 switch (p->bandwidth_hz) { in DRX_Start()
2303 p->bandwidth_hz = 8000000; in DRX_Start()
2328 status = -EINVAL; in DRX_Start()
2345 if ((p->transmission_mode == TRANSMISSION_MODE_2K) && in DRX_Start()
2346 (p->guard_interval == GUARD_INTERVAL_1_32)) { in DRX_Start()
2358 status = SetCfgNoiseCalibration(state, &state->noise_cal); in DRX_Start()
2362 if (state->cscd_state == CSCD_INIT) { in DRX_Start()
2368 state->cscd_state = CSCD_SET; in DRX_Start()
2372 /*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) => in DRX_Start()
2373 ((SysFreq / BandWidth) * (2^21) ) - (2^23) */ in DRX_Start()
2374 feIfIncr = MulDiv32(state->sys_clock_freq * 1000, in DRX_Start()
2375 (1ULL << 21), bandwidth) - (1 << 23); in DRX_Start()
2418 if (state->operation_mode != OM_Default) { in DRX_Start()
2424 state->drxd_state = DRXD_STARTED; in DRX_Start()
2450 u32 ulClock = state->config.clock; in CDRXD()
2460 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO; in CDRXD()
2461 state->if_agc_cfg.outputLevel = 0; in CDRXD()
2462 state->if_agc_cfg.settleLevel = 140; in CDRXD()
2463 state->if_agc_cfg.minOutputLevel = 0; in CDRXD()
2464 state->if_agc_cfg.maxOutputLevel = 1023; in CDRXD()
2465 state->if_agc_cfg.speed = 904; in CDRXD()
2468 state->if_agc_cfg.ctrlMode = AGC_CTRL_USER; in CDRXD()
2469 state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel); in CDRXD()
2477 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO; in CDRXD()
2478 state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel); in CDRXD()
2479 state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel); in CDRXD()
2480 state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel); in CDRXD()
2481 state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed); in CDRXD()
2484 state->if_agc_cfg.R1 = (u16) (ulIfAgcR1); in CDRXD()
2485 state->if_agc_cfg.R2 = (u16) (ulIfAgcR2); in CDRXD()
2486 state->if_agc_cfg.R3 = (u16) (ulIfAgcR3); in CDRXD()
2488 state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1); in CDRXD()
2489 state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2); in CDRXD()
2490 state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3); in CDRXD()
2492 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO; in CDRXD()
2495 state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER; in CDRXD()
2496 state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel); in CDRXD()
2504 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO; in CDRXD()
2505 state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel); in CDRXD()
2506 state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel); in CDRXD()
2507 state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel); in CDRXD()
2508 state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed); in CDRXD()
2512 state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF; in CDRXD()
2515 state->app_env_default = (enum app_env) in CDRXD()
2518 state->app_env_diversity = (enum app_env) in CDRXD()
2523 state->noise_cal.cpOpt = 0; in CDRXD()
2524 state->noise_cal.cpNexpOfs = 40; in CDRXD()
2525 state->noise_cal.tdCal2k = -40; in CDRXD()
2526 state->noise_cal.tdCal8k = -24; in CDRXD()
2529 state->noise_cal.cpOpt = 1; in CDRXD()
2530 state->noise_cal.cpNexpOfs = 0; in CDRXD()
2531 state->noise_cal.tdCal2k = -21; in CDRXD()
2532 state->noise_cal.tdCal8k = -24; in CDRXD()
2534 state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop); in CDRXD()
2536 state->chip_adr = (state->config.demod_address << 1) | 1; in CDRXD()
2539 state->m_HiI2cPatch = DRXD_HiI2cPatch_1; in CDRXD()
2542 state->m_HiI2cPatch = DRXD_HiI2cPatch_3; in CDRXD()
2545 state->m_HiI2cPatch = NULL; in CDRXD()
2549 state->intermediate_freq = (u16) (IntermediateFrequency / 1000); in CDRXD()
2551 state->expected_sys_clock_freq = 48000; in CDRXD()
2553 state->sys_clock_freq = 48000; in CDRXD()
2554 state->osc_clock_freq = (u16) ulClock; in CDRXD()
2555 state->osc_clock_deviation = 0; in CDRXD()
2556 state->cscd_state = CSCD_INIT; in CDRXD()
2557 state->drxd_state = DRXD_UNINITIALIZED; in CDRXD()
2559 state->PGA = 0; in CDRXD()
2560 state->type_A = 0; in CDRXD()
2561 state->tuner_mirrors = 0; in CDRXD()
2564 state->insert_rs_byte = state->config.insert_rs_byte; in CDRXD()
2565 state->enable_parallel = (ulSerialMode != 1); in CDRXD()
2570 state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) * in CDRXD()
2574 state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) * in CDRXD()
2577 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER; in CDRXD()
2578 /* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */ in CDRXD()
2579 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO; in CDRXD()
2588 if (state->init_done) in DRXD_init()
2591 CDRXD(state, state->config.IF ? state->config.IF : 36000000); in DRXD_init()
2594 state->operation_mode = OM_Default; in DRXD_init()
2601 if (!state->type_A && state->m_HiI2cPatch) { in DRXD_init()
2602 status = WriteTable(state, state->m_HiI2cPatch); in DRXD_init()
2607 if (state->type_A) { in DRXD_init()
2626 state->osc_clock_deviation = 0; in DRXD_init()
2628 if (state->config.osc_deviation) in DRXD_init()
2629 state->osc_clock_deviation = in DRXD_init()
2630 state->config.osc_deviation(state->priv, 0, 0); in DRXD_init()
2634 s32 devA = (s32) (state->osc_clock_deviation) * in DRXD_init()
2635 (s32) (state->expected_sys_clock_freq); in DRXD_init()
2642 devB = (-2); in DRXD_init()
2644 /* add +1 or -1 */ in DRXD_init()
2648 state->sys_clock_freq = in DRXD_init()
2649 (u16) ((state->expected_sys_clock_freq) + in DRXD_init()
2662 if (state->type_A) { in DRXD_init()
2672 status = DownloadMicrocode(state, state->microcode, state->microcode_length); in DRXD_init()
2677 if (state->PGA) { in DRXD_init()
2678 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; in DRXD_init()
2681 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER; in DRXD_init()
2684 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO; in DRXD_init()
2708 status = SetCfgIfAgc(state, &state->if_agc_cfg); in DRXD_init()
2711 status = SetCfgRfAgc(state, &state->rf_agc_cfg); in DRXD_init()
2715 state->cscd_state = CSCD_INIT; in DRXD_init()
2739 state->drxd_state = DRXD_STOPPED; in DRXD_init()
2740 state->init_done = 1; in DRXD_init()
2766 struct drxd_state *state = fe->demodulator_priv; in drxd_read_signal_strength()
2774 *strength = 0xffff - (value << 4); in drxd_read_signal_strength()
2780 struct drxd_state *state = fe->demodulator_priv; in drxd_read_status()
2803 struct drxd_state *state = fe->demodulator_priv; in drxd_init()
2810 struct drxd_state *state = fe->demodulator_priv; in drxd_config_i2c()
2812 if (state->config.disable_i2c_gate_ctrl == 1) in drxd_config_i2c()
2821 sets->min_delay_ms = 10000; in drxd_get_tune_settings()
2822 sets->max_drift = 0; in drxd_get_tune_settings()
2823 sets->step_size = 0; in drxd_get_tune_settings()
2847 struct drxd_state *state = fe->demodulator_priv; in drxd_sleep()
2860 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in drxd_set_frontend()
2861 struct drxd_state *state = fe->demodulator_priv; in drxd_set_frontend()
2864 state->props = *p; in drxd_set_frontend()
2867 if (fe->ops.tuner_ops.set_params) { in drxd_set_frontend()
2868 fe->ops.tuner_ops.set_params(fe); in drxd_set_frontend()
2869 if (fe->ops.i2c_gate_ctrl) in drxd_set_frontend()
2870 fe->ops.i2c_gate_ctrl(fe, 0); in drxd_set_frontend()
2880 struct drxd_state *state = fe->demodulator_priv; in drxd_release()
2888 .name = "Micronas DRXD DVB-T",
2926 state->ops = drxd_ops; in drxd_attach()
2927 state->dev = dev; in drxd_attach()
2928 state->config = *config; in drxd_attach()
2929 state->i2c = i2c; in drxd_attach()
2930 state->priv = priv; in drxd_attach()
2932 mutex_init(&state->mutex); in drxd_attach()
2937 state->frontend.ops = drxd_ops; in drxd_attach()
2938 state->frontend.demodulator_priv = state; in drxd_attach()
2941 CDRXD(state, state->config.IF ? state->config.IF : 36000000); in drxd_attach()
2944 return &state->frontend; in drxd_attach()