Lines Matching +full:i2c +full:- +full:sda +full:- +full:hold +full:- +full:time +full:- +full:ns
2 Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
52 /*-----------------------------------------------------------------------------
54 ----------------------------------------------------------------------------*/
74 #define DRX39XX_MAIN_FIRMWARE "dvb-fe-drxj-mc-1.0.8.fw"
200 /*-----------------------------------------------------------------------------
202 ----------------------------------------------------------------------------*/
204 /*-----------------------------------------------------------------------------
206 ----------------------------------------------------------------------------*/
208 #define DRXJ_WAKE_UP_KEY (demod->my_i2c_dev_addr->i2c_addr)
213 * \brief Default I2C address of a demodulator instance.
231 * \brief HI timing delay for I2C timing (in nano seconds)
239 * \brief HI timing delay for I2C timing (in nano seconds)
246 * \brief Time Window for MER and SER Measurement in Units of Segment duration.
279 * \brief Maximal wait time for QAM auto constellation in ms
437 #define AUD_VOLUME_DB_MIN -60
483 * Block writes speed up I2C traffic between host and demod.
485 * x -> lowbyte(x), highbyte(x)
491 * Block read speed up I2C traffic between host and demod.
526 /*-----------------------------------------------------------------------------
528 ----------------------------------------------------------------------------*/
625 {-5,
633 {-50,
649 {-160,
774 { /* ATV RF-AGC */
782 4000 /* cut-off current */
784 { /* ATV IF-AGC */
812 * \brief Default I2C address and device identifier.
815 DRXJ_DEF_I2C_ADDR, /* i2c address */
829 (151875 - 0), /* system clock frequency in kHz */
872 1, /* nr of I2C port to which tuner is */
895 &drxj_default_addr_g, /* i2c address & device id */
975 /*-----------------------------------------------------------------------------
977 ----------------------------------------------------------------------------*/
1001 * struct drxu_code_block_hdr - Structure of the microcode block headers
1016 /*-----------------------------------------------------------------------------
1018 ----------------------------------------------------------------------------*/
1053 * This function is used to avoid floating-point calculations as they may
1056 * frac28 performs an unsigned 28/28 bits division to 32-bit fixed point
1058 * N and D can hold numbers up to width: 28-bits.
1061 * Usage condition: ((1<<28)*n)/d < ((1<<32)-1) => (n/d) < 15.999
1063 * N: 0...(1<<28)-1 = 268435454
1064 * D: 0...(1<<28)-1
1065 * Q: 0...(1<<32)-1
1073 R0 = (N % D) << 4; /* 32-28 == 4 shifts possible at max */ in frac28()
1160 /* computing y in log(x/y) = log(x) - log(y) */ in log1_times100()
1161 if ((x & (((u32) (-1)) << (scale + 1))) == 0) { in log1_times100()
1162 for (k = scale; k > 0; k--) { in log1_times100()
1169 if ((x & (((u32) (-1)) << (scale + 1))) == 0) in log1_times100()
1175 Now x has binary point between bit[scale] and bit[scale-1] in log1_times100()
1182 x &= ((((u32) 1) << scale) - 1); in log1_times100()
1184 i = (u8) (x >> (scale - index_width)); in log1_times100()
1185 /* compute delta (x-a) */ in log1_times100()
1186 d = x & ((((u32) 1) << (scale - index_width)) - 1); in log1_times100()
1189 ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - index_width)); in log1_times100()
1204 * \param N nominator 16-bits.
1205 * \param D denominator 32-bits.
1265 -conversion to short address format
1266 -access to audio block
1320 state = r_dev_addr->user_data; in drxbsp_i2c_write_read()
1321 msg[0].addr = r_dev_addr->i2c_addr >> 1; in drxbsp_i2c_write_read()
1328 state = w_dev_addr->user_data; in drxbsp_i2c_write_read()
1329 msg[0].addr = w_dev_addr->i2c_addr >> 1; in drxbsp_i2c_write_read()
1336 state = w_dev_addr->user_data; in drxbsp_i2c_write_read()
1337 msg[0].addr = w_dev_addr->i2c_addr >> 1; in drxbsp_i2c_write_read()
1341 msg[1].addr = r_dev_addr->i2c_addr >> 1; in drxbsp_i2c_write_read()
1348 if (state->i2c == NULL) { in drxbsp_i2c_write_read()
1349 pr_err("i2c was zero, aborting\n"); in drxbsp_i2c_write_read()
1352 if (i2c_transfer(state->i2c, msg, num_msgs) != num_msgs) { in drxbsp_i2c_write_read()
1353 pr_warn("drx3933: I2C write/read failed\n"); in drxbsp_i2c_write_read()
1354 return -EREMOTEIO; in drxbsp_i2c_write_read()
1361 state = w_dev_addr->user_data; in drxbsp_i2c_write_read()
1363 if (state->i2c == NULL) in drxbsp_i2c_write_read()
1366 msg[0].addr = w_dev_addr->i2c_addr; in drxbsp_i2c_write_read()
1370 msg[1].addr = r_dev_addr->i2c_addr; in drxbsp_i2c_write_read()
1376 pr_debug("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n", in drxbsp_i2c_write_read()
1377 w_dev_addr->i2c_addr, state->i2c, w_count, r_count); in drxbsp_i2c_write_read()
1379 if (i2c_transfer(state->i2c, msg, 2) != 2) { in drxbsp_i2c_write_read()
1380 pr_warn("drx3933: I2C write/read failed\n"); in drxbsp_i2c_write_read()
1381 return -EREMOTEIO; in drxbsp_i2c_write_read()
1392 * struct i2c_device_addr *dev_addr, -- address of I2C device
1393 * u32 addr, -- address of chip register/memory
1394 * u16 datasize, -- number of bytes to read
1395 * u8 *data, -- data to receive
1396 * u32 flags) -- special device flags
1408 * - 0 if reading was successful
1410 * - -EIO if anything went wrong
1426 return -EINVAL; in drxdap_fasi_read_block()
1428 overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) + in drxdap_fasi_read_block()
1436 return -EINVAL; in drxdap_fasi_read_block()
1445 /* Read block from I2C **************************************************** */ in drxdap_fasi_read_block()
1494 datasize -= todo; in drxdap_fasi_read_block()
1504 * struct i2c_device_addr *dev_addr, -- address of I2C device
1505 * u32 addr, -- address of chip register/memory
1506 * u16 *data, -- data to receive
1507 * u32 flags) -- special device flags
1509 * Read one 16-bit register or memory location. The data received back is
1513 * - 0 if reading was successful
1515 * - -EIO if anything went wrong
1527 return -EINVAL; in drxdap_fasi_read_reg16()
1537 * struct i2c_device_addr *dev_addr, -- address of I2C device
1538 * u32 addr, -- address of chip register/memory
1539 * u32 *data, -- data to receive
1540 * u32 flags) -- special device flags
1542 * Read one 32-bit register or memory location. The data received back is
1546 * - 0 if reading was successful
1548 * - -EIO if anything went wrong
1560 return -EINVAL; in drxdap_fasi_read_reg32()
1572 * struct i2c_device_addr *dev_addr, -- address of I2C device
1573 * u32 addr, -- address of chip register/memory
1574 * u16 datasize, -- number of bytes to read
1575 * u8 *data, -- data to receive
1576 * u32 flags) -- special device flags
1586 * - 0 if writing was successful
1587 * - -EIO if anything went wrong
1597 int st = -EIO; in drxdap_fasi_write_block()
1604 return -EINVAL; in drxdap_fasi_write_block()
1606 overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) + in drxdap_fasi_write_block()
1614 return -EINVAL; in drxdap_fasi_write_block()
1622 /* Write block to I2C ***************************************************** */ in drxdap_fasi_write_block()
1623 block_size = ((DRXDAP_MAX_WCHUNKSIZE) - overhead_size) & ~1; in drxdap_fasi_write_block()
1655 In single master mode block_size can be 0. In such a case this I2C in drxdap_fasi_write_block()
1656 sequense will be visible: (1) write address {i2c addr, in drxdap_fasi_write_block()
1657 4 bytes chip address} (2) write data {i2c addr, 4 bytes data } in drxdap_fasi_write_block()
1668 (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1); in drxdap_fasi_write_block()
1670 (DRXDAP_MAX_WCHUNKSIZE - overhead_size_i2c_addr) & ~1; in drxdap_fasi_write_block()
1700 datasize -= todo; in drxdap_fasi_write_block()
1711 * struct i2c_device_addr *dev_addr, -- address of I2C device
1712 * u32 addr, -- address of chip register/memory
1713 * u16 data, -- data to send
1714 * u32 flags) -- special device flags
1716 * Write one 16-bit register or memory location. The data being written is
1720 * - 0 if writing was successful
1721 * - -EIO if anything went wrong
1740 * struct i2c_device_addr *dev_addr, -- address of I2C device
1741 * u32 waddr, -- address of chip register/memory
1742 * u32 raddr, -- chip address to read back from
1743 * u16 wdata, -- data to send
1744 * u16 *rdata) -- data to receive back
1746 * Write 16-bit data, then read back the original contents of that location.
1753 * master on the I2C bus.
1756 * - 0 if reading was successful
1758 * - -EIO if anything went wrong
1767 int rc = -EIO; in drxdap_fasi_read_modify_write_reg16()
1771 return -EINVAL; in drxdap_fasi_read_modify_write_reg16()
1784 * struct i2c_device_addr *dev_addr, -- address of I2C device
1785 * u32 addr, -- address of chip register/memory
1786 * u32 data, -- data to send
1787 * u32 flags) -- special device flags
1789 * Write one 32-bit register or memory location. The data being written is
1793 * - 0 if writing was successful
1794 * - -EIO if anything went wrong
1824 * \retval -EIO Timeout, I2C error, illegal bank
1843 return -EINVAL; in drxj_dap_rm_write_reg16short()
1901 * \retval -EIO Timeout, I2C error, illegal bank
1913 int stat = -EIO; in drxj_dap_read_aud_reg16()
1917 stat = -EINVAL; in drxj_dap_read_aud_reg16()
1937 delta_timer = current_timer - start_timer; in drxj_dap_read_aud_reg16()
1939 stat = -EIO; in drxj_dap_read_aud_reg16()
1962 delta_timer = current_timer - start_timer; in drxj_dap_read_aud_reg16()
1964 stat = -EIO; in drxj_dap_read_aud_reg16()
1985 int stat = -EIO; in drxj_dap_read_reg16()
1989 return -EINVAL; in drxj_dap_read_reg16()
2008 * \retval -EIO Timeout, I2C error, illegal bank
2016 int stat = -EIO; in drxj_dap_write_aud_reg16()
2020 stat = -EINVAL; in drxj_dap_write_aud_reg16()
2041 delta_timer = current_timer - start_timer; in drxj_dap_write_aud_reg16()
2043 stat = -EIO; in drxj_dap_write_aud_reg16()
2063 int stat = -EIO; in drxj_dap_write_reg16()
2067 return -EINVAL; in drxj_dap_write_reg16()
2092 * \param dev_addr pointer to i2c dev address
2098 * \retval -EIO Timeout, I2C error, illegal bank
2115 return -EINVAL; in drxj_dap_atomic_read_write_block()
2124 hi_cmd.param3 = (u16) ((datasize / 2) - 1); in drxj_dap_atomic_read_write_block()
2189 return -EINVAL; in drxj_dap_atomic_read_reg32()
2229 * been put into one HI API function (configure). Especially the I2C bridge
2230 * enable/disable should not need re-configuration of the HI.
2240 ext_attr = (struct drxj_data *) demod->my_ext_attr; in hi_cfg_command()
2244 hi_cmd.param2 = ext_attr->hi_cfg_timing_div; in hi_cfg_command()
2245 hi_cmd.param3 = ext_attr->hi_cfg_bridge_delay; in hi_cfg_command()
2246 hi_cmd.param4 = ext_attr->hi_cfg_wake_up_key; in hi_cfg_command()
2247 hi_cmd.param5 = ext_attr->hi_cfg_ctrl; in hi_cfg_command()
2248 hi_cmd.param6 = ext_attr->hi_cfg_transmit; in hi_cfg_command()
2250 rc = hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result); in hi_cfg_command()
2257 ext_attr->hi_cfg_ctrl &= (~(SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ)); in hi_cfg_command()
2268 * \param dev_addr I2C address.
2285 switch (cmd->cmd) { in hi_command()
2289 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6, 0); in hi_command()
2294 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5, 0); in hi_command()
2299 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4, 0); in hi_command()
2304 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3, 0); in hi_command()
2311 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2, 0); in hi_command()
2316 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1, 0); in hi_command()
2327 return -EINVAL; in hi_command()
2332 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, cmd->cmd, 0); in hi_command()
2338 if ((cmd->cmd) == SIO_HI_RA_RAM_CMD_RESET) in hi_command()
2342 powerdown_cmd = (bool) ((cmd->cmd == SIO_HI_RA_RAM_CMD_CONFIG) && in hi_command()
2343 (((cmd-> in hi_command()
2382 * \retval -EIO Failure.
2385 * Need to store configuration in driver because of the way I2C
2396 ext_attr = (struct drxj_data *) demod->my_ext_attr; in init_hi()
2397 common_attr = (struct drx_common_attr *) demod->my_common_attr; in init_hi()
2398 dev_addr = demod->my_i2c_dev_addr; in init_hi()
2407 /* Timing div, 250ns/Psys */ in init_hi()
2409 ext_attr->hi_cfg_timing_div = in init_hi()
2410 (u16) ((common_attr->sys_clock_freq / 1000) * HI_I2C_DELAY) / 1000; in init_hi()
2412 if ((ext_attr->hi_cfg_timing_div) > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) in init_hi()
2413 ext_attr->hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; in init_hi()
2416 /* SDA brdige delay */ in init_hi()
2417 ext_attr->hi_cfg_bridge_delay = in init_hi()
2418 (u16) ((common_attr->osc_clock_freq / 1000) * HI_I2C_BRIDGE_DELAY) / in init_hi()
2421 if ((ext_attr->hi_cfg_bridge_delay) > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) in init_hi()
2422 ext_attr->hi_cfg_bridge_delay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M; in init_hi()
2423 /* SCL bridge delay, same as SDA for now */ in init_hi()
2424 ext_attr->hi_cfg_bridge_delay += ((ext_attr->hi_cfg_bridge_delay) << in init_hi()
2429 ext_attr->hi_cfg_wake_up_key = DRXJ_WAKE_UP_KEY; in init_hi()
2431 ext_attr->hi_cfg_ctrl = (SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE); in init_hi()
2432 /* transit mode time out delay and watch dog divider */ in init_hi()
2433 ext_attr->hi_cfg_transmit = SIO_HI_RA_RAM_PAR_6__PRE; in init_hi()
2463 * \retval -EIO Failure
2466 * * common_attr->osc_clock_freq
2467 * * ext_attr->has_lna
2468 * * ext_attr->has_ntsc
2469 * * ext_attr->has_btsc
2470 * * ext_attr->has_oob
2483 common_attr = (struct drx_common_attr *) demod->my_common_attr; in get_device_capabilities()
2484 ext_attr = (struct drxj_data *) demod->my_ext_attr; in get_device_capabilities()
2485 dev_addr = demod->my_i2c_dev_addr; in get_device_capabilities()
2509 common_attr->osc_clock_freq = 27000; in get_device_capabilities()
2513 common_attr->osc_clock_freq = 20250; in get_device_capabilities()
2517 common_attr->osc_clock_freq = 4000; in get_device_capabilities()
2520 return -EIO; in get_device_capabilities()
2532 ext_attr->mfx = (u8) ((sio_top_jtagid_lo >> 29) & 0xF); in get_device_capabilities()
2553 ext_attr->has_lna = true; in get_device_capabilities()
2554 ext_attr->has_ntsc = false; in get_device_capabilities()
2555 ext_attr->has_btsc = false; in get_device_capabilities()
2556 ext_attr->has_oob = false; in get_device_capabilities()
2557 ext_attr->has_smatx = true; in get_device_capabilities()
2558 ext_attr->has_smarx = false; in get_device_capabilities()
2559 ext_attr->has_gpio = false; in get_device_capabilities()
2560 ext_attr->has_irqn = false; in get_device_capabilities()
2563 ext_attr->has_lna = false; in get_device_capabilities()
2564 ext_attr->has_ntsc = false; in get_device_capabilities()
2565 ext_attr->has_btsc = false; in get_device_capabilities()
2566 ext_attr->has_oob = false; in get_device_capabilities()
2567 ext_attr->has_smatx = true; in get_device_capabilities()
2568 ext_attr->has_smarx = false; in get_device_capabilities()
2569 ext_attr->has_gpio = false; in get_device_capabilities()
2570 ext_attr->has_irqn = false; in get_device_capabilities()
2573 ext_attr->has_lna = true; in get_device_capabilities()
2574 ext_attr->has_ntsc = true; in get_device_capabilities()
2575 ext_attr->has_btsc = false; in get_device_capabilities()
2576 ext_attr->has_oob = false; in get_device_capabilities()
2577 ext_attr->has_smatx = true; in get_device_capabilities()
2578 ext_attr->has_smarx = true; in get_device_capabilities()
2579 ext_attr->has_gpio = true; in get_device_capabilities()
2580 ext_attr->has_irqn = false; in get_device_capabilities()
2583 ext_attr->has_lna = false; in get_device_capabilities()
2584 ext_attr->has_ntsc = true; in get_device_capabilities()
2585 ext_attr->has_btsc = false; in get_device_capabilities()
2586 ext_attr->has_oob = false; in get_device_capabilities()
2587 ext_attr->has_smatx = true; in get_device_capabilities()
2588 ext_attr->has_smarx = true; in get_device_capabilities()
2589 ext_attr->has_gpio = true; in get_device_capabilities()
2590 ext_attr->has_irqn = false; in get_device_capabilities()
2593 ext_attr->has_lna = true; in get_device_capabilities()
2594 ext_attr->has_ntsc = true; in get_device_capabilities()
2595 ext_attr->has_btsc = true; in get_device_capabilities()
2596 ext_attr->has_oob = false; in get_device_capabilities()
2597 ext_attr->has_smatx = true; in get_device_capabilities()
2598 ext_attr->has_smarx = true; in get_device_capabilities()
2599 ext_attr->has_gpio = true; in get_device_capabilities()
2600 ext_attr->has_irqn = false; in get_device_capabilities()
2603 ext_attr->has_lna = false; in get_device_capabilities()
2604 ext_attr->has_ntsc = true; in get_device_capabilities()
2605 ext_attr->has_btsc = true; in get_device_capabilities()
2606 ext_attr->has_oob = false; in get_device_capabilities()
2607 ext_attr->has_smatx = true; in get_device_capabilities()
2608 ext_attr->has_smarx = true; in get_device_capabilities()
2609 ext_attr->has_gpio = true; in get_device_capabilities()
2610 ext_attr->has_irqn = false; in get_device_capabilities()
2613 ext_attr->has_lna = true; in get_device_capabilities()
2614 ext_attr->has_ntsc = false; in get_device_capabilities()
2615 ext_attr->has_btsc = false; in get_device_capabilities()
2616 ext_attr->has_oob = true; in get_device_capabilities()
2617 ext_attr->has_smatx = true; in get_device_capabilities()
2618 ext_attr->has_smarx = true; in get_device_capabilities()
2619 ext_attr->has_gpio = true; in get_device_capabilities()
2620 ext_attr->has_irqn = true; in get_device_capabilities()
2623 ext_attr->has_lna = false; in get_device_capabilities()
2624 ext_attr->has_ntsc = true; in get_device_capabilities()
2625 ext_attr->has_btsc = true; in get_device_capabilities()
2626 ext_attr->has_oob = true; in get_device_capabilities()
2627 ext_attr->has_smatx = true; in get_device_capabilities()
2628 ext_attr->has_smarx = true; in get_device_capabilities()
2629 ext_attr->has_gpio = true; in get_device_capabilities()
2630 ext_attr->has_irqn = true; in get_device_capabilities()
2633 ext_attr->has_lna = true; in get_device_capabilities()
2634 ext_attr->has_ntsc = true; in get_device_capabilities()
2635 ext_attr->has_btsc = true; in get_device_capabilities()
2636 ext_attr->has_oob = true; in get_device_capabilities()
2637 ext_attr->has_smatx = true; in get_device_capabilities()
2638 ext_attr->has_smarx = true; in get_device_capabilities()
2639 ext_attr->has_gpio = true; in get_device_capabilities()
2640 ext_attr->has_irqn = true; in get_device_capabilities()
2643 ext_attr->has_lna = false; in get_device_capabilities()
2644 ext_attr->has_ntsc = true; in get_device_capabilities()
2645 ext_attr->has_btsc = true; in get_device_capabilities()
2646 ext_attr->has_oob = true; in get_device_capabilities()
2647 ext_attr->has_smatx = true; in get_device_capabilities()
2648 ext_attr->has_smarx = true; in get_device_capabilities()
2649 ext_attr->has_gpio = true; in get_device_capabilities()
2650 ext_attr->has_irqn = true; in get_device_capabilities()
2654 return -EIO; in get_device_capabilities()
2669 * \retval -EIO Failure, I2C or max retries reached
2684 dev_addr = demod->my_i2c_dev_addr; in power_up_device()
2686 wake_up_addr.i2c_dev_id = dev_addr->i2c_dev_id; in power_up_device()
2687 wake_up_addr.user_data = dev_addr->user_data; in power_up_device()
2689 * I2C access may fail in this case: no ack in power_up_device()
2705 /* Need some recovery time .... */ in power_up_device()
2709 return -EIO; in power_up_device()
2714 /*----------------------------------------------------------------------------*/
2715 /* MPEG Output Configuration Functions - begin */
2716 /*----------------------------------------------------------------------------*/
2750 return -EINVAL; in ctrl_set_cfg_mpeg_output()
2752 dev_addr = demod->my_i2c_dev_addr; in ctrl_set_cfg_mpeg_output()
2753 ext_attr = (struct drxj_data *) demod->my_ext_attr; in ctrl_set_cfg_mpeg_output()
2754 common_attr = (struct drx_common_attr *) demod->my_common_attr; in ctrl_set_cfg_mpeg_output()
2756 if (cfg_data->enable_mpeg_output == true) { in ctrl_set_cfg_mpeg_output()
2759 switch (ext_attr->standard) { in ctrl_set_cfg_mpeg_output()
2774 switch (ext_attr->standard) { in ctrl_set_cfg_mpeg_output()
2821 switch (ext_attr->constellation) { in ctrl_set_cfg_mpeg_output()
2838 return -EIO; in ctrl_set_cfg_mpeg_output()
2839 } /* ext_attr->constellation */ in ctrl_set_cfg_mpeg_output()
2843 (ext_attr->curr_symbol_rate / 8) * nr_bits * 188; in ctrl_set_cfg_mpeg_output()
2871 if (cfg_data->static_clk == true) { in ctrl_set_cfg_mpeg_output()
2899 /* Check insertion of the Reed-Solomon parity bytes */ in ctrl_set_cfg_mpeg_output()
2910 if (cfg_data->insert_rs_byte == true) { in ctrl_set_cfg_mpeg_output()
2915 switch (ext_attr->standard) { in ctrl_set_cfg_mpeg_output()
2921 switch (ext_attr->constellation) { in ctrl_set_cfg_mpeg_output()
2929 return -EIO; in ctrl_set_cfg_mpeg_output()
2934 /* insert_rs_byte = true -> coef = 188/188 -> 1, RS bits are in MPEG output */ in ctrl_set_cfg_mpeg_output()
2938 (u32) (common_attr->sys_clock_freq / 8))) / in ctrl_set_cfg_mpeg_output()
2942 return -EIO; in ctrl_set_cfg_mpeg_output()
2943 } /* ext_attr->standard */ in ctrl_set_cfg_mpeg_output()
2950 switch (ext_attr->standard) { in ctrl_set_cfg_mpeg_output()
2956 switch (ext_attr->constellation) { in ctrl_set_cfg_mpeg_output()
2964 return -EIO; in ctrl_set_cfg_mpeg_output()
2969 /* insert_rs_byte = false -> coef = 188/204, RS bits not in MPEG output */ in ctrl_set_cfg_mpeg_output()
2973 (u32) (common_attr->sys_clock_freq / 8))) / in ctrl_set_cfg_mpeg_output()
2977 return -EIO; in ctrl_set_cfg_mpeg_output()
2978 } /* ext_attr->standard */ in ctrl_set_cfg_mpeg_output()
2981 if (cfg_data->enable_parallel == true) { /* MPEG data output is parallel -> clear ipr_mode[0] */ in ctrl_set_cfg_mpeg_output()
2983 } else { /* MPEG data output is serial -> set ipr_mode[0] */ in ctrl_set_cfg_mpeg_output()
2988 if (cfg_data->invert_data == true) in ctrl_set_cfg_mpeg_output()
2993 if (cfg_data->invert_err == true) in ctrl_set_cfg_mpeg_output()
2998 if (cfg_data->invert_str == true) in ctrl_set_cfg_mpeg_output()
3003 if (cfg_data->invert_val == true) in ctrl_set_cfg_mpeg_output()
3008 if (cfg_data->invert_clk == true) in ctrl_set_cfg_mpeg_output()
3014 if (cfg_data->static_clk == true) { /* Static mode */ in ctrl_set_cfg_mpeg_output()
3022 switch (ext_attr->standard) { in ctrl_set_cfg_mpeg_output()
3025 if (cfg_data->insert_rs_byte == true) in ctrl_set_cfg_mpeg_output()
3031 if (cfg_data->insert_rs_byte == true) { in ctrl_set_cfg_mpeg_output()
3035 if (ext_attr->curr_symbol_rate >= in ctrl_set_cfg_mpeg_output()
3045 if (cfg_data->insert_rs_byte == true) in ctrl_set_cfg_mpeg_output()
3050 if (cfg_data->insert_rs_byte == true) in ctrl_set_cfg_mpeg_output()
3054 return -EIO; in ctrl_set_cfg_mpeg_output()
3057 common_attr->sys_clock_freq * 1000 / (fec_oc_dto_period + in ctrl_set_cfg_mpeg_output()
3060 frac28(bit_rate, common_attr->sys_clock_freq * 1000); in ctrl_set_cfg_mpeg_output()
3087 if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) in ctrl_set_cfg_mpeg_output()
3088 fec_oc_dto_period = ext_attr->mpeg_output_clock_rate - 1; in ctrl_set_cfg_mpeg_output()
3167 …if (cfg_data->enable_parallel == true) { /* MPEG data output is parallel -> set MD1 to MD7 to outp… in ctrl_set_cfg_mpeg_output()
3212 } else { /* MPEG data output is serial -> set MD1 to MD7 to tri-state */ in ctrl_set_cfg_mpeg_output()
3343 /* save values for restore after re-acquire */ in ctrl_set_cfg_mpeg_output()
3344 common_attr->mpeg_cfg.enable_mpeg_output = cfg_data->enable_mpeg_output; in ctrl_set_cfg_mpeg_output()
3351 /*----------------------------------------------------------------------------*/
3354 /*----------------------------------------------------------------------------*/
3355 /* MPEG Output Configuration Functions - end */
3356 /*----------------------------------------------------------------------------*/
3358 /*----------------------------------------------------------------------------*/
3359 /* miscellaneous configurations - begin */
3360 /*----------------------------------------------------------------------------*/
3380 dev_addr = demod->my_i2c_dev_addr; in set_mpegtei_handling()
3381 ext_attr = (struct drxj_data *) demod->my_ext_attr; in set_mpegtei_handling()
3405 if (ext_attr->disable_te_ihandling) { in set_mpegtei_handling()
3434 /*----------------------------------------------------------------------------*/
3437 * \brief Set MPEG output bit-endian settings.
3451 dev_addr = demod->my_i2c_dev_addr; in bit_reverse_mpeg_output()
3452 ext_attr = (struct drxj_data *) demod->my_ext_attr; in bit_reverse_mpeg_output()
3463 if (ext_attr->bit_reverse_mpeg_outout) in bit_reverse_mpeg_output()
3477 /*----------------------------------------------------------------------------*/
3495 dev_addr = demod->my_i2c_dev_addr; in set_mpeg_start_width()
3496 ext_attr = (struct drxj_data *) demod->my_ext_attr; in set_mpeg_start_width()
3497 common_attr = demod->my_common_attr; in set_mpeg_start_width()
3499 if ((common_attr->mpeg_cfg.static_clk == true) in set_mpeg_start_width()
3500 && (common_attr->mpeg_cfg.enable_parallel == false)) { in set_mpeg_start_width()
3507 if (ext_attr->mpeg_start_width == DRXJ_MPEG_START_WIDTH_8CLKCYC) in set_mpeg_start_width()
3521 /*----------------------------------------------------------------------------*/
3522 /* miscellaneous configurations - end */
3523 /*----------------------------------------------------------------------------*/
3525 /*----------------------------------------------------------------------------*/
3526 /* UIO Configuration Functions - begin */
3527 /*----------------------------------------------------------------------------*/
3541 return -EINVAL; in ctrl_set_uio_cfg()
3543 ext_attr = (struct drxj_data *) demod->my_ext_attr; in ctrl_set_uio_cfg()
3546 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); in ctrl_set_uio_cfg()
3551 switch (uio_cfg->uio) { in ctrl_set_uio_cfg()
3554 /* DRX_UIO1: SMA_TX UIO-1 */ in ctrl_set_uio_cfg()
3555 if (!ext_attr->has_smatx) in ctrl_set_uio_cfg()
3556 return -EIO; in ctrl_set_uio_cfg()
3557 switch (uio_cfg->mode) { in ctrl_set_uio_cfg()
3561 ext_attr->uio_sma_tx_mode = uio_cfg->mode; in ctrl_set_uio_cfg()
3564 ext_attr->uio_sma_tx_mode = uio_cfg->mode; in ctrl_set_uio_cfg()
3565 /* pad configuration register is set 0 - input mode */ in ctrl_set_uio_cfg()
3566 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0, 0); in ctrl_set_uio_cfg()
3573 return -EINVAL; in ctrl_set_uio_cfg()
3574 } /* switch ( uio_cfg->mode ) */ in ctrl_set_uio_cfg()
3578 /* DRX_UIO2: SMA_RX UIO-2 */ in ctrl_set_uio_cfg()
3579 if (!ext_attr->has_smarx) in ctrl_set_uio_cfg()
3580 return -EIO; in ctrl_set_uio_cfg()
3581 switch (uio_cfg->mode) { in ctrl_set_uio_cfg()
3584 ext_attr->uio_sma_rx_mode = uio_cfg->mode; in ctrl_set_uio_cfg()
3587 ext_attr->uio_sma_rx_mode = uio_cfg->mode; in ctrl_set_uio_cfg()
3588 /* pad configuration register is set 0 - input mode */ in ctrl_set_uio_cfg()
3589 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, 0, 0); in ctrl_set_uio_cfg()
3596 return -EINVAL; in ctrl_set_uio_cfg()
3598 } /* switch ( uio_cfg->mode ) */ in ctrl_set_uio_cfg()
3602 /* DRX_UIO3: GPIO UIO-3 */ in ctrl_set_uio_cfg()
3603 if (!ext_attr->has_gpio) in ctrl_set_uio_cfg()
3604 return -EIO; in ctrl_set_uio_cfg()
3605 switch (uio_cfg->mode) { in ctrl_set_uio_cfg()
3608 ext_attr->uio_gpio_mode = uio_cfg->mode; in ctrl_set_uio_cfg()
3611 ext_attr->uio_gpio_mode = uio_cfg->mode; in ctrl_set_uio_cfg()
3612 /* pad configuration register is set 0 - input mode */ in ctrl_set_uio_cfg()
3613 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, 0, 0); in ctrl_set_uio_cfg()
3620 return -EINVAL; in ctrl_set_uio_cfg()
3622 } /* switch ( uio_cfg->mode ) */ in ctrl_set_uio_cfg()
3626 /* DRX_UIO4: IRQN UIO-4 */ in ctrl_set_uio_cfg()
3627 if (!ext_attr->has_irqn) in ctrl_set_uio_cfg()
3628 return -EIO; in ctrl_set_uio_cfg()
3629 switch (uio_cfg->mode) { in ctrl_set_uio_cfg()
3631 ext_attr->uio_irqn_mode = uio_cfg->mode; in ctrl_set_uio_cfg()
3634 /* pad configuration register is set 0 - input mode */ in ctrl_set_uio_cfg()
3635 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, 0, 0); in ctrl_set_uio_cfg()
3640 ext_attr->uio_irqn_mode = uio_cfg->mode; in ctrl_set_uio_cfg()
3644 return -EINVAL; in ctrl_set_uio_cfg()
3646 } /* switch ( uio_cfg->mode ) */ in ctrl_set_uio_cfg()
3650 return -EINVAL; in ctrl_set_uio_cfg()
3651 } /* switch ( uio_cfg->uio ) */ in ctrl_set_uio_cfg()
3654 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); in ctrl_set_uio_cfg()
3681 return -EINVAL; in ctrl_uio_write()
3683 ext_attr = (struct drxj_data *) demod->my_ext_attr; in ctrl_uio_write()
3686 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); in ctrl_uio_write()
3691 switch (uio_data->uio) { in ctrl_uio_write()
3694 /* DRX_UIO1: SMA_TX UIO-1 */ in ctrl_uio_write()
3695 if (!ext_attr->has_smatx) in ctrl_uio_write()
3696 return -EIO; in ctrl_uio_write()
3697 if ((ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_READWRITE) in ctrl_uio_write()
3698 && (ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_FIRMWARE_SAW)) { in ctrl_uio_write()
3699 return -EIO; in ctrl_uio_write()
3707 /* write to io pad configuration register - output mode */ in ctrl_uio_write()
3708 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0); in ctrl_uio_write()
3715 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); in ctrl_uio_write()
3720 if (!uio_data->value) in ctrl_uio_write()
3721 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ in ctrl_uio_write()
3723 value |= 0x8000; /* write one to 15th bit - 1st UIO */ in ctrl_uio_write()
3726 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); in ctrl_uio_write()
3734 /* DRX_UIO2: SMA_RX UIO-2 */ in ctrl_uio_write()
3735 if (!ext_attr->has_smarx) in ctrl_uio_write()
3736 return -EIO; in ctrl_uio_write()
3737 if (ext_attr->uio_sma_rx_mode != DRX_UIO_MODE_READWRITE) in ctrl_uio_write()
3738 return -EIO; in ctrl_uio_write()
3746 /* write to io pad configuration register - output mode */ in ctrl_uio_write()
3747 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0); in ctrl_uio_write()
3754 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); in ctrl_uio_write()
3759 if (!uio_data->value) in ctrl_uio_write()
3760 value &= 0xBFFF; /* write zero to 14th bit - 2nd UIO */ in ctrl_uio_write()
3762 value |= 0x4000; /* write one to 14th bit - 2nd UIO */ in ctrl_uio_write()
3765 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); in ctrl_uio_write()
3773 /* DRX_UIO3: ASEL UIO-3 */ in ctrl_uio_write()
3774 if (!ext_attr->has_gpio) in ctrl_uio_write()
3775 return -EIO; in ctrl_uio_write()
3776 if (ext_attr->uio_gpio_mode != DRX_UIO_MODE_READWRITE) in ctrl_uio_write()
3777 return -EIO; in ctrl_uio_write()
3785 /* write to io pad configuration register - output mode */ in ctrl_uio_write()
3786 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0); in ctrl_uio_write()
3793 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, &value, 0); in ctrl_uio_write()
3798 if (!uio_data->value) in ctrl_uio_write()
3799 value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */ in ctrl_uio_write()
3801 value |= 0x0004; /* write one to 2nd bit - 3rd UIO */ in ctrl_uio_write()
3804 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, value, 0); in ctrl_uio_write()
3812 /* DRX_UIO4: IRQN UIO-4 */ in ctrl_uio_write()
3813 if (!ext_attr->has_irqn) in ctrl_uio_write()
3814 return -EIO; in ctrl_uio_write()
3816 if (ext_attr->uio_irqn_mode != DRX_UIO_MODE_READWRITE) in ctrl_uio_write()
3817 return -EIO; in ctrl_uio_write()
3825 /* write to io pad configuration register - output mode */ in ctrl_uio_write()
3826 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0); in ctrl_uio_write()
3833 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); in ctrl_uio_write()
3838 if (uio_data->value == false) in ctrl_uio_write()
3839 value &= 0xEFFF; /* write zero to 12th bit - 4th UIO */ in ctrl_uio_write()
3841 value |= 0x1000; /* write one to 12th bit - 4th UIO */ in ctrl_uio_write()
3844 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); in ctrl_uio_write()
3852 return -EINVAL; in ctrl_uio_write()
3853 } /* switch ( uio_data->uio ) */ in ctrl_uio_write()
3856 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); in ctrl_uio_write()
3867 /*---------------------------------------------------------------------------*/
3868 /* UIO Configuration Functions - end */
3869 /*---------------------------------------------------------------------------*/
3871 /*----------------------------------------------------------------------------*/
3872 /* I2C Bridge Functions - begin */
3873 /*----------------------------------------------------------------------------*/
3876 * \brief Open or close the I2C switch to tuner.
3890 return -EINVAL; in ctrl_i2c_bridge()
3899 return hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result); in ctrl_i2c_bridge()
3902 /*----------------------------------------------------------------------------*/
3903 /* I2C Bridge Functions - end */
3904 /*----------------------------------------------------------------------------*/
3906 /*----------------------------------------------------------------------------*/
3907 /* Smart antenna Functions - begin */
3908 /*----------------------------------------------------------------------------*/
3924 dev_addr = demod->my_i2c_dev_addr; in smart_ant_init()
3925 ext_attr = (struct drxj_data *) demod->my_ext_attr; in smart_ant_init()
3928 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); in smart_ant_init()
3939 if (ext_attr->smart_ant_inverted) { in smart_ant_init()
3959 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0x13, 0); in smart_ant_init()
3964 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03, 0); in smart_ant_init()
3971 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); in smart_ant_init()
3990 return -EINVAL; in scu_command()
3999 return -EIO; in scu_command()
4001 switch (cmd->parameter_len) { in scu_command()
4003 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_4__A, *(cmd->parameter + 4), 0); in scu_command()
4010 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3), 0); in scu_command()
4017 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2), 0); in scu_command()
4024 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1), 0); in scu_command()
4031 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0), 0); in scu_command()
4042 return -EIO; in scu_command()
4044 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_COMMAND__A, cmd->command, 0); in scu_command()
4064 return -EIO; in scu_command()
4067 if ((cmd->result_len > 0) && (cmd->result != NULL)) { in scu_command()
4070 switch (cmd->result_len) { in scu_command()
4072 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_3__A, cmd->result + 3, 0); in scu_command()
4079 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2, 0); in scu_command()
4086 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1, 0); in scu_command()
4093 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0, 0); in scu_command()
4104 return -EIO; in scu_command()
4108 err = cmd->result[0]; in scu_command()
4116 return -EINVAL; in scu_command()
4120 return -EIO; in scu_command()
4134 * \param dev_addr pointer to i2c dev address
4140 * \retval -EIO Timeout, I2C error, illegal bank
4143 #define ADDR_AT_SCU_SPACE(x) ((x - 0x82E000) * 2)
4155 return -EINVAL; in drxj_dap_scu_atomic_read_write_block()
4217 return -EINVAL; in drxj_dap_scu_atomic_read_reg16()
4251 /* -------------------------------------------------------------------------- */
4258 * \retval -EIO Failure: I2C error
4267 dev_addr = demod->my_i2c_dev_addr; in adc_sync_measurement()
4317 * \retval -EIO Failure: I2C error or failure to synchronize
4330 dev_addr = demod->my_i2c_dev_addr; in adc_synchronization()
4364 return -EIO; in adc_synchronization()
4411 dev_addr = demod->my_i2c_dev_addr; in init_agc()
4412 common_attr = (struct drx_common_attr *) demod->my_common_attr; in init_agc()
4413 ext_attr = (struct drxj_data *) demod->my_ext_attr; in init_agc()
4415 switch (ext_attr->standard) { in init_agc()
4418 clp_dir_to = (u16) (-9); in init_agc()
4420 sns_dir_to = (u16) (-9); in init_agc()
4421 ki_innergain_min = (u16) (-32768); in init_agc()
4493 p_agc_if_settings = &(ext_attr->vsb_if_agc_cfg); in init_agc()
4494 p_agc_rf_settings = &(ext_attr->vsb_rf_agc_cfg); in init_agc()
4502 clp_dir_to = (u16) (-5); in init_agc()
4504 sns_dir_to = (u16) (-3); in init_agc()
4561 p_agc_if_settings = &(ext_attr->qam_if_agc_cfg); in init_agc()
4562 p_agc_rf_settings = &(ext_attr->qam_rf_agc_cfg); in init_agc()
4563 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0); in init_agc()
4583 return -EINVAL; in init_agc()
4587 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_if_settings->top, 0); in init_agc()
4592 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, p_agc_if_settings->top, 0); in init_agc()
4611 } /* set to p_agc_settings->top before */ in init_agc()
4718 agc_rf = 0x800 + p_agc_rf_settings->cut_off_current; in init_agc()
4719 if (common_attr->tuner_rf_agc_pol == true) in init_agc()
4720 agc_rf = 0x87ff - agc_rf; in init_agc()
4723 if (common_attr->tuner_if_agc_pol == true) in init_agc()
4724 agc_rf = 0x87ff - agc_rf; in init_agc()
4768 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in set_frequency()
4769 struct drxj_data *ext_attr = demod->my_ext_attr; in set_frequency()
4774 s32 rf_freq_residual = -1 * tuner_freq_offset; in set_frequency()
4785 rf_mirror = (ext_attr->mirror == DRX_MIRROR_YES) ? true : false; in set_frequency()
4786 tuner_mirror = demod->my_common_attr->mirror_freq_spect ? false : true; in set_frequency()
4791 switch (ext_attr->standard) { in set_frequency()
4813 return -EINVAL; in set_frequency()
4815 intermediate_freq = demod->my_common_attr->intermediate_freq; in set_frequency()
4816 sampling_frequency = demod->my_common_attr->sys_clock_freq / 3; in set_frequency()
4820 if_freq_actual = intermediate_freq - rf_freq_residual - fm_frequency_shift; in set_frequency()
4823 adc_freq = sampling_frequency - if_freq_actual; in set_frequency()
4846 ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs; in set_frequency()
4847 ext_attr->pos_image = (bool) (rf_mirror ^ tuner_mirror ^ select_pos_image); in set_frequency()
4861 * \retval -EINVAL sig_strength is NULL.
4862 * \retval -EIO Erroneous data, sig_strength contains invalid data.
4874 ext_attr = (struct drxj_data *) demod->my_ext_attr; in get_acc_pkt_err()
4875 dev_addr = demod->my_i2c_dev_addr; in get_acc_pkt_err()
4882 if (ext_attr->reset_pkt_err_acc) { in get_acc_pkt_err()
4885 ext_attr->reset_pkt_err_acc = false; in get_acc_pkt_err()
4889 pkt_err += 0xffff - last_pkt_err; in get_acc_pkt_err()
4892 pkt_err += (data - last_pkt_err); in get_acc_pkt_err()
4924 common_attr = (struct drx_common_attr *) demod->my_common_attr; in set_agc_rf()
4925 dev_addr = demod->my_i2c_dev_addr; in set_agc_rf()
4926 ext_attr = (struct drxj_data *) demod->my_ext_attr; in set_agc_rf()
4937 if ((ext_attr->standard == agc_settings->standard) || in set_agc_rf()
4938 (DRXJ_ISQAMSTD(ext_attr->standard) && in set_agc_rf()
4939 DRXJ_ISQAMSTD(agc_settings->standard)) || in set_agc_rf()
4940 (DRXJ_ISATVSTD(ext_attr->standard) && in set_agc_rf()
4941 DRXJ_ISATVSTD(agc_settings->standard))) { in set_agc_rf()
4944 switch (agc_settings->ctrl_mode) { in set_agc_rf()
4967 if (ext_attr->standard == DRX_STANDARD_8VSB) in set_agc_rf()
4969 else if (DRXJ_ISQAMSTD(ext_attr->standard)) in set_agc_rf()
4974 if (common_attr->tuner_rf_agc_pol) in set_agc_rf()
4991 …rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_RAG… in set_agc_rf()
4997 if (agc_settings->standard == DRX_STANDARD_8VSB) in set_agc_rf()
4998 p_agc_settings = &(ext_attr->vsb_if_agc_cfg); in set_agc_rf()
4999 else if (DRXJ_ISQAMSTD(agc_settings->standard)) in set_agc_rf()
5000 p_agc_settings = &(ext_attr->qam_if_agc_cfg); in set_agc_rf()
5001 else if (DRXJ_ISATVSTD(agc_settings->standard)) in set_agc_rf()
5002 p_agc_settings = &(ext_attr->atv_if_agc_cfg); in set_agc_rf()
5004 return -EINVAL; in set_agc_rf()
5006 /* Set TOP, only if IF-AGC is in AUTO mode */ in set_agc_rf()
5007 if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) { in set_agc_rf()
5008 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->top, 0); in set_agc_rf()
5013 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, agc_settings->top, 0); in set_agc_rf()
5020 /* Cut-Off current */ in set_agc_rf()
5021 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, agc_settings->cut_off_current, 0); in set_agc_rf()
5049 if (common_attr->tuner_rf_agc_pol) in set_agc_rf()
5060 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, agc_settings->output_level, 0); in set_agc_rf()
5095 return -EINVAL; in set_agc_rf()
5096 } /* switch ( agcsettings->ctrl_mode ) */ in set_agc_rf()
5100 switch (agc_settings->standard) { in set_agc_rf()
5102 ext_attr->vsb_rf_agc_cfg = *agc_settings; in set_agc_rf()
5108 ext_attr->qam_rf_agc_cfg = *agc_settings; in set_agc_rf()
5112 return -EIO; in set_agc_rf()
5138 common_attr = (struct drx_common_attr *) demod->my_common_attr; in set_agc_if()
5139 dev_addr = demod->my_i2c_dev_addr; in set_agc_if()
5140 ext_attr = (struct drxj_data *) demod->my_ext_attr; in set_agc_if()
5151 if ((ext_attr->standard == agc_settings->standard) || in set_agc_if()
5152 (DRXJ_ISQAMSTD(ext_attr->standard) && in set_agc_if()
5153 DRXJ_ISQAMSTD(agc_settings->standard)) || in set_agc_if()
5154 (DRXJ_ISATVSTD(ext_attr->standard) && in set_agc_if()
5155 DRXJ_ISATVSTD(agc_settings->standard))) { in set_agc_if()
5158 switch (agc_settings->ctrl_mode) { in set_agc_if()
5181 if (ext_attr->standard == DRX_STANDARD_8VSB) in set_agc_if()
5183 else if (DRXJ_ISQAMSTD(ext_attr->standard)) in set_agc_if()
5188 if (common_attr->tuner_if_agc_pol) in set_agc_if()
5205 …rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_IA… in set_agc_if()
5211 if (agc_settings->standard == DRX_STANDARD_8VSB) in set_agc_if()
5212 p_agc_settings = &(ext_attr->vsb_rf_agc_cfg); in set_agc_if()
5213 else if (DRXJ_ISQAMSTD(agc_settings->standard)) in set_agc_if()
5214 p_agc_settings = &(ext_attr->qam_rf_agc_cfg); in set_agc_if()
5215 else if (DRXJ_ISATVSTD(agc_settings->standard)) in set_agc_if()
5216 p_agc_settings = &(ext_attr->atv_rf_agc_cfg); in set_agc_if()
5218 return -EINVAL; in set_agc_if()
5221 if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) { in set_agc_if()
5222 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_settings->top, 0); in set_agc_if()
5227 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, p_agc_settings->top, 0); in set_agc_if()
5269 if (common_attr->tuner_if_agc_pol) in set_agc_if()
5280 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->output_level, 0); in set_agc_if()
5317 return -EINVAL; in set_agc_if()
5318 } /* switch ( agcsettings->ctrl_mode ) */ in set_agc_if()
5320 /* always set the top to support configurations without if-loop */ in set_agc_if()
5321 rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, agc_settings->top, 0); in set_agc_if()
5329 switch (agc_settings->standard) { in set_agc_if()
5331 ext_attr->vsb_if_agc_cfg = *agc_settings; in set_agc_if()
5337 ext_attr->qam_if_agc_cfg = *agc_settings; in set_agc_if()
5341 return -EIO; in set_agc_if()
5362 dev_addr = demod->my_i2c_dev_addr; in set_iqm_af()
5404 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in power_down_vsb()
5692 dev_addr = demod->my_i2c_dev_addr; in set_vsb_leak_n_gain()
5726 DRXJ_16TO8(-2), /* re0 */ in set_vsb()
5729 DRXJ_16TO8(-4), /* re3 */ in set_vsb()
5732 DRXJ_16TO8(-3), /* re6 */ in set_vsb()
5733 DRXJ_16TO8(-3), /* re7 */ in set_vsb()
5736 DRXJ_16TO8(-9), /* re10 */ in set_vsb()
5739 DRXJ_16TO8(-9), /* re13 */ in set_vsb()
5740 DRXJ_16TO8(-15), /* re14 */ in set_vsb()
5743 DRXJ_16TO8(-29), /* re17 */ in set_vsb()
5744 DRXJ_16TO8(-22), /* re18 */ in set_vsb()
5747 DRXJ_16TO8(-70), /* re21 */ in set_vsb()
5748 DRXJ_16TO8(-28), /* re22 */ in set_vsb()
5751 DRXJ_16TO8(-201), /* re25 */ in set_vsb()
5752 DRXJ_16TO8(-31), /* re26 */ in set_vsb()
5756 dev_addr = demod->my_i2c_dev_addr; in set_vsb()
5757 common_attr = (struct drx_common_attr *) demod->my_common_attr; in set_vsb()
5758 ext_attr = (struct drxj_data *) demod->my_ext_attr; in set_vsb()
5825 ext_attr->iqm_rc_rate_ofs = 0x00AD0D79; in set_vsb()
5826 rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0); in set_vsb()
6041 /* B-Input to ADC, PGA+filter in standby */ in set_vsb()
6042 if (!ext_attr->has_lna) { in set_vsb()
6067 rc = set_agc_if(demod, &(ext_attr->vsb_if_agc_cfg), false); in set_vsb()
6072 rc = set_agc_rf(demod, &(ext_attr->vsb_rf_agc_cfg), false); in set_vsb()
6082 vsb_pga_cfg.gain = ext_attr->vsb_pga_cfg; in set_vsb()
6089 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->vsb_pre_saw_cfg)); in set_vsb()
6116 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output)); in set_vsb()
6241 /* 77.3 us is time for per packet */ in get_vsb_post_rs_pck_err()
6244 return -EIO; in get_vsb_post_rs_pck_err()
6288 return -EIO; in get_vs_bpost_viterbi_ber()
6291 (bit_errors_exp - 3) : bit_errors_exp); in get_vs_bpost_viterbi_ber()
6313 return -EIO; in get_vs_bpre_viterbi_ber()
6337 (u16) (log1_times100(21504) - log1_times100((data_hi << 6) / 52)); in get_vsbmer()
6371 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in power_down_qam()
6373 struct drx_common_attr *common_attr = demod->my_common_attr; in power_down_qam()
6443 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output)); in power_down_qam()
6470 * TODO: overriding the ext_attr->fec_bits_desired by constellation dependent
6480 struct i2c_device_addr *dev_addr = NULL; /* device address for I2C writes */ in set_qam_measurement()
6486 u32 fec_rs_period = 0; /* Value for corresponding I2C register */ in set_qam_measurement()
6488 u32 fec_oc_snc_fail_period = 0; /* Value for corresponding I2C register */ in set_qam_measurement()
6489 u32 qam_vd_period = 0; /* Value for corresponding I2C register */ in set_qam_measurement()
6494 dev_addr = demod->my_i2c_dev_addr; in set_qam_measurement()
6495 ext_attr = (struct drxj_data *) demod->my_ext_attr; in set_qam_measurement()
6497 fec_bits_desired = ext_attr->fec_bits_desired; in set_qam_measurement()
6498 fec_rs_prescale = ext_attr->fec_rs_prescale; in set_qam_measurement()
6517 return -EINVAL; in set_qam_measurement()
6520 /* Parameters for Reed-Solomon Decoder */ in set_qam_measurement()
6523 /* result is within 32 bit arithmetic -> */ in set_qam_measurement()
6527 switch (ext_attr->standard) { in set_qam_measurement()
6536 return -EINVAL; in set_qam_measurement()
6539 ext_attr->fec_rs_plen = fec_rs_plen; /* for getSigQual */ in set_qam_measurement()
6543 return -EIO; in set_qam_measurement()
6546 if (ext_attr->standard != DRX_STANDARD_ITU_B) in set_qam_measurement()
6549 /* limit to max 16 bit value (I2C register width) if needed */ in set_qam_measurement()
6554 switch (ext_attr->standard) { in set_qam_measurement()
6569 return -EINVAL; in set_qam_measurement()
6573 return -EINVAL; in set_qam_measurement()
6591 ext_attr->fec_rs_period = (u16) fec_rs_period; in set_qam_measurement()
6592 ext_attr->fec_rs_prescale = fec_rs_prescale; in set_qam_measurement()
6609 if (ext_attr->standard == DRX_STANDARD_ITU_B) { in set_qam_measurement()
6614 /* result is within 32 bit arithmetic -> */ in set_qam_measurement()
6618 fec_vd_plen = ext_attr->fec_vd_plen; in set_qam_measurement()
6619 qam_vd_prescale = ext_attr->qam_vd_prescale; in set_qam_measurement()
6636 return -EINVAL; in set_qam_measurement()
6640 return -EIO; in set_qam_measurement()
6643 /* limit to max 16 bit value (I2C register width) if needed */ in set_qam_measurement()
6660 ext_attr->qam_vd_period = (u16) qam_vd_period; in set_qam_measurement()
6661 ext_attr->qam_vd_prescale = qam_vd_prescale; in set_qam_measurement()
6679 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in set_qam16()
6776 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-24), 0); in set_qam16()
6781 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-65), 0); in set_qam16()
6786 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-127), 0); in set_qam16()
6914 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in set_qam32()
7001 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16)(-8), 0); in set_qam32()
7006 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16)(-16), 0); in set_qam32()
7011 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-26), 0); in set_qam32()
7016 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-56), 0); in set_qam32()
7021 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-86), 0); in set_qam32()
7149 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in set_qam64()
7152 /* this is hw reset value. no necessary to re-write */ in set_qam64()
7247 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-15), 0); in set_qam64()
7252 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-45), 0); in set_qam64()
7257 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-80), 0); in set_qam64()
7385 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in set_qam128()
7482 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-1), 0); in set_qam128()
7492 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-23), 0); in set_qam128()
7620 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in set_qam256()
7727 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-8), 0); in set_qam256()
7879 DRXJ_16TO8(-1), /* re0 */ in set_qam()
7882 DRXJ_16TO8(-1), /* re3 */ in set_qam()
7883 DRXJ_16TO8(-1), /* re4 */ in set_qam()
7886 DRXJ_16TO8(-2), /* re7 */ in set_qam()
7889 DRXJ_16TO8(-1), /* re10 */ in set_qam()
7890 DRXJ_16TO8(-3), /* re11 */ in set_qam()
7893 DRXJ_16TO8(-8), /* re14 */ in set_qam()
7896 DRXJ_16TO8(-13), /* re17 */ in set_qam()
7897 DRXJ_16TO8(-19), /* re18 */ in set_qam()
7900 DRXJ_16TO8(-53), /* re21 */ in set_qam()
7901 DRXJ_16TO8(-31), /* re22 */ in set_qam()
7904 DRXJ_16TO8(-190), /* re25 */ in set_qam()
7905 DRXJ_16TO8(-40), /* re26 */ in set_qam()
7910 DRXJ_16TO8(-2), /* re1 */ in set_qam()
7913 DRXJ_16TO8(-2), /* re4 */ in set_qam()
7916 DRXJ_16TO8(-2), /* re7 */ in set_qam()
7917 DRXJ_16TO8(-4), /* re8 */ in set_qam()
7920 DRXJ_16TO8(-6), /* re11 */ in set_qam()
7923 DRXJ_16TO8(-5), /* re14 */ in set_qam()
7924 DRXJ_16TO8(-3), /* re15 */ in set_qam()
7926 DRXJ_16TO8(-4), /* re17 */ in set_qam()
7927 DRXJ_16TO8(-19), /* re18 */ in set_qam()
7930 DRXJ_16TO8(-45), /* re21 */ in set_qam()
7931 DRXJ_16TO8(-36), /* re22 */ in set_qam()
7934 DRXJ_16TO8(-185), /* re25 */ in set_qam()
7935 DRXJ_16TO8(-46), /* re26 */ in set_qam()
7939 DRXJ_16TO8(-2), /* re0 */ in set_qam()
7942 DRXJ_16TO8(-4), /* re3 */ in set_qam()
7945 DRXJ_16TO8(-2), /* re6 */ in set_qam()
7946 DRXJ_16TO8(-4), /* re7 */ in set_qam()
7949 DRXJ_16TO8(-8), /* re10 */ in set_qam()
7952 DRXJ_16TO8(-8), /* re13 */ in set_qam()
7953 DRXJ_16TO8(-15), /* re14 */ in set_qam()
7956 DRXJ_16TO8(-27), /* re17 */ in set_qam()
7957 DRXJ_16TO8(-22), /* re18 */ in set_qam()
7960 DRXJ_16TO8(-69), /* re21 */ in set_qam()
7961 DRXJ_16TO8(-28), /* re22 */ in set_qam()
7964 DRXJ_16TO8(-201), /* re25 */ in set_qam()
7965 DRXJ_16TO8(-32), /* re26 */ in set_qam()
7969 DRXJ_16TO8(-3), /* re0 */ in set_qam()
7972 DRXJ_16TO8(-4), /* re3 */ in set_qam()
7975 DRXJ_16TO8(-1), /* re6 */ in set_qam()
7976 DRXJ_16TO8(-4), /* re7 */ in set_qam()
7979 DRXJ_16TO8(-5), /* re10 */ in set_qam()
7982 DRXJ_16TO8(-4), /* re13 */ in set_qam()
7983 DRXJ_16TO8(-12), /* re14 */ in set_qam()
7986 DRXJ_16TO8(-21), /* re17 */ in set_qam()
7987 DRXJ_16TO8(-20), /* re18 */ in set_qam()
7990 DRXJ_16TO8(-62), /* re21 */ in set_qam()
7991 DRXJ_16TO8(-28), /* re22 */ in set_qam()
7994 DRXJ_16TO8(-197), /* re25 */ in set_qam()
7995 DRXJ_16TO8(-33), /* re26 */ in set_qam()
7999 dev_addr = demod->my_i2c_dev_addr; in set_qam()
8000 ext_attr = (struct drxj_data *) demod->my_ext_attr; in set_qam()
8001 common_attr = (struct drx_common_attr *) demod->my_common_attr; in set_qam()
8004 if (ext_attr->standard == DRX_STANDARD_ITU_B) { in set_qam()
8005 switch (channel->constellation) { in set_qam()
8010 channel->symbolrate = 5360537; in set_qam()
8016 channel->symbolrate = 5056941; in set_qam()
8020 return -EINVAL; in set_qam()
8023 adc_frequency = (common_attr->sys_clock_freq * 1000) / 3; in set_qam()
8024 if (channel->symbolrate == 0) { in set_qam()
8026 return -EIO; in set_qam()
8029 (adc_frequency / channel->symbolrate) * (1 << 21) + in set_qam()
8031 ((adc_frequency % channel->symbolrate), in set_qam()
8032 channel->symbolrate) >> 7) - (1 << 23); in set_qam()
8035 (channel->symbolrate + in set_qam()
8044 if (ext_attr->standard == DRX_STANDARD_ITU_A) { in set_qam()
8046 set_param_parameters[0] = channel->constellation; /* constellation */ in set_qam()
8048 } else if (ext_attr->standard == DRX_STANDARD_ITU_B) { in set_qam()
8050 set_param_parameters[0] = channel->constellation; /* constellation */ in set_qam()
8051 set_param_parameters[1] = channel->interleavemode; /* interleave mode */ in set_qam()
8052 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) { in set_qam()
8054 set_param_parameters[0] = channel->constellation; /* constellation */ in set_qam()
8057 return -EINVAL; in set_qam()
8120 -set env in set_qam()
8121 -set params (resets IQM,QAM,FEC HW; initializes some SCU variables ) in set_qam()
8152 ext_attr->iqm_rc_rate_ofs = iqm_rc_rate; in set_qam()
8153 rc = set_qam_measurement(demod, channel->constellation, channel->symbolrate); in set_qam()
8162 /* TODO: remove re-writes of HW reset values */ in set_qam()
8186 if (!ext_attr->has_lna) { in set_qam()
8267 if (ext_attr->standard == DRX_STANDARD_ITU_B) { in set_qam()
8284 switch (channel->constellation) { in set_qam()
8323 return -EIO; in set_qam()
8473 rc = set_agc_if(demod, &(ext_attr->qam_if_agc_cfg), false); in set_qam()
8478 rc = set_agc_rf(demod, &(ext_attr->qam_rf_agc_cfg), false); in set_qam()
8488 qam_pga_cfg.gain = ext_attr->qam_pga_cfg; in set_qam()
8495 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->qam_pre_saw_cfg)); in set_qam()
8503 if (ext_attr->standard == DRX_STANDARD_ITU_A) { in set_qam()
8514 } else if (ext_attr->standard == DRX_STANDARD_ITU_B) { in set_qam()
8515 switch (channel->constellation) { in set_qam()
8541 return -EIO; in set_qam()
8543 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) { in set_qam()
8557 switch (channel->constellation) { in set_qam()
8594 return -EIO; in set_qam()
8626 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output)); in set_qam()
8679 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in qam_flip_spec()
8680 struct drxj_data *ext_attr = demod->my_ext_attr; in qam_flip_spec()
8725 ofsofs = iqm_fs_rate_lo - iqm_fs_rate_ofs; in qam_flip_spec()
8727 iqm_fs_rate_ofs -= 2 * ofsofs; in qam_flip_spec()
8770 ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs; in qam_flip_spec()
8771 ext_attr->pos_image = (ext_attr->pos_image) ? false : true; in qam_flip_spec()
8798 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data, 0); in qam_flip_spec()
8811 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data, 0); in qam_flip_spec()
8874 struct drxj_data *ext_attr = demod->my_ext_attr; in qam64auto()
8875 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in qam64auto()
8876 struct drx39xxj_state *state = dev_addr->user_data; in qam64auto()
8877 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache; in qam64auto()
8904 if (p->cnr.stat[0].svalue > 20800) { in qam64auto()
8914 ((jiffies_to_msecs(jiffies) - d_locked_time) > in qam64auto()
8916 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); in qam64auto()
8921 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0); in qam64auto()
8932 if (channel->mirror == DRX_MIRROR_AUTO) { in qam64auto()
8934 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); in qam64auto()
8939 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data & 0xFFFE, 0); in qam64auto()
8945 ext_attr->mirror = DRX_MIRROR_YES; in qam64auto()
8959 jiffies_to_msecs(jiffies) - in qam64auto()
8960 DRXJ_QAM_MAX_WAITTIME - timeout_ofs; in qam64auto()
8966 ((jiffies_to_msecs(jiffies) - d_locked_time) > in qam64auto()
8973 if (p->cnr.stat[0].svalue > 20800) { in qam64auto()
8974 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); in qam64auto()
8979 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0); in qam64auto()
8986 jiffies_to_msecs(jiffies) - in qam64auto()
8987 DRXJ_QAM_MAX_WAITTIME - timeout_ofs; in qam64auto()
8998 ((jiffies_to_msecs(jiffies) - start_time) < in qam64auto()
9022 struct drxj_data *ext_attr = demod->my_ext_attr; in qam256auto()
9023 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in qam256auto()
9024 struct drx39xxj_state *state = dev_addr->user_data; in qam256auto()
9025 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache; in qam256auto()
9050 if (p->cnr.stat[0].svalue > 26800) { in qam256auto()
9059 if ((channel->mirror == DRX_MIRROR_AUTO) && in qam256auto()
9060 ((jiffies_to_msecs(jiffies) - d_locked_time) > in qam256auto()
9062 ext_attr->mirror = DRX_MIRROR_YES; in qam256auto()
9071 timeout_ofs = -DRXJ_QAM_MAX_WAITTIME / 2; in qam256auto()
9084 ((jiffies_to_msecs(jiffies) - start_time) < in qam256auto()
9109 ext_attr = (struct drxj_data *) demod->my_ext_attr; in set_qam_channel()
9112 switch (channel->constellation) { in set_qam_channel()
9116 return -EINVAL; in set_qam_channel()
9119 if (ext_attr->standard != DRX_STANDARD_ITU_B) in set_qam_channel()
9120 return -EINVAL; in set_qam_channel()
9122 ext_attr->constellation = channel->constellation; in set_qam_channel()
9123 if (channel->mirror == DRX_MIRROR_AUTO) in set_qam_channel()
9124 ext_attr->mirror = DRX_MIRROR_NO; in set_qam_channel()
9126 ext_attr->mirror = channel->mirror; in set_qam_channel()
9134 if (channel->constellation == DRX_CONSTELLATION_QAM64) in set_qam_channel()
9146 if (ext_attr->standard == DRX_STANDARD_ITU_B) { in set_qam_channel()
9152 channel->constellation = DRX_CONSTELLATION_QAM256; in set_qam_channel()
9153 ext_attr->constellation = DRX_CONSTELLATION_QAM256; in set_qam_channel()
9154 if (channel->mirror == DRX_MIRROR_AUTO) in set_qam_channel()
9155 ext_attr->mirror = DRX_MIRROR_NO; in set_qam_channel()
9157 ext_attr->mirror = channel->mirror; in set_qam_channel()
9172 channel->constellation = DRX_CONSTELLATION_AUTO; in set_qam_channel()
9177 channel->constellation = DRX_CONSTELLATION_QAM64; in set_qam_channel()
9178 ext_attr->constellation = DRX_CONSTELLATION_QAM64; in set_qam_channel()
9179 if (channel->mirror == DRX_MIRROR_AUTO) in set_qam_channel()
9180 ext_attr->mirror = DRX_MIRROR_NO; in set_qam_channel()
9182 ext_attr->mirror = channel->mirror; in set_qam_channel()
9184 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9191 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9198 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9212 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9227 channel->constellation = DRX_CONSTELLATION_AUTO; in set_qam_channel()
9228 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) { in set_qam_channel()
9231 channel->constellation = DRX_CONSTELLATION_QAM64; in set_qam_channel()
9232 ext_attr->constellation = DRX_CONSTELLATION_QAM64; in set_qam_channel()
9235 if (channel->mirror == DRX_MIRROR_AUTO) in set_qam_channel()
9236 ext_attr->mirror = DRX_MIRROR_NO; in set_qam_channel()
9238 ext_attr->mirror = channel->mirror; in set_qam_channel()
9239 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9246 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9253 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9267 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9280 channel->constellation = DRX_CONSTELLATION_AUTO; in set_qam_channel()
9282 return -EINVAL; in set_qam_channel()
9286 return -EINVAL; in set_qam_channel()
9293 channel->constellation = DRX_CONSTELLATION_AUTO; in set_qam_channel()
9318 return -EINVAL; in get_qamrs_err_count()
9353 /* These register values are fetched in non-atomic fashion */ in get_qamrs_err_count()
9356 rs_errors->nr_bit_errors = nr_bit_errors & FEC_RS_NR_BIT_ERRORS__M; in get_qamrs_err_count()
9357 rs_errors->nr_symbol_errors = nr_symbol_errors & FEC_RS_NR_SYMBOL_ERRORS__M; in get_qamrs_err_count()
9358 rs_errors->nr_packet_errors = nr_packet_errors & FEC_RS_NR_PACKET_ERRORS__M; in get_qamrs_err_count()
9359 rs_errors->nr_failures = nr_failures & FEC_RS_NR_FAILURES__M; in get_qamrs_err_count()
9360 rs_errors->nr_snc_par_fail_count = in get_qamrs_err_count()
9374 * \param u16-t Pointer to signal strength data; range 0, .. , 100.
9377 * \retval -EINVAL sig_strength is NULL.
9378 * \retval -EIO Erroneous data, sig_strength contains invalid data.
9387 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in get_sig_strength()
9420 return -EIO; in get_sig_strength()
9423 75 + 25 * (rf_gain - rf_agc_min) / (rf_agc_max - in get_sig_strength()
9430 return -EIO; in get_sig_strength()
9433 20 + 55 * (if_gain - if_agc_sns) / (if_agc_top - if_agc_sns); in get_sig_strength()
9437 return -EIO; in get_sig_strength()
9457 * \retval -EINVAL sig_quality is NULL.
9458 * \retval -EIO Erroneous data, sig_quality contains invalid data.
9460 * Pre-condition: Device must be started and in lock.
9465 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in ctrl_get_qam_sig_quality()
9466 struct drxj_data *ext_attr = demod->my_ext_attr; in ctrl_get_qam_sig_quality()
9467 struct drx39xxj_state *state = dev_addr->user_data; in ctrl_get_qam_sig_quality()
9468 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache; in ctrl_get_qam_sig_quality()
9470 enum drx_modulation constellation = ext_attr->constellation; in ctrl_get_qam_sig_quality()
9480 u16 fec_rs_period = 0; /* Value for corresponding I2C register */ in ctrl_get_qam_sig_quality()
9497 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_get_qam_sig_quality()
9520 fec_rs_period = ext_attr->fec_rs_period; in ctrl_get_qam_sig_quality()
9521 fec_rs_prescale = ext_attr->fec_rs_prescale; in ctrl_get_qam_sig_quality()
9522 rs_bit_cnt = fec_rs_period * fec_rs_prescale * ext_attr->fec_rs_plen; in ctrl_get_qam_sig_quality()
9523 qam_vd_period = ext_attr->qam_vd_period; in ctrl_get_qam_sig_quality()
9524 qam_vd_prescale = ext_attr->qam_vd_prescale; in ctrl_get_qam_sig_quality()
9525 vd_bit_cnt = qam_vd_period * qam_vd_prescale * ext_attr->fec_vd_plen; in ctrl_get_qam_sig_quality()
9545 return -EIO; in ctrl_get_qam_sig_quality()
9548 /* ------------------------------ */ in ctrl_get_qam_sig_quality()
9550 /* ------------------------------ */ in ctrl_get_qam_sig_quality()
9557 qam_sl_mer = log1_times100(qam_sl_sig_power) - log1_times100((u32)qam_sl_err_power); in ctrl_get_qam_sig_quality()
9559 /* ----------------------------------------- */ in ctrl_get_qam_sig_quality()
9561 /* ----------------------------------------- */ in ctrl_get_qam_sig_quality()
9581 qam_vd_ser = m << ((e > 2) ? (e - 3) : e); in ctrl_get_qam_sig_quality()
9583 /* --------------------------------------- */ in ctrl_get_qam_sig_quality()
9585 /* --------------------------------------- */ in ctrl_get_qam_sig_quality()
9586 /* pre RS BER is good if it is below 3.5e-4 */ in ctrl_get_qam_sig_quality()
9593 /* pre Reed-Solomon bit error count */ in ctrl_get_qam_sig_quality()
9627 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; in ctrl_get_qam_sig_quality()
9628 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; in ctrl_get_qam_sig_quality()
9629 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; in ctrl_get_qam_sig_quality()
9630 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; in ctrl_get_qam_sig_quality()
9631 p->block_error.stat[0].scale = FE_SCALE_COUNTER; in ctrl_get_qam_sig_quality()
9632 p->cnr.stat[0].scale = FE_SCALE_DECIBEL; in ctrl_get_qam_sig_quality()
9634 p->cnr.stat[0].svalue = ((u16) qam_sl_mer) * 100; in ctrl_get_qam_sig_quality()
9635 if (ext_attr->standard == DRX_STANDARD_ITU_B) { in ctrl_get_qam_sig_quality()
9636 p->pre_bit_error.stat[0].uvalue += qam_vd_ser; in ctrl_get_qam_sig_quality()
9637 p->pre_bit_count.stat[0].uvalue += vd_bit_cnt * ((e > 2) ? 1 : 8) / 8; in ctrl_get_qam_sig_quality()
9639 p->pre_bit_error.stat[0].uvalue += qam_pre_rs_ber; in ctrl_get_qam_sig_quality()
9640 p->pre_bit_count.stat[0].uvalue += rs_bit_cnt >> e; in ctrl_get_qam_sig_quality()
9643 p->post_bit_error.stat[0].uvalue += qam_post_rs_ber; in ctrl_get_qam_sig_quality()
9644 p->post_bit_count.stat[0].uvalue += rs_bit_cnt >> e; in ctrl_get_qam_sig_quality()
9646 p->block_error.stat[0].uvalue += pkt_errs; in ctrl_get_qam_sig_quality()
9649 rc = get_acc_pkt_err(demod, &sig_quality->packet_error); in ctrl_get_qam_sig_quality()
9658 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_get_qam_sig_quality()
9659 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_get_qam_sig_quality()
9660 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_get_qam_sig_quality()
9661 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_get_qam_sig_quality()
9662 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_get_qam_sig_quality()
9663 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_get_qam_sig_quality()
9715 has to perform these settings each time the ATV or FM standards is
9734 /* -------------------------------------------------------------------------- */
9750 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in power_down_atv()
9849 dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr; in power_down_aud()
9850 ext_attr = (struct drxj_data *) demod->my_ext_attr; in power_down_aud()
9858 ext_attr->aud_data.audio_is_active = false; in power_down_aud()
9874 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in set_orx_nsu_aox()
9916 #define IMPULSE_COSINE_ALPHA_0_3 {-3, -4, -1, 6, 10, 7, -5, -20, -25, -10, 29, 79, 123, 140} /*s…
9917 #define IMPULSE_COSINE_ALPHA_0_5 { 2, 0, -2, -2, 2, 5, 2, -10, -20, -14, 20, 74, 125, 145} /*sqr…
9918 …ne IMPULSE_COSINE_ALPHA_RO_0_5 { 0, 0, 1, 2, 3, 0, -7, -15, -16, 0, 34, 77, 114, 128} /*full rais…
9943 …{DRXJ_16TO8(-92), DRXJ_16TO8(-108), DRXJ_16TO8(100)}, /* TARGET_MODE = 0: PFI_A = -23/32; PFI_… in ctrl_set_oob()
9944 …{DRXJ_16TO8(-64), DRXJ_16TO8(-80), DRXJ_16TO8(80)}, /* TARGET_MODE = 1: PFI_A = -16/32; PFI_B … in ctrl_set_oob()
9945 …{DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)}, /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B … in ctrl_set_oob()
9946 …{DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)} /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B =… in ctrl_set_oob()
9950 dev_addr = demod->my_i2c_dev_addr; in ctrl_set_oob()
9951 ext_attr = (struct drxj_data *) demod->my_ext_attr; in ctrl_set_oob()
9952 mirror_freq_spect_oob = ext_attr->mirror_freq_spect_oob; in ctrl_set_oob()
9978 ext_attr->oob_power_on = false; in ctrl_set_oob()
9982 freq = oob_param->frequency; in ctrl_set_oob()
9984 return -EIO; in ctrl_set_oob()
9985 freq = (freq - 50000) / 50; in ctrl_set_oob()
9990 u16 *trk_filtercfg = ext_attr->oob_trk_filter_cfg; in ctrl_set_oob()
9992 index = (u16) ((freq - 400) / 200); in ctrl_set_oob()
9993 remainder = (u16) ((freq - 400) % 200); in ctrl_set_oob()
9995 trk_filtercfg[index] - (trk_filtercfg[index] - in ctrl_set_oob()
10039 /* 1-data rate;2-frequency */ in ctrl_set_oob()
10040 switch (oob_param->standard) { in ctrl_set_oob()
10044 ((oob_param->spectrum_inverted == true) && in ctrl_set_oob()
10049 ((oob_param->spectrum_inverted == false) && in ctrl_set_oob()
10062 ((oob_param->spectrum_inverted == true) && in ctrl_set_oob()
10067 ((oob_param->spectrum_inverted == false) && in ctrl_set_oob()
10081 ((oob_param->spectrum_inverted == true) && in ctrl_set_oob()
10086 ((oob_param->spectrum_inverted == false) && in ctrl_set_oob()
10154 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0); in ctrl_set_oob()
10194 /* AGN_LOCK = {2048>>3, -2048, 8, -8, 0, 1}; */ in ctrl_set_oob()
10200 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10210 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16)(-8), 0); in ctrl_set_oob()
10221 /* DGN_LOCK = {10, -2048, 8, -8, 0, 1<<1}; */ in ctrl_set_oob()
10227 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10237 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16)(-8), 0); in ctrl_set_oob()
10248 /* FRQ_LOCK = {15,-2048, 8, -8, 0, 1<<2}; */ in ctrl_set_oob()
10254 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10264 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16)(-8), 0); in ctrl_set_oob()
10275 /* PHA_LOCK = {5000, -2048, 8, -8, 0, 1<<3}; */ in ctrl_set_oob()
10281 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10291 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16)(-8), 0); in ctrl_set_oob()
10302 /* TIM_LOCK = {300, -2048, 8, -8, 0, 1<<4}; */ in ctrl_set_oob()
10308 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10318 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16)(-8), 0); in ctrl_set_oob()
10329 /* EQU_LOCK = {20, -2048, 8, -8, 0, 1<<5}; */ in ctrl_set_oob()
10335 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10345 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16)(-4), 0); in ctrl_set_oob()
10356 /* PRE-Filter coefficients (PFI) */ in ctrl_set_oob()
10368 /* NYQUIST-Filter coefficients (NYQ) */ in ctrl_set_oob()
10410 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0); in ctrl_set_oob()
10416 ext_attr->oob_power_on = true; in ctrl_set_oob()
10461 return -EINVAL; in ctrl_set_channel()
10463 dev_addr = demod->my_i2c_dev_addr; in ctrl_set_channel()
10464 ext_attr = (struct drxj_data *) demod->my_ext_attr; in ctrl_set_channel()
10465 standard = ext_attr->standard; in ctrl_set_channel()
10478 return -EINVAL; in ctrl_set_channel()
10485 switch (channel->bandwidth) { in ctrl_set_channel()
10488 channel->bandwidth = DRX_BANDWIDTH_6MHZ; in ctrl_set_channel()
10493 return -EINVAL; in ctrl_set_channel()
10498 -check symbolrate and constellation in ctrl_set_channel()
10499 -derive bandwidth from symbolrate (input bandwidth is ignored) in ctrl_set_channel()
10517 if (channel->symbolrate < min_symbol_rate || in ctrl_set_channel()
10518 channel->symbolrate > max_symbol_rate) { in ctrl_set_channel()
10519 return -EINVAL; in ctrl_set_channel()
10522 switch (channel->constellation) { in ctrl_set_channel()
10528 bandwidth_temp = channel->symbolrate * bw_rolloff_factor; in ctrl_set_channel()
10535 channel->bandwidth = DRX_BANDWIDTH_6MHZ; in ctrl_set_channel()
10538 channel->bandwidth = DRX_BANDWIDTH_7MHZ; in ctrl_set_channel()
10540 channel->bandwidth = DRX_BANDWIDTH_8MHZ; in ctrl_set_channel()
10544 return -EINVAL; in ctrl_set_channel()
10549 -check constellation in ctrl_set_channel()
10552 switch (channel->constellation) { in ctrl_set_channel()
10558 return -EINVAL; in ctrl_set_channel()
10561 switch (channel->interleavemode) { in ctrl_set_channel()
10583 return -EINVAL; in ctrl_set_channel()
10587 if ((ext_attr->uio_sma_tx_mode) == DRX_UIO_MODE_FIRMWARE_SAW) { in ctrl_set_channel()
10591 switch (channel->bandwidth) { in ctrl_set_channel()
10603 return -EINVAL; in ctrl_set_channel()
10624 if (channel->mirror == DRX_MIRROR_AUTO) in ctrl_set_channel()
10625 ext_attr->mirror = DRX_MIRROR_NO; in ctrl_set_channel()
10627 ext_attr->mirror = channel->mirror; in ctrl_set_channel()
10652 return -EIO; in ctrl_set_channel()
10656 ext_attr->reset_pkt_err_acc = true; in ctrl_set_channel()
10674 * \retval -EINVAL sig_quality is NULL.
10675 * \retval -EIO Erroneous data, sig_quality contains invalid data.
10682 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in ctrl_sig_quality()
10683 struct drxj_data *ext_attr = demod->my_ext_attr; in ctrl_sig_quality()
10684 struct drx39xxj_state *state = dev_addr->user_data; in ctrl_sig_quality()
10685 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache; in ctrl_sig_quality()
10686 enum drx_standard standard = ext_attr->standard; in ctrl_sig_quality()
10694 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10696 p->strength.stat[0].scale = FE_SCALE_RELATIVE; in ctrl_sig_quality()
10697 p->strength.stat[0].uvalue = 65535UL * strength/ 100; in ctrl_sig_quality()
10710 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10711 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10712 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10713 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10714 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10715 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10716 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10721 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10723 p->block_error.stat[0].scale = FE_SCALE_COUNTER; in ctrl_sig_quality()
10724 p->block_error.stat[0].uvalue += err; in ctrl_sig_quality()
10725 p->block_count.stat[0].scale = FE_SCALE_COUNTER; in ctrl_sig_quality()
10726 p->block_count.stat[0].uvalue += pkt; in ctrl_sig_quality()
10729 /* PostViterbi is compute in steps of 10^(-6) */ in ctrl_sig_quality()
10732 pr_err("error %d getting pre-ber\n", rc); in ctrl_sig_quality()
10733 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10735 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; in ctrl_sig_quality()
10736 p->pre_bit_error.stat[0].uvalue += ber; in ctrl_sig_quality()
10737 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; in ctrl_sig_quality()
10738 p->pre_bit_count.stat[0].uvalue += cnt; in ctrl_sig_quality()
10743 pr_err("error %d getting post-ber\n", rc); in ctrl_sig_quality()
10744 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10746 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; in ctrl_sig_quality()
10747 p->post_bit_error.stat[0].uvalue += ber; in ctrl_sig_quality()
10748 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; in ctrl_sig_quality()
10749 p->post_bit_count.stat[0].uvalue += cnt; in ctrl_sig_quality()
10754 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in ctrl_sig_quality()
10756 p->cnr.stat[0].svalue = mer * 100; in ctrl_sig_quality()
10757 p->cnr.stat[0].scale = FE_SCALE_DECIBEL; in ctrl_sig_quality()
10773 return -EIO; in ctrl_sig_quality()
10809 return -EINVAL; in ctrl_lock_status()
10811 dev_addr = demod->my_i2c_dev_addr; in ctrl_lock_status()
10812 ext_attr = (struct drxj_data *) demod->my_ext_attr; in ctrl_lock_status()
10813 standard = ext_attr->standard; in ctrl_lock_status()
10834 return -EIO; in ctrl_lock_status()
10890 return -EINVAL; in ctrl_set_standard()
10892 ext_attr = (struct drxj_data *) demod->my_ext_attr; in ctrl_set_standard()
10893 prev_standard = ext_attr->standard; in ctrl_set_standard()
10922 return -EINVAL; in ctrl_set_standard()
10929 ext_attr->standard = *standard; in ctrl_set_standard()
10938 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); in ctrl_set_standard()
10954 ext_attr->standard = DRX_STANDARD_UNKNOWN; in ctrl_set_standard()
10955 return -EINVAL; in ctrl_set_standard()
10962 ext_attr->standard = DRX_STANDARD_UNKNOWN; in ctrl_set_standard()
10971 if (ext_attr->has_lna) { in drxj_reset_mode()
10974 ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B; in drxj_reset_mode()
10975 ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF; in drxj_reset_mode()
10976 ext_attr->qam_pga_cfg = 140 + (11 * 13); in drxj_reset_mode()
10978 ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB; in drxj_reset_mode()
10979 ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF; in drxj_reset_mode()
10980 ext_attr->vsb_pga_cfg = 140 + (11 * 13); in drxj_reset_mode()
10984 ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B; in drxj_reset_mode()
10985 ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; in drxj_reset_mode()
10986 ext_attr->qam_if_agc_cfg.min_output_level = 0; in drxj_reset_mode()
10987 ext_attr->qam_if_agc_cfg.max_output_level = 0x7FFF; in drxj_reset_mode()
10988 ext_attr->qam_if_agc_cfg.speed = 3; in drxj_reset_mode()
10989 ext_attr->qam_if_agc_cfg.top = 1297; in drxj_reset_mode()
10990 ext_attr->qam_pga_cfg = 140; in drxj_reset_mode()
10992 ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB; in drxj_reset_mode()
10993 ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; in drxj_reset_mode()
10994 ext_attr->vsb_if_agc_cfg.min_output_level = 0; in drxj_reset_mode()
10995 ext_attr->vsb_if_agc_cfg.max_output_level = 0x7FFF; in drxj_reset_mode()
10996 ext_attr->vsb_if_agc_cfg.speed = 3; in drxj_reset_mode()
10997 ext_attr->vsb_if_agc_cfg.top = 1024; in drxj_reset_mode()
10998 ext_attr->vsb_pga_cfg = 140; in drxj_reset_mode()
11003 ext_attr->qam_rf_agc_cfg.standard = DRX_STANDARD_ITU_B; in drxj_reset_mode()
11004 ext_attr->qam_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; in drxj_reset_mode()
11005 ext_attr->qam_rf_agc_cfg.min_output_level = 0; in drxj_reset_mode()
11006 ext_attr->qam_rf_agc_cfg.max_output_level = 0x7FFF; in drxj_reset_mode()
11007 ext_attr->qam_rf_agc_cfg.speed = 3; in drxj_reset_mode()
11008 ext_attr->qam_rf_agc_cfg.top = 9500; in drxj_reset_mode()
11009 ext_attr->qam_rf_agc_cfg.cut_off_current = 4000; in drxj_reset_mode()
11010 ext_attr->qam_pre_saw_cfg.standard = DRX_STANDARD_ITU_B; in drxj_reset_mode()
11011 ext_attr->qam_pre_saw_cfg.reference = 0x07; in drxj_reset_mode()
11012 ext_attr->qam_pre_saw_cfg.use_pre_saw = true; in drxj_reset_mode()
11015 ext_attr->vsb_rf_agc_cfg.standard = DRX_STANDARD_8VSB; in drxj_reset_mode()
11016 ext_attr->vsb_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO; in drxj_reset_mode()
11017 ext_attr->vsb_rf_agc_cfg.min_output_level = 0; in drxj_reset_mode()
11018 ext_attr->vsb_rf_agc_cfg.max_output_level = 0x7FFF; in drxj_reset_mode()
11019 ext_attr->vsb_rf_agc_cfg.speed = 3; in drxj_reset_mode()
11020 ext_attr->vsb_rf_agc_cfg.top = 9500; in drxj_reset_mode()
11021 ext_attr->vsb_rf_agc_cfg.cut_off_current = 4000; in drxj_reset_mode()
11022 ext_attr->vsb_pre_saw_cfg.standard = DRX_STANDARD_8VSB; in drxj_reset_mode()
11023 ext_attr->vsb_pre_saw_cfg.reference = 0x07; in drxj_reset_mode()
11024 ext_attr->vsb_pre_saw_cfg.use_pre_saw = true; in drxj_reset_mode()
11034 * \retval -EIO I2C error or other failure
11035 * \retval -EINVAL Invalid mode argument.
11048 common_attr = (struct drx_common_attr *) demod->my_common_attr; in ctrl_power_mode()
11049 ext_attr = (struct drxj_data *) demod->my_ext_attr; in ctrl_power_mode()
11050 dev_addr = demod->my_i2c_dev_addr; in ctrl_power_mode()
11054 return -EINVAL; in ctrl_power_mode()
11057 if (common_attr->current_power_mode == *mode) in ctrl_power_mode()
11076 return -EINVAL; in ctrl_power_mode()
11081 if ((common_attr->current_power_mode != DRX_POWER_UP)) { in ctrl_power_mode()
11097 /* Set pins with possible pull-ups connected to them in input mode */ in ctrl_power_mode()
11106 switch (ext_attr->standard) { in ctrl_power_mode()
11130 rc = power_down_atv(demod, ext_attr->standard, true); in ctrl_power_mode()
11141 return -EIO; in ctrl_power_mode()
11143 ext_attr->standard = DRX_STANDARD_UNKNOWN; in ctrl_power_mode()
11166 ext_attr->hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; in ctrl_power_mode()
11175 common_attr->current_power_mode = *mode; in ctrl_power_mode()
11188 * \brief Set Pre-saw reference.
11204 dev_addr = demod->my_i2c_dev_addr; in ctrl_set_cfg_pre_saw()
11205 ext_attr = (struct drxj_data *) demod->my_ext_attr; in ctrl_set_cfg_pre_saw()
11208 if ((pre_saw == NULL) || (pre_saw->reference > IQM_AF_PDREF__M) in ctrl_set_cfg_pre_saw()
11210 return -EINVAL; in ctrl_set_cfg_pre_saw()
11214 if ((ext_attr->standard == pre_saw->standard) || in ctrl_set_cfg_pre_saw()
11215 (DRXJ_ISQAMSTD(ext_attr->standard) && in ctrl_set_cfg_pre_saw()
11216 DRXJ_ISQAMSTD(pre_saw->standard)) || in ctrl_set_cfg_pre_saw()
11217 (DRXJ_ISATVSTD(ext_attr->standard) && in ctrl_set_cfg_pre_saw()
11218 DRXJ_ISATVSTD(pre_saw->standard))) { in ctrl_set_cfg_pre_saw()
11219 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, pre_saw->reference, 0); in ctrl_set_cfg_pre_saw()
11226 /* Store pre-saw settings */ in ctrl_set_cfg_pre_saw()
11227 switch (pre_saw->standard) { in ctrl_set_cfg_pre_saw()
11229 ext_attr->vsb_pre_saw_cfg = *pre_saw; in ctrl_set_cfg_pre_saw()
11235 ext_attr->qam_pre_saw_cfg = *pre_saw; in ctrl_set_cfg_pre_saw()
11239 return -EINVAL; in ctrl_set_cfg_pre_saw()
11270 return -EINVAL; in ctrl_set_cfg_afe_gain()
11272 dev_addr = demod->my_i2c_dev_addr; in ctrl_set_cfg_afe_gain()
11273 ext_attr = (struct drxj_data *) demod->my_ext_attr; in ctrl_set_cfg_afe_gain()
11275 switch (afe_gain->standard) { in ctrl_set_cfg_afe_gain()
11285 return -EINVAL; in ctrl_set_cfg_afe_gain()
11291 if (afe_gain->gain >= 329) in ctrl_set_cfg_afe_gain()
11293 else if (afe_gain->gain <= 147) in ctrl_set_cfg_afe_gain()
11296 gain = (afe_gain->gain - 140 + 6) / 13; in ctrl_set_cfg_afe_gain()
11299 if (ext_attr->standard == afe_gain->standard) { in ctrl_set_cfg_afe_gain()
11308 switch (afe_gain->standard) { in ctrl_set_cfg_afe_gain()
11310 ext_attr->vsb_pga_cfg = gain * 13 + 140; in ctrl_set_cfg_afe_gain()
11316 ext_attr->qam_pga_cfg = gain * 13 + 140; in ctrl_set_cfg_afe_gain()
11320 return -EIO; in ctrl_set_cfg_afe_gain()
11362 (demod->my_common_attr == NULL) || in drxj_open()
11363 (demod->my_ext_attr == NULL) || in drxj_open()
11364 (demod->my_i2c_dev_addr == NULL) || in drxj_open()
11365 (demod->my_common_attr->is_opened)) { in drxj_open()
11366 return -EINVAL; in drxj_open()
11370 if (demod->my_ext_attr == NULL) in drxj_open()
11371 return -EINVAL; in drxj_open()
11373 dev_addr = demod->my_i2c_dev_addr; in drxj_open()
11374 ext_attr = (struct drxj_data *) demod->my_ext_attr; in drxj_open()
11375 common_attr = (struct drx_common_attr *) demod->my_common_attr; in drxj_open()
11383 rc = -EINVAL; in drxj_open()
11396 * Soft reset of sys- and osc-clockdomain in drxj_open()
11400 * Btw, this is coherent with DRX-K, where we send reset codes in drxj_open()
11401 * for modulation (OFTM, in DRX-k), SYS and OSC clock domains. in drxj_open()
11441 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output)); in drxj_open()
11463 if (common_attr->microcode_file != NULL) { in drxj_open()
11466 common_attr->is_opened = true; in drxj_open()
11467 ucode_info.mc_file = common_attr->microcode_file; in drxj_open()
11469 if (DRX_ISPOWERDOWNMODE(demod->my_common_attr->current_power_mode)) { in drxj_open()
11471 return -EINVAL; in drxj_open()
11479 if (common_attr->verify_microcode == true) { in drxj_open()
11487 common_attr->is_opened = false; in drxj_open()
11498 common_attr->scan_demod_lock_timeout = DRXJ_SCAN_TIMEOUT; in drxj_open()
11499 common_attr->scan_desired_lock = DRX_LOCKED; in drxj_open()
11502 ext_attr->standard = DRX_STANDARD_UNKNOWN; in drxj_open()
11512 via I2C from SCU RAM in drxj_open()
11547 ext_attr->aud_data = drxj_default_aud_data_g; in drxj_open()
11549 demod->my_common_attr->is_opened = true; in drxj_open()
11553 common_attr->is_opened = false; in drxj_open()
11566 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in drxj_close()
11570 if ((demod->my_common_attr == NULL) || in drxj_close()
11571 (demod->my_ext_attr == NULL) || in drxj_close()
11572 (demod->my_i2c_dev_addr == NULL) || in drxj_close()
11573 (!demod->my_common_attr->is_opened)) { in drxj_close()
11574 return -EINVAL; in drxj_close()
11610 * drx_u_code_compute_crc - Compute CRC of block of microcode data.
11638 * drx_check_firmware - checks if the loaded firmware is valid
11720 return -EINVAL; in drx_check_firmware()
11724 * drx_ctrl_u_code - Handle microcode upload or verify.
11731 * - In case of UCODE_UPLOAD: code is successfully uploaded.
11732 * - In case of UCODE_VERIFY: image on device is equal to
11734 * -EIO:
11735 * - In case of UCODE_UPLOAD: I2C error.
11736 * - In case of UCODE_VERIFY: I2C error or image on device
11738 * -EINVAL:
11739 * - Invalid arguments.
11740 * - Provided image is corrupt
11746 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr; in drx_ctrl_u_code()
11757 if (!mc_info || !mc_info->mc_file) in drx_ctrl_u_code()
11758 return -EINVAL; in drx_ctrl_u_code()
11760 mc_file = mc_info->mc_file; in drx_ctrl_u_code()
11762 if (!demod->firmware) { in drx_ctrl_u_code()
11765 rc = request_firmware(&fw, mc_file, demod->i2c->dev.parent); in drx_ctrl_u_code()
11770 demod->firmware = fw; in drx_ctrl_u_code()
11772 if (demod->firmware->size < 2 * sizeof(u16)) { in drx_ctrl_u_code()
11773 rc = -EINVAL; in drx_ctrl_u_code()
11779 mc_file, demod->firmware->size); in drx_ctrl_u_code()
11782 mc_data_init = demod->firmware->data; in drx_ctrl_u_code()
11783 size = demod->firmware->size; in drx_ctrl_u_code()
11793 rc = -EINVAL; in drx_ctrl_u_code()
11823 (mc_data - mc_data_init), block_hdr.addr, in drx_ctrl_u_code()
11827 - data larger than 64Kb in drx_ctrl_u_code()
11828 - if CRC enabled check CRC in drx_ctrl_u_code()
11835 rc = -EINVAL; in drx_ctrl_u_code()
11852 rc = -EIO; in drx_ctrl_u_code()
11854 mc_data - mc_data_init); in drx_ctrl_u_code()
11878 mc_data - mc_data_init); in drx_ctrl_u_code()
11879 return -EIO; in drx_ctrl_u_code()
11887 mc_data - mc_data_init); in drx_ctrl_u_code()
11888 return -EIO; in drx_ctrl_u_code()
11893 bytes_left -=((u32) bytes_to_comp); in drx_ctrl_u_code()
11898 return -EINVAL; in drx_ctrl_u_code()
11908 release_firmware(demod->firmware); in drx_ctrl_u_code()
11909 demod->firmware = NULL; in drx_ctrl_u_code()
11923 /* Configure user-I/O #3: enable read/write */ in drxj_set_lna_state()
11949 struct drx39xxj_state *state = fe->demodulator_priv; in drx39xxj_set_powerstate()
11950 struct drx_demod_instance *demod = state->demod; in drx39xxj_set_powerstate()
11970 struct drx39xxj_state *state = fe->demodulator_priv; in drx39xxj_read_status()
11971 struct drx_demod_instance *demod = state->demod; in drx39xxj_read_status()
12018 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in drx39xxj_read_ber()
12020 if (p->pre_bit_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { in drx39xxj_read_ber()
12025 if (!p->pre_bit_count.stat[0].uvalue) { in drx39xxj_read_ber()
12026 if (!p->pre_bit_error.stat[0].uvalue) in drx39xxj_read_ber()
12031 *ber = frac_times1e6(p->pre_bit_error.stat[0].uvalue, in drx39xxj_read_ber()
12032 p->pre_bit_count.stat[0].uvalue); in drx39xxj_read_ber()
12040 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in drx39xxj_read_signal_strength()
12042 if (p->strength.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { in drx39xxj_read_signal_strength()
12047 *strength = p->strength.stat[0].uvalue; in drx39xxj_read_signal_strength()
12053 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in drx39xxj_read_snr()
12056 if (p->cnr.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { in drx39xxj_read_snr()
12061 tmp64 = p->cnr.stat[0].svalue; in drx39xxj_read_snr()
12069 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in drx39xxj_read_ucblocks()
12071 if (p->block_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { in drx39xxj_read_ucblocks()
12076 *ucb = p->block_error.stat[0].uvalue; in drx39xxj_read_ucblocks()
12085 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in drx39xxj_set_frontend()
12086 struct drx39xxj_state *state = fe->demodulator_priv; in drx39xxj_set_frontend()
12087 struct drx_demod_instance *demod = state->demod; in drx39xxj_set_frontend()
12113 if (fe->ops.tuner_ops.set_params) { in drx39xxj_set_frontend()
12116 if (fe->ops.i2c_gate_ctrl) in drx39xxj_set_frontend()
12117 fe->ops.i2c_gate_ctrl(fe, 1); in drx39xxj_set_frontend()
12120 fe->ops.tuner_ops.set_params(fe); in drx39xxj_set_frontend()
12123 if (fe->ops.tuner_ops.get_if_frequency) { in drx39xxj_set_frontend()
12124 fe->ops.tuner_ops.get_if_frequency(fe, &int_freq); in drx39xxj_set_frontend()
12125 demod->my_common_attr->intermediate_freq = int_freq / 1000; in drx39xxj_set_frontend()
12128 if (fe->ops.i2c_gate_ctrl) in drx39xxj_set_frontend()
12129 fe->ops.i2c_gate_ctrl(fe, 0); in drx39xxj_set_frontend()
12132 switch (p->delivery_system) { in drx39xxj_set_frontend()
12139 switch (p->modulation) { in drx39xxj_set_frontend()
12152 return -EINVAL; in drx39xxj_set_frontend()
12159 return -EINVAL; in drx39xxj_set_frontend()
12164 channel.frequency = p->frequency / 1000; in drx39xxj_set_frontend()
12172 return -EINVAL; in drx39xxj_set_frontend()
12178 p->strength.stat[0].scale = FE_SCALE_RELATIVE; in drx39xxj_set_frontend()
12185 /* power-down the demodulator */ in drx39xxj_sleep()
12191 struct drx39xxj_state *state = fe->demodulator_priv; in drx39xxj_i2c_gate_ctrl()
12192 struct drx_demod_instance *demod = state->demod; in drx39xxj_i2c_gate_ctrl()
12197 pr_debug("i2c gate call: enable=%d state=%d\n", enable, in drx39xxj_i2c_gate_ctrl()
12198 state->i2c_gate_open); in drx39xxj_i2c_gate_ctrl()
12206 if (state->i2c_gate_open == enable) { in drx39xxj_i2c_gate_ctrl()
12213 pr_err("drx39xxj: could not open i2c gate [%d]\n", in drx39xxj_i2c_gate_ctrl()
12217 state->i2c_gate_open = enable; in drx39xxj_i2c_gate_ctrl()
12224 struct drx39xxj_state *state = fe->demodulator_priv; in drx39xxj_init()
12225 struct drx_demod_instance *demod = state->demod; in drx39xxj_init()
12228 if (fe->exit == DVB_FE_DEVICE_RESUME) { in drx39xxj_init()
12230 demod->my_common_attr->is_opened = false; in drx39xxj_init()
12242 struct dtv_frontend_properties *c = &fe->dtv_property_cache; in drx39xxj_set_lna()
12243 struct drx39xxj_state *state = fe->demodulator_priv; in drx39xxj_set_lna()
12244 struct drx_demod_instance *demod = state->demod; in drx39xxj_set_lna()
12245 struct drxj_data *ext_attr = demod->my_ext_attr; in drx39xxj_set_lna()
12247 if (c->lna) { in drx39xxj_set_lna()
12248 if (!ext_attr->has_lna) { in drx39xxj_set_lna()
12250 return -EINVAL; in drx39xxj_set_lna()
12255 return drxj_set_lna_state(demod, c->lna); in drx39xxj_set_lna()
12261 tune->min_delay_ms = 1000; in drx39xxj_get_tune_settings()
12267 struct drx39xxj_state *state = fe->demodulator_priv; in drx39xxj_release()
12268 struct drx_demod_instance *demod = state->demod; in drx39xxj_release()
12271 if (fe->exit != DVB_FE_DEVICE_REMOVED) in drx39xxj_release()
12274 kfree(demod->my_ext_attr); in drx39xxj_release()
12275 kfree(demod->my_common_attr); in drx39xxj_release()
12276 kfree(demod->my_i2c_dev_addr); in drx39xxj_release()
12277 release_firmware(demod->firmware); in drx39xxj_release()
12284 struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) in drx39xxj_attach() argument
12320 state->i2c = i2c; in drx39xxj_attach()
12321 state->demod = demod; in drx39xxj_attach()
12324 demod->my_i2c_dev_addr = demod_addr; in drx39xxj_attach()
12325 demod->my_common_attr = demod_comm_attr; in drx39xxj_attach()
12326 demod->my_i2c_dev_addr->user_data = state; in drx39xxj_attach()
12327 demod->my_common_attr->microcode_file = DRX39XX_MAIN_FIRMWARE; in drx39xxj_attach()
12328 demod->my_common_attr->verify_microcode = true; in drx39xxj_attach()
12329 demod->my_common_attr->intermediate_freq = 5000; in drx39xxj_attach()
12330 demod->my_common_attr->current_power_mode = DRX_POWER_DOWN; in drx39xxj_attach()
12331 demod->my_ext_attr = demod_ext_attr; in drx39xxj_attach()
12332 ((struct drxj_data *)demod_ext_attr)->uio_sma_tx_mode = DRX_UIO_MODE_READWRITE; in drx39xxj_attach()
12333 demod->i2c = i2c; in drx39xxj_attach()
12342 memcpy(&state->frontend.ops, &drx39xxj_ops, in drx39xxj_attach()
12345 state->frontend.demodulator_priv = state; in drx39xxj_attach()
12347 /* Initialize stats - needed for DVBv5 stats to work */ in drx39xxj_attach()
12348 p = &state->frontend.dtv_property_cache; in drx39xxj_attach()
12349 p->strength.len = 1; in drx39xxj_attach()
12350 p->pre_bit_count.len = 1; in drx39xxj_attach()
12351 p->pre_bit_error.len = 1; in drx39xxj_attach()
12352 p->post_bit_count.len = 1; in drx39xxj_attach()
12353 p->post_bit_error.len = 1; in drx39xxj_attach()
12354 p->block_count.len = 1; in drx39xxj_attach()
12355 p->block_error.len = 1; in drx39xxj_attach()
12356 p->cnr.len = 1; in drx39xxj_attach()
12358 p->strength.stat[0].scale = FE_SCALE_RELATIVE; in drx39xxj_attach()
12359 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drx39xxj_attach()
12360 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drx39xxj_attach()
12361 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drx39xxj_attach()
12362 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drx39xxj_attach()
12363 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drx39xxj_attach()
12364 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drx39xxj_attach()
12365 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drx39xxj_attach()
12367 return &state->frontend; in drx39xxj_attach()