Lines Matching +full:adc +full:- +full:diff +full:- +full:channels
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Linux-DVB Driver for DiBcom's DiB8000 chip (ISDB-T).
22 #define LAYER_ALL -1
149 {.addr = i2c->addr >> 1, .flags = 0, .len = 2}, in dib8000_i2c_read16()
150 {.addr = i2c->addr >> 1, .flags = I2C_M_RD, .len = 2}, in dib8000_i2c_read16()
153 if (mutex_lock_interruptible(i2c->i2c_buffer_lock) < 0) { in dib8000_i2c_read16()
158 msg[0].buf = i2c->i2c_write_buffer; in dib8000_i2c_read16()
161 msg[1].buf = i2c->i2c_read_buffer; in dib8000_i2c_read16()
163 if (i2c_transfer(i2c->adap, msg, 2) != 2) in dib8000_i2c_read16()
167 mutex_unlock(i2c->i2c_buffer_lock); in dib8000_i2c_read16()
175 state->i2c_write_buffer[0] = reg >> 8; in __dib8000_read_word()
176 state->i2c_write_buffer[1] = reg & 0xff; in __dib8000_read_word()
178 memset(state->msg, 0, 2 * sizeof(struct i2c_msg)); in __dib8000_read_word()
179 state->msg[0].addr = state->i2c.addr >> 1; in __dib8000_read_word()
180 state->msg[0].flags = 0; in __dib8000_read_word()
181 state->msg[0].buf = state->i2c_write_buffer; in __dib8000_read_word()
182 state->msg[0].len = 2; in __dib8000_read_word()
183 state->msg[1].addr = state->i2c.addr >> 1; in __dib8000_read_word()
184 state->msg[1].flags = I2C_M_RD; in __dib8000_read_word()
185 state->msg[1].buf = state->i2c_read_buffer; in __dib8000_read_word()
186 state->msg[1].len = 2; in __dib8000_read_word()
188 if (i2c_transfer(state->i2c.adap, state->msg, 2) != 2) in __dib8000_read_word()
191 ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1]; in __dib8000_read_word()
200 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib8000_read_word()
207 mutex_unlock(&state->i2c_buffer_lock); in dib8000_read_word()
216 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib8000_read32()
224 mutex_unlock(&state->i2c_buffer_lock); in dib8000_read32()
231 struct i2c_msg msg = {.addr = i2c->addr >> 1, .flags = 0, .len = 4}; in dib8000_i2c_write16()
234 if (mutex_lock_interruptible(i2c->i2c_buffer_lock) < 0) { in dib8000_i2c_write16()
236 return -EINVAL; in dib8000_i2c_write16()
239 msg.buf = i2c->i2c_write_buffer; in dib8000_i2c_write16()
245 ret = i2c_transfer(i2c->adap, &msg, 1) != 1 ? -EREMOTEIO : 0; in dib8000_i2c_write16()
246 mutex_unlock(i2c->i2c_buffer_lock); in dib8000_i2c_write16()
255 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib8000_write_word()
257 return -EINVAL; in dib8000_write_word()
260 state->i2c_write_buffer[0] = (reg >> 8) & 0xff; in dib8000_write_word()
261 state->i2c_write_buffer[1] = reg & 0xff; in dib8000_write_word()
262 state->i2c_write_buffer[2] = (val >> 8) & 0xff; in dib8000_write_word()
263 state->i2c_write_buffer[3] = val & 0xff; in dib8000_write_word()
265 memset(&state->msg[0], 0, sizeof(struct i2c_msg)); in dib8000_write_word()
266 state->msg[0].addr = state->i2c.addr >> 1; in dib8000_write_word()
267 state->msg[0].flags = 0; in dib8000_write_word()
268 state->msg[0].buf = state->i2c_write_buffer; in dib8000_write_word()
269 state->msg[0].len = 4; in dib8000_write_word()
271 ret = (i2c_transfer(state->i2c.adap, state->msg, 1) != 1 ? in dib8000_write_word()
272 -EREMOTEIO : 0); in dib8000_write_word()
273 mutex_unlock(&state->i2c_buffer_lock); in dib8000_write_word()
288 …(832 << 5) | 0x10, (912 << 5) | 0x05, (900 << 5) | 0x12, (832 << 5) | 0x10, (-931 << 5) | 0x0f, (9…
289 (-931 << 5) | 0x0f
298 …(699 << 5) | 0x14, (607 << 5) | 0x04, (944 << 5) | 0x13, (699 << 5) | 0x14, (-720 << 5) | 0x0d, (6…
299 (-720 << 5) | 0x0d
303 …(664 << 5) | 0x0c, (925 << 5) | 0x03, (937 << 5) | 0x10, (664 << 5) | 0x0c, (-610 << 5) | 0x0a, (6…
304 (-610 << 5) | 0x0a
308 …(-955 << 5) | 0x0e, (687 << 5) | 0x04, (818 << 5) | 0x10, (-955 << 5) | 0x0e, (-922 << 5) | 0x0d, …
309 (-922 << 5) | 0x0d
313 …(638 << 5) | 0x0d, (683 << 5) | 0x02, (638 << 5) | 0x0d, (638 << 5) | 0x0d, (-655 << 5) | 0x0a, (5…
314 (-655 << 5) | 0x0a
318 …(-707 << 5) | 0x14, (910 << 5) | 0x06, (889 << 5) | 0x16, (-707 << 5) | 0x14, (-958 << 5) | 0x13, …
319 (-958 << 5) | 0x13
323 …(-723 << 5) | 0x13, (910 << 5) | 0x05, (777 << 5) | 0x14, (-723 << 5) | 0x13, (-568 << 5) | 0x0f, …
324 (-568 << 5) | 0x0f
328 …(-940 << 5) | 0x15, (607 << 5) | 0x05, (915 << 5) | 0x16, (-940 << 5) | 0x15, (-848 << 5) | 0x13, …
329 (-848 << 5) | 0x13
333 …(612 << 5) | 0x12, (910 << 5) | 0x04, (864 << 5) | 0x14, (612 << 5) | 0x12, (-869 << 5) | 0x13, (6…
334 (-869 << 5) | 0x13
338 …(-835 << 5) | 0x12, (684 << 5) | 0x05, (735 << 5) | 0x14, (-835 << 5) | 0x12, (-598 << 5) | 0x10, …
339 (-598 << 5) | 0x10
353 …(-924 << 5) | 0x17, (910 << 5) | 0x06, (774 << 5) | 0x17, (-924 << 5) | 0x17, (-877 << 5) | 0x15, …
354 (-877 << 5) | 0x15
358 …(-921 << 5) | 0x19, (607 << 5) | 0x06, (881 << 5) | 0x19, (-921 << 5) | 0x19, (-921 << 5) | 0x14, …
359 (-921 << 5) | 0x14
376 396, 305, 105, -51, -77, -12, 41, 31, -11, -30, -11, 14, 15, -2, -13, -7, 5, 8, 1, -6, -7, -3, 0, 1
382 switch (state->fe[0]->dtv_property_cache.transmission_mode) { in fft_to_mode()
407 struct dib8000_state *state = fe->demodulator_priv; in dib8000_set_output_mode()
410 state->output_mode = mode; in dib8000_set_output_mode()
415 dprintk("-I- Setting output mode for demod %p to %d\n", in dib8000_set_output_mode()
416 &state->fe[0], mode); in dib8000_set_output_mode()
429 if (state->cfg.hostbus_diversity) { in dib8000_set_output_mode()
451 &state->fe[0]); in dib8000_set_output_mode()
452 return -EINVAL; in dib8000_set_output_mode()
455 if (state->cfg.output_mpeg2_in_188_bytes) in dib8000_set_output_mode()
468 struct dib8000_state *state = fe->demodulator_priv; in dib8000_set_diversity_in()
472 if (!state->differential_constellation) { in dib8000_set_diversity_in()
479 state->diversity_onoff = onoff; in dib8000_set_diversity_in()
482 case 0: /* only use the internal way - not the diversity input */ in dib8000_set_diversity_in()
496 if (state->revision == 0x8002) { in dib8000_set_diversity_in()
512 if (state->revision != 0x8090) in dib8000_set_power_mode()
525 if (state->revision != 0x8090) in dib8000_set_power_mode()
531 if (state->revision != 0x8090) in dib8000_set_power_mode()
554 if (state->revision != 0x8090) { in dib8000_set_adc_state()
580 if (state->revision == 0x8090) { in dib8000_set_adc_state()
619 struct dib8000_state *state = fe->demodulator_priv; in dib8000_set_bandwidth()
625 if (state->timf == 0) { in dib8000_set_bandwidth()
627 timf = state->timf_default; in dib8000_set_bandwidth()
630 timf = state->timf; in dib8000_set_bandwidth()
643 if (state->revision == 0x8090) { in dib8000_sad_calib()
665 struct dib8000_state *state = fe->demodulator_priv; in dib8000_set_wbd_ref()
668 state->wbd_ref = value; in dib8000_set_wbd_ref()
674 dprintk("ifreq: %d %x, inversion: %d\n", bw->ifreq, bw->ifreq, bw->ifreq >> 25); in dib8000_reset_pll_common()
675 if (state->revision != 0x8090) { in dib8000_reset_pll_common()
677 (u16) (((bw->internal * 1000) >> 16) & 0xffff)); in dib8000_reset_pll_common()
679 (u16) ((bw->internal * 1000) & 0xffff)); in dib8000_reset_pll_common()
681 dib8000_write_word(state, 23, (u16) (((bw->internal / 2 * 1000) >> 16) & 0xffff)); in dib8000_reset_pll_common()
683 (u16) ((bw->internal / 2 * 1000) & 0xffff)); in dib8000_reset_pll_common()
685 dib8000_write_word(state, 27, (u16) ((bw->ifreq >> 16) & 0x01ff)); in dib8000_reset_pll_common()
686 dib8000_write_word(state, 28, (u16) (bw->ifreq & 0xffff)); in dib8000_reset_pll_common()
687 dib8000_write_word(state, 26, (u16) ((bw->ifreq >> 25) & 0x0003)); in dib8000_reset_pll_common()
689 if (state->revision != 0x8090) in dib8000_reset_pll_common()
690 dib8000_write_word(state, 922, bw->sad_cfg); in dib8000_reset_pll_common()
695 const struct dibx000_bandwidth_config *pll = state->cfg.pll; in dib8000_reset_pll()
698 if (state->revision != 0x8090) { in dib8000_reset_pll()
700 (pll->pll_prediv << 8) | (pll->pll_ratio << 0)); in dib8000_reset_pll()
702 clk_cfg1 = (1 << 10) | (0 << 9) | (pll->IO_CLK_en_core << 8) | in dib8000_reset_pll()
703 (pll->bypclk_div << 5) | (pll->enable_refdiv << 4) | in dib8000_reset_pll()
704 (1 << 3) | (pll->pll_range << 1) | in dib8000_reset_pll()
705 (pll->pll_reset << 0); in dib8000_reset_pll()
708 clk_cfg1 = (clk_cfg1 & 0xfff7) | (pll->pll_bypass << 3); in dib8000_reset_pll()
714 if (state->cfg.pll->ADClkSrc == 0) in dib8000_reset_pll()
717 (pll->modulo << 8) | in dib8000_reset_pll()
718 (pll->ADClkSrc << 7) | (0 << 1)); in dib8000_reset_pll()
719 else if (state->cfg.refclksel != 0) in dib8000_reset_pll()
721 ((state->cfg.refclksel & 0x3) << 10) | in dib8000_reset_pll()
722 (pll->modulo << 8) | in dib8000_reset_pll()
723 (pll->ADClkSrc << 7) | (0 << 1)); in dib8000_reset_pll()
726 (3 << 10) | (pll->modulo << 8) | in dib8000_reset_pll()
727 (pll->ADClkSrc << 7) | (0 << 1)); in dib8000_reset_pll()
729 dib8000_write_word(state, 1856, (!pll->pll_reset<<13) | in dib8000_reset_pll()
730 (pll->pll_range<<12) | (pll->pll_ratio<<6) | in dib8000_reset_pll()
731 (pll->pll_prediv)); in dib8000_reset_pll()
734 dib8000_write_word(state, 1857, reg|(!pll->pll_bypass<<15)); in dib8000_reset_pll()
739 dib8000_write_word(state, 904, (pll->modulo << 8)); in dib8000_reset_pll()
748 struct dib8000_state *state = fe->demodulator_priv; in dib8000_update_pll()
750 u8 loopdiv, prediv, oldprediv = state->cfg.pll->pll_prediv ; in dib8000_update_pll()
757 if ((pll == NULL) || (pll->pll_prediv == prediv && in dib8000_update_pll()
758 pll->pll_ratio == loopdiv)) in dib8000_update_pll()
759 return -EINVAL; in dib8000_update_pll()
761 …d = %d new = %d ; loopdiv : old = %d new = %d)\n", prediv, pll->pll_prediv, loopdiv, pll->pll_rat… in dib8000_update_pll()
762 if (state->revision == 0x8090) { in dib8000_update_pll()
769 ((pll->pll_ratio & 0x3f) << 6) | in dib8000_update_pll()
770 (pll->pll_prediv & 0x3f)); in dib8000_update_pll()
776 internal = 1000 * (xtal/pll->pll_prediv) * pll->pll_ratio; in dib8000_update_pll()
794 if (bw != state->current_demod_bw) { in dib8000_update_pll()
796 …: Bandwidth Change %d MHz -> %d MHz (prediv: %d->%d)\n", state->current_demod_bw / 1000, bw / 1000… in dib8000_update_pll()
798 if (state->cfg.pll->pll_prediv != oldprediv) { in dib8000_update_pll()
802 … MHz Bandwidth (prediv: %d, ratio: %d)\n", bw/1000, state->cfg.pll->pll_prediv, state->cfg.pll->pl… in dib8000_update_pll()
807 ratio = state->cfg.pll->pll_ratio; in dib8000_update_pll()
809 state->current_demod_bw = bw; in dib8000_update_pll()
814 dprintk("PLL: Update ratio (prediv: %d, ratio: %d)\n", state->cfg.pll->pll_prediv, ratio); in dib8000_update_pll()
815 …dib8000_write_word(state, 901, (state->cfg.pll->pll_prediv << 8) | (ratio << 0)); /* only the PLL … in dib8000_update_pll()
825 dib8000_write_word(st, 1029, st->cfg.gpio_dir); in dib8000_reset_gpio()
826 dib8000_write_word(st, 1030, st->cfg.gpio_val); in dib8000_reset_gpio()
830 dib8000_write_word(st, 1032, st->cfg.gpio_pwm_pos); in dib8000_reset_gpio()
832 dib8000_write_word(st, 1037, st->cfg.pwm_freq_div); in dib8000_reset_gpio()
838 st->cfg.gpio_dir = dib8000_read_word(st, 1029); in dib8000_cfg_gpio()
839 st->cfg.gpio_dir &= ~(1 << num); /* reset the direction bit */ in dib8000_cfg_gpio()
840 st->cfg.gpio_dir |= (dir & 0x1) << num; /* set the new direction */ in dib8000_cfg_gpio()
841 dib8000_write_word(st, 1029, st->cfg.gpio_dir); in dib8000_cfg_gpio()
843 st->cfg.gpio_val = dib8000_read_word(st, 1030); in dib8000_cfg_gpio()
844 st->cfg.gpio_val &= ~(1 << num); /* reset the direction bit */ in dib8000_cfg_gpio()
845 st->cfg.gpio_val |= (val & 0x01) << num; /* set the new value */ in dib8000_cfg_gpio()
846 dib8000_write_word(st, 1030, st->cfg.gpio_val); in dib8000_cfg_gpio()
848 dprintk("gpio dir: %x: gpio val: %x\n", st->cfg.gpio_dir, st->cfg.gpio_val); in dib8000_cfg_gpio()
855 struct dib8000_state *state = fe->demodulator_priv; in dib8000_set_gpio()
860 /* auto search configuration - lock0 by default waiting
884 11, 80, /* set ADC level to -16 */
885 (1 << 13) - 825 - 117,
886 (1 << 13) - 837 - 117,
887 (1 << 13) - 811 - 117,
888 (1 << 13) - 766 - 117,
889 (1 << 13) - 737 - 117,
890 (1 << 13) - 693 - 117,
891 (1 << 13) - 648 - 117,
892 (1 << 13) - 619 - 117,
893 (1 << 13) - 575 - 117,
894 (1 << 13) - 531 - 117,
895 (1 << 13) - 501 - 117,
997 struct dib8000_state *state = fe->demodulator_priv; in dib8000_reset_stats()
998 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_reset_stats()
1001 memset(&c->strength, 0, sizeof(c->strength)); in dib8000_reset_stats()
1002 memset(&c->cnr, 0, sizeof(c->cnr)); in dib8000_reset_stats()
1003 memset(&c->post_bit_error, 0, sizeof(c->post_bit_error)); in dib8000_reset_stats()
1004 memset(&c->post_bit_count, 0, sizeof(c->post_bit_count)); in dib8000_reset_stats()
1005 memset(&c->block_error, 0, sizeof(c->block_error)); in dib8000_reset_stats()
1007 c->strength.len = 1; in dib8000_reset_stats()
1008 c->cnr.len = 1; in dib8000_reset_stats()
1009 c->block_error.len = 1; in dib8000_reset_stats()
1010 c->block_count.len = 1; in dib8000_reset_stats()
1011 c->post_bit_error.len = 1; in dib8000_reset_stats()
1012 c->post_bit_count.len = 1; in dib8000_reset_stats()
1014 c->strength.stat[0].scale = FE_SCALE_DECIBEL; in dib8000_reset_stats()
1015 c->strength.stat[0].uvalue = 0; in dib8000_reset_stats()
1017 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in dib8000_reset_stats()
1018 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in dib8000_reset_stats()
1019 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in dib8000_reset_stats()
1020 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in dib8000_reset_stats()
1021 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in dib8000_reset_stats()
1025 state->init_ucb = -ucb; in dib8000_reset_stats()
1026 state->ber_jiffies_stats = 0; in dib8000_reset_stats()
1027 state->per_jiffies_stats = 0; in dib8000_reset_stats()
1028 memset(&state->ber_jiffies_stats_layer, 0, in dib8000_reset_stats()
1029 sizeof(state->ber_jiffies_stats_layer)); in dib8000_reset_stats()
1034 struct dib8000_state *state = fe->demodulator_priv; in dib8000_reset()
1036 if ((state->revision = dib8000_identify(&state->i2c)) == 0) in dib8000_reset()
1037 return -EINVAL; in dib8000_reset()
1040 if (state->revision != 0x8090) in dib8000_reset()
1043 if (state->revision == 0x8000) in dib8000_reset()
1046 dibx000_reset_i2c_master(&state->i2c_master); in dib8000_reset()
1050 /* always leave the VBG voltage on - it consumes almost nothing but takes a long time to start */ in dib8000_reset()
1058 if (state->revision == 0x8090) in dib8000_reset()
1072 if (state->revision != 0x8090) { in dib8000_reset()
1073 if (state->cfg.drives) in dib8000_reset()
1074 dib8000_write_word(state, 906, state->cfg.drives); in dib8000_reset()
1076 …dprintk("using standard PAD-drive-settings, please adjust settings in config-struct to be optimal.… in dib8000_reset()
1077 /* min drive SDRAM - not optimal - adjust */ in dib8000_reset()
1083 if (state->revision != 0x8090) in dib8000_reset()
1089 if ((state->revision != 0x8090) && in dib8000_reset()
1093 state->current_agc = NULL; in dib8000_reset()
1097 if (state->cfg.pll->ifreq == 0) in dib8000_reset()
1112 } while (--l); in dib8000_reset()
1117 state->isdbt_cfg_loaded = 0; in dib8000_reset()
1120 if ((state->revision != 8090) && (state->cfg.div_cfg != 0)) in dib8000_reset()
1121 dib8000_write_word(state, 903, state->cfg.div_cfg); in dib8000_reset()
1130 if (state->revision != 0x8090) in dib8000_reset()
1154 if (state->cfg.update_lna) { in dib8000_update_lna()
1155 // read dyn_gain here (because it is demod-dependent and not tuner) in dib8000_update_lna()
1158 if (state->cfg.update_lna(state->fe[0], dyn_gain)) { in dib8000_update_lna()
1172 if (state->current_band == band && state->current_agc != NULL) in dib8000_set_agc_config()
1174 state->current_band = band; in dib8000_set_agc_config()
1176 for (i = 0; i < state->cfg.agc_config_count; i++) in dib8000_set_agc_config()
1177 if (state->cfg.agc[i].band_caps & band) { in dib8000_set_agc_config()
1178 agc = &state->cfg.agc[i]; in dib8000_set_agc_config()
1184 return -EINVAL; in dib8000_set_agc_config()
1187 state->current_agc = agc; in dib8000_set_agc_config()
1190 dib8000_write_word(state, 76, agc->setup); in dib8000_set_agc_config()
1191 dib8000_write_word(state, 77, agc->inv_gain); in dib8000_set_agc_config()
1192 dib8000_write_word(state, 78, agc->time_stabiliz); in dib8000_set_agc_config()
1193 dib8000_write_word(state, 101, (agc->alpha_level << 12) | agc->thlock); in dib8000_set_agc_config()
1196 dib8000_write_word(state, 102, (agc->alpha_mant << 5) | agc->alpha_exp); in dib8000_set_agc_config()
1197 dib8000_write_word(state, 103, (agc->beta_mant << 6) | agc->beta_exp); in dib8000_set_agc_config()
1200 …state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, ag… in dib8000_set_agc_config()
1203 if (state->wbd_ref != 0) in dib8000_set_agc_config()
1204 dib8000_write_word(state, 106, state->wbd_ref); in dib8000_set_agc_config()
1206 dib8000_write_word(state, 106, agc->wbd_ref); in dib8000_set_agc_config()
1208 if (state->revision == 0x8090) { in dib8000_set_agc_config()
1210 dib8000_write_word(state, 922, reg | (agc->wbd_sel << 2)); in dib8000_set_agc_config()
1213 dib8000_write_word(state, 107, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8)); in dib8000_set_agc_config()
1214 dib8000_write_word(state, 108, agc->agc1_max); in dib8000_set_agc_config()
1215 dib8000_write_word(state, 109, agc->agc1_min); in dib8000_set_agc_config()
1216 dib8000_write_word(state, 110, agc->agc2_max); in dib8000_set_agc_config()
1217 dib8000_write_word(state, 111, agc->agc2_min); in dib8000_set_agc_config()
1218 dib8000_write_word(state, 112, (agc->agc1_pt1 << 8) | agc->agc1_pt2); in dib8000_set_agc_config()
1219 dib8000_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2); in dib8000_set_agc_config()
1220 dib8000_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2); in dib8000_set_agc_config()
1221 dib8000_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2); in dib8000_set_agc_config()
1223 dib8000_write_word(state, 75, agc->agc1_pt3); in dib8000_set_agc_config()
1224 if (state->revision != 0x8090) in dib8000_set_agc_config()
1227 (agc->wbd_inv << 4) | (agc->wbd_sel << 2)); in dib8000_set_agc_config()
1234 struct dib8000_state *state = fe->demodulator_priv; in dib8000_pwm_agc_reset()
1236 …dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency /… in dib8000_pwm_agc_reset()
1243 …if (!state->current_agc || !state->current_agc->perform_agc_softsplit || state->current_agc->split… in dib8000_agc_soft_split()
1249 if (agc > state->current_agc->split.min_thres) in dib8000_agc_soft_split()
1250 split_offset = state->current_agc->split.min; in dib8000_agc_soft_split()
1251 else if (agc < state->current_agc->split.max_thres) in dib8000_agc_soft_split()
1252 split_offset = state->current_agc->split.max; in dib8000_agc_soft_split()
1254 split_offset = state->current_agc->split.max * in dib8000_agc_soft_split()
1255 (agc - state->current_agc->split.min_thres) / in dib8000_agc_soft_split()
1256 (state->current_agc->split.max_thres - state->current_agc->split.min_thres); in dib8000_agc_soft_split()
1267 struct dib8000_state *state = fe->demodulator_priv; in dib8000_agc_startup()
1268 enum frontend_tune_state *tune_state = &state->tune_state; in dib8000_agc_startup()
1275 // set power-up level: interf+analog+AGC in dib8000_agc_startup()
1277 if (state->revision != 0x8090) in dib8000_agc_startup()
1289 /* enable adc i & q */ in dib8000_agc_startup()
1295 …if (dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequen… in dib8000_agc_startup()
1297 state->status = FE_STATUS_TUNE_FAILED; in dib8000_agc_startup()
1307 if (state->cfg.agc_control) in dib8000_agc_startup()
1308 state->cfg.agc_control(fe, 1); in dib8000_agc_startup()
1331 if (state->cfg.agc_control) in dib8000_agc_startup()
1332 state->cfg.agc_control(fe, 0); in dib8000_agc_startup()
1387 if ((syncFreq & ((1 << quantif) - 1)) != 0) in dib8096p_calcSyncFreq()
1393 syncFreq = syncFreq - 1; in dib8096p_calcSyncFreq()
1468 if ((enSerialMode == 1) && (state->input_mode_mpeg == 1)) in dib8096p_configMpegMux()
1528 struct dib8000_state *state = fe->demodulator_priv; in dib8096p_set_diversity_in()
1532 case 0: /* only use the internal way - not the diversity input */ in dib8096p_set_diversity_in()
1547 state->input_mode_mpeg = 1; in dib8096p_set_diversity_in()
1553 state->input_mode_mpeg = 0; in dib8096p_set_diversity_in()
1557 dib8000_set_diversity_in(state->fe[0], onoff); in dib8096p_set_diversity_in()
1563 struct dib8000_state *state = fe->demodulator_priv; in dib8096p_set_output_mode()
1568 state->output_mode = mode; in dib8096p_set_output_mode()
1640 state->cfg.output_mpeg2_in_188_bytes); in dib8096p_set_output_mode()
1641 if (state->cfg.output_mpeg2_in_188_bytes) in dib8096p_set_output_mode()
1654 if (msg->buf[0] <= 15) in map_addr_to_serpar_number()
1655 msg->buf[0] -= 1; in map_addr_to_serpar_number()
1656 else if (msg->buf[0] == 17) in map_addr_to_serpar_number()
1657 msg->buf[0] = 15; in map_addr_to_serpar_number()
1658 else if (msg->buf[0] == 16) in map_addr_to_serpar_number()
1659 msg->buf[0] = 17; in map_addr_to_serpar_number()
1660 else if (msg->buf[0] == 19) in map_addr_to_serpar_number()
1661 msg->buf[0] = 16; in map_addr_to_serpar_number()
1662 else if (msg->buf[0] >= 21 && msg->buf[0] <= 25) in map_addr_to_serpar_number()
1663 msg->buf[0] -= 3; in map_addr_to_serpar_number()
1664 else if (msg->buf[0] == 28) in map_addr_to_serpar_number()
1665 msg->buf[0] = 23; in map_addr_to_serpar_number()
1666 else if (msg->buf[0] == 99) in map_addr_to_serpar_number()
1667 msg->buf[0] = 99; in map_addr_to_serpar_number()
1669 return -EINVAL; in map_addr_to_serpar_number()
1683 i--; in dib8096p_tuner_write_serpar()
1704 i--; in dib8096p_tuner_read_serpar()
1713 i--; in dib8096p_tuner_read_serpar()
1887 struct dib8000_state *st = fe->demodulator_priv; in dib8096p_get_i2c_tuner()
1888 return &st->dib8096p_tuner_adap; in dib8096p_get_i2c_tuner()
1893 struct dib8000_state *state = fe->demodulator_priv; in dib8096p_tuner_sleep()
1902 state->tuner_enable = en_cur_state ; in dib8096p_tuner_sleep()
1907 if (state->tuner_enable != 0) in dib8096p_tuner_sleep()
1908 en_cur_state = state->tuner_enable; in dib8096p_tuner_sleep()
1923 struct dib8000_state *state = fe->demodulator_priv; in dib8000_get_adc_power()
1933 ix = (u8)((mant-1000)/100); /* index of the LUT */ in dib8000_get_adc_power()
1934 val = (lut_1000ln_mant[ix] + 693*(exp-20) - 6908); in dib8000_get_adc_power()
1942 struct dib8000_state *state = fe->demodulator_priv; in dib8090p_get_dc_power()
1954 val -= 1024; in dib8090p_get_dc_power()
1961 u32 timf = state->timf = dib8000_read32(state, 435); in dib8000_update_timf()
1965 dprintk("Updated timing frequency: %d (default: %d)\n", state->timf, state->timf_default); in dib8000_update_timf()
1970 struct dib8000_state *state = fe->demodulator_priv; in dib8000_ctrl_timf()
1974 state->timf = timf; in dib8000_ctrl_timf()
1982 dib8000_set_bandwidth(state->fe[0], 6000); in dib8000_ctrl_timf()
1984 return state->timf; in dib8000_ctrl_timf()
1996 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_set_layer()
1998 switch (c->layer[layer_index].modulation) { in dib8000_set_layer()
2014 switch (c->layer[layer_index].fec) { in dib8000_set_layer()
2033 time_intlv = fls(c->layer[layer_index].interleaving); in dib8000_set_layer()
2034 if (time_intlv > 3 && !(time_intlv == 4 && c->isdbt_sb_mode == 1)) in dib8000_set_layer()
2037 …dib8000_write_word(state, 2 + layer_index, (constellation << 10) | ((c->layer[layer_index].segment… in dib8000_set_layer()
2038 if (c->layer[layer_index].segment_count > 0) { in dib8000_set_layer()
2042 if (c->layer[layer_index].modulation == QAM_16 || c->layer[layer_index].modulation == QAM_64) in dib8000_set_layer()
2043 max_constellation = c->layer[layer_index].modulation; in dib8000_set_layer()
2046 if (c->layer[layer_index].modulation == QAM_64) in dib8000_set_layer()
2047 max_constellation = c->layer[layer_index].modulation; in dib8000_set_layer()
2055 …4, 0xfff8}; /* P_adp_regul_cnt 0.04, P_adp_noise_cnt -0.002, P_adp_regul_ext 0.02, P_adp_noise_ext…
2056 …4, 0xfff0}; /* P_adp_regul_cnt 0.07, P_adp_noise_cnt -0.004, P_adp_regul_ext 0.02, P_adp_noise_ext…
2057 …3, 0xfff8}; /* P_adp_regul_cnt 0.3, P_adp_noise_cnt -0.01, P_adp_regul_ext 0.1, P_adp_noise_ext…
2091 /* update ADC target depending on ana_gain */ in dib8000_update_ana_gain()
2092 if (ana_gain) { /* set -16dB ADC target for ana_gain=-1 */ in dib8000_update_ana_gain()
2095 } else { /* set -22dB ADC target for ana_gain=0 */ in dib8000_update_ana_gain()
2097 dib8000_write_word(state, 80 + i, adc_target_16dB[i] - 355); in dib8000_update_ana_gain()
2105 if (state->isdbt_cfg_loaded == 0) in dib8000_load_ana_fe_coefs()
2127 switch (state->fe[0]->dtv_property_cache.transmission_mode) { in dib8000_get_init_prbs()
2143 state->seg_mask = 0x1fff; /* All 13 segments enabled */ in dib8000_set_13seg_channel()
2145 /* ---- COFF ---- Carloff, the most robust --- */ in dib8000_set_13seg_channel()
2146 …if (state->isdbt_cfg_loaded == 0) { /* if not Sound Broadcasting mode : put default values for 13… in dib8000_set_13seg_channel()
2172 if (state->cfg.pll->ifreq == 0) in dib8000_set_13seg_channel()
2173 …dib8000_write_word(state, 266, ~state->seg_mask | state->seg_diff_mask | 0x40); /* P_equal_noise_s… in dib8000_set_13seg_channel()
2190 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_small_fine_tune()
2192 dib8000_write_word(state, 352, state->seg_diff_mask); in dib8000_small_fine_tune()
2193 dib8000_write_word(state, 353, state->seg_mask); in dib8000_small_fine_tune()
2195 …/* P_small_coef_ext_enable=ISDB-Tsb, P_small_narrow_band=ISDB-Tsb, P_small_last_seg=13, P_small_of… in dib8000_small_fine_tune()
2196 dib8000_write_word(state, 351, (c->isdbt_sb_mode << 9) | (c->isdbt_sb_mode << 8) | (13 << 4) | 5); in dib8000_small_fine_tune()
2198 if (c->isdbt_sb_mode) { in dib8000_small_fine_tune()
2199 /* ---- SMALL ---- */ in dib8000_small_fine_tune()
2200 switch (c->transmission_mode) { in dib8000_small_fine_tune()
2202 if (c->isdbt_partial_reception == 0) { /* 1-seg */ in dib8000_small_fine_tune()
2203 if (c->layer[0].modulation == DQPSK) /* DQPSK */ in dib8000_small_fine_tune()
2207 } else { /* 3-segments */ in dib8000_small_fine_tune()
2208 if (c->layer[0].modulation == DQPSK) { /* DQPSK on central segment */ in dib8000_small_fine_tune()
2209 if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */ in dib8000_small_fine_tune()
2214 if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */ in dib8000_small_fine_tune()
2222 if (c->isdbt_partial_reception == 0) { /* 1-seg */ in dib8000_small_fine_tune()
2223 if (c->layer[0].modulation == DQPSK) /* DQPSK */ in dib8000_small_fine_tune()
2227 } else { /* 3-segments */ in dib8000_small_fine_tune()
2228 if (c->layer[0].modulation == DQPSK) { /* DQPSK on central segment */ in dib8000_small_fine_tune()
2229 if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */ in dib8000_small_fine_tune()
2234 if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */ in dib8000_small_fine_tune()
2244 if (c->isdbt_partial_reception == 0) { /* 1-seg */ in dib8000_small_fine_tune()
2245 if (c->layer[0].modulation == DQPSK) /* DQPSK */ in dib8000_small_fine_tune()
2249 } else { /* 3-segments */ in dib8000_small_fine_tune()
2250 if (c->layer[0].modulation == DQPSK) { /* DQPSK on central segment */ in dib8000_small_fine_tune()
2251 if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */ in dib8000_small_fine_tune()
2256 if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */ in dib8000_small_fine_tune()
2274 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_set_sb_channel()
2278 if (c->transmission_mode == TRANSMISSION_MODE_2K || c->transmission_mode == TRANSMISSION_MODE_4K) { in dib8000_set_sb_channel()
2286 if (c->isdbt_partial_reception == 1) /* 3-segments */ in dib8000_set_sb_channel()
2287 state->seg_mask = 0x00E0; in dib8000_set_sb_channel()
2288 else /* 1-segment */ in dib8000_set_sb_channel()
2289 state->seg_mask = 0x0040; in dib8000_set_sb_channel()
2293 /* ---- COFF ---- Carloff, the most robust --- */ in dib8000_set_sb_channel()
2295 …dib8000_write_word(state, 187, (4 << 12) | (0 << 11) | (63 << 5) | (0x3 << 3) | ((~c->isdbt_partia… in dib8000_set_sb_channel()
2301 if (c->isdbt_partial_reception == 0) { in dib8000_set_sb_channel()
2302 …63, P_coff_thres_lock=15, P_coff_one_seg_width = (P_mode == 3) , P_coff_one_seg_sym = (P_mode-1) */ in dib8000_set_sb_channel()
2303 if (state->mode == 3) in dib8000_set_sb_channel()
2304 dib8000_write_word(state, 180, 0x1fcf | ((state->mode - 1) << 14)); in dib8000_set_sb_channel()
2306 dib8000_write_word(state, 180, 0x0fcf | ((state->mode - 1) << 14)); in dib8000_set_sb_channel()
2321 if (c->isdbt_partial_reception == 0 && c->transmission_mode == TRANSMISSION_MODE_2K) in dib8000_set_sb_channel()
2335 …dib8000_write_word(state, 266, ~state->seg_mask | state->seg_diff_mask); /* P_equal_noise_seg_inh … in dib8000_set_sb_channel()
2337 if (c->isdbt_partial_reception == 0) in dib8000_set_sb_channel()
2349 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_set_isdbt_common_channel()
2352 c->isdbt_partial_reception = 1; in dib8000_set_isdbt_common_channel()
2358 state->mode = fft_to_mode(state); in dib8000_set_isdbt_common_channel()
2362 dib8000_write_word(state, 1, (tmp&0xfffc) | (c->guard_interval & 0x3)); in dib8000_set_isdbt_common_channel()
2364 …te, 274, (dib8000_read_word(state, 274) & 0xffcf) | ((c->isdbt_partial_reception & 1) << 5) | ((c-… in dib8000_set_isdbt_common_channel()
2367 if (c->isdbt_partial_reception) { in dib8000_set_isdbt_common_channel()
2368 state->seg_diff_mask = (c->layer[0].modulation == DQPSK) << permu_seg[0]; in dib8000_set_isdbt_common_channel()
2370 nbseg_diff += (c->layer[i].modulation == DQPSK) * c->layer[i].segment_count; in dib8000_set_isdbt_common_channel()
2372 state->seg_diff_mask |= 1 << permu_seg[i+1]; in dib8000_set_isdbt_common_channel()
2375 nbseg_diff += (c->layer[i].modulation == DQPSK) * c->layer[i].segment_count; in dib8000_set_isdbt_common_channel()
2377 state->seg_diff_mask |= 1 << permu_seg[i]; in dib8000_set_isdbt_common_channel()
2380 if (state->seg_diff_mask) in dib8000_set_isdbt_common_channel()
2388 state->layer_b_nb_seg = c->layer[1].segment_count; in dib8000_set_isdbt_common_channel()
2389 state->layer_c_nb_seg = c->layer[2].segment_count; in dib8000_set_isdbt_common_channel()
2392 /* WRITE: Mode & Diff mask */ in dib8000_set_isdbt_common_channel()
2393 dib8000_write_word(state, 0, (state->mode << 13) | state->seg_diff_mask); in dib8000_set_isdbt_common_channel()
2395 state->differential_constellation = (state->seg_diff_mask != 0); in dib8000_set_isdbt_common_channel()
2403 /* ---- ANA_FE ---- */ in dib8000_set_isdbt_common_channel()
2404 if (c->isdbt_partial_reception) /* 3-segments */ in dib8000_set_isdbt_common_channel()
2407 dib8000_load_ana_fe_coefs(state, ana_fe_coeff_1seg); /* 1-segment */ in dib8000_set_isdbt_common_channel()
2410 if (c->isdbt_sb_mode) { in dib8000_set_isdbt_common_channel()
2412 if (c->isdbt_sb_subchannel < 14) in dib8000_set_isdbt_common_channel()
2413 init_prbs = dib8000_get_init_prbs(state, c->isdbt_sb_subchannel); in dib8000_set_isdbt_common_channel()
2426 /* ---- CHAN_BLK ---- */ in dib8000_set_isdbt_common_channel()
2428 if ((((~state->seg_diff_mask) >> i) & 1) == 1) { in dib8000_set_isdbt_common_channel()
2429 …p_cfr_left_edge += (1 << i) * ((i == 0) || ((((state->seg_mask & (~state->seg_diff_mask)) >> (i -… in dib8000_set_isdbt_common_channel()
2430 …p_cfr_right_edge += (1 << i) * ((i == 12) || ((((state->seg_mask & (~state->seg_diff_mask)) >> (i … in dib8000_set_isdbt_common_channel()
2437 dib8000_write_word(state, 189, ~state->seg_mask | state->seg_diff_mask); /* P_lmod4_seg_inh */ in dib8000_set_isdbt_common_channel()
2438 dib8000_write_word(state, 192, ~state->seg_mask | state->seg_diff_mask); /* P_pha3_seg_inh */ in dib8000_set_isdbt_common_channel()
2439 dib8000_write_word(state, 225, ~state->seg_mask | state->seg_diff_mask); /* P_tac_seg_inh */ in dib8000_set_isdbt_common_channel()
2442 …dib8000_write_word(state, 288, (~state->seg_mask | state->seg_diff_mask) & 0x1fff); /* P_tmcc_seg_… in dib8000_set_isdbt_common_channel()
2444 …1fff); /*disable equalisation of the tmcc when autosearch to be able to find the DQPSK channels. */ in dib8000_set_isdbt_common_channel()
2446 dib8000_write_word(state, 211, state->seg_mask & (~state->seg_diff_mask)); /* P_des_seg_enabled */ in dib8000_set_isdbt_common_channel()
2447 dib8000_write_word(state, 287, ~state->seg_mask | 0x1000); /* P_tmcc_seg_inh */ in dib8000_set_isdbt_common_channel()
2451 /* ---- TMCC ---- */ in dib8000_set_isdbt_common_channel()
2453 tmcc_pow += (((c->layer[i].modulation == DQPSK) * 4 + 1) * c->layer[i].segment_count) ; in dib8000_set_isdbt_common_channel()
2457 tmcc_pow *= (1 << (9-2)); in dib8000_set_isdbt_common_channel()
2463 /* ---- PHA3 ---- */ in dib8000_set_isdbt_common_channel()
2464 if (state->isdbt_cfg_loaded == 0) in dib8000_set_isdbt_common_channel()
2467 state->isdbt_cfg_loaded = 0; in dib8000_set_isdbt_common_channel()
2478 if (state->revision == 0x8090) in dib8000_wait_lock()
2494 struct dib8000_state *state = fe->demodulator_priv; in dib8000_autosearch_start()
2495 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_autosearch_start()
2497 u32 value, internal = state->cfg.pll->internal; in dib8000_autosearch_start()
2499 if (state->revision == 0x8090) in dib8000_autosearch_start()
2502 if ((state->revision >= 0x8002) && in dib8000_autosearch_start()
2503 (state->autosearch_state == AS_SEARCHING_FFT)) { in dib8000_autosearch_start()
2514 if (state->revision == 0x8090) in dib8000_autosearch_start()
2526 if (state->revision == 0x8090) in dib8000_autosearch_start()
2539 } else if ((state->revision >= 0x8002) && in dib8000_autosearch_start()
2540 (state->autosearch_state == AS_SEARCHING_GUARD)) { in dib8000_autosearch_start()
2541 c->transmission_mode = TRANSMISSION_MODE_8K; in dib8000_autosearch_start()
2542 c->guard_interval = GUARD_INTERVAL_1_8; in dib8000_autosearch_start()
2543 c->inversion = 0; in dib8000_autosearch_start()
2544 c->layer[0].modulation = QAM_64; in dib8000_autosearch_start()
2545 c->layer[0].fec = FEC_2_3; in dib8000_autosearch_start()
2546 c->layer[0].interleaving = 0; in dib8000_autosearch_start()
2547 c->layer[0].segment_count = 13; in dib8000_autosearch_start()
2550 c->transmission_mode = state->found_nfft; in dib8000_autosearch_start()
2556 if (state->revision == 0x8090) in dib8000_autosearch_start()
2563 if (state->revision == 0x8090) in dib8000_autosearch_start()
2579 c->inversion = 0; in dib8000_autosearch_start()
2580 c->layer[0].modulation = QAM_64; in dib8000_autosearch_start()
2581 c->layer[0].fec = FEC_2_3; in dib8000_autosearch_start()
2582 c->layer[0].interleaving = 0; in dib8000_autosearch_start()
2583 c->layer[0].segment_count = 13; in dib8000_autosearch_start()
2584 if (!c->isdbt_sb_mode) in dib8000_autosearch_start()
2585 c->layer[0].segment_count = 13; in dib8000_autosearch_start()
2588 if (c->isdbt_sb_mode) { in dib8000_autosearch_start()
2592 if (c->guard_interval == GUARD_INTERVAL_AUTO) { in dib8000_autosearch_start()
2593 if (c->transmission_mode == TRANSMISSION_MODE_AUTO) { in dib8000_autosearch_start()
2594 c->transmission_mode = TRANSMISSION_MODE_8K; in dib8000_autosearch_start()
2595 c->guard_interval = GUARD_INTERVAL_1_8; in dib8000_autosearch_start()
2599 c->guard_interval = GUARD_INTERVAL_1_8; in dib8000_autosearch_start()
2603 if (c->transmission_mode == TRANSMISSION_MODE_AUTO) { in dib8000_autosearch_start()
2604 c->transmission_mode = TRANSMISSION_MODE_8K; in dib8000_autosearch_start()
2617 if (state->revision == 0x8090) in dib8000_autosearch_start()
2624 if (state->revision == 0x8090) in dib8000_autosearch_start()
2639 struct dib8000_state *state = fe->demodulator_priv; in dib8000_autosearch_irq()
2642 if ((state->revision >= 0x8002) && in dib8000_autosearch_irq()
2643 (state->autosearch_state == AS_SEARCHING_FFT)) { in dib8000_autosearch_irq()
2678 u32 dds = state->cfg.pll->ifreq & 0x1ffffff; in dib8000_set_dds()
2679 u8 invert = !!(state->cfg.pll->ifreq & (1 << 25)); in dib8000_set_dds()
2682 if (state->revision == 0x8090) { in dib8000_set_dds()
2686 dds = (1 << 26) - (abs_offset_khz * unit_khz_dds_val); in dib8000_set_dds()
2691 dds = (1<<26) - dds; in dib8000_set_dds()
2694 unit_khz_dds_val = (u16) (67108864 / state->cfg.pll->internal); in dib8000_set_dds()
2697 unit_khz_dds_val *= -1; in dib8000_set_dds()
2701 dds -= abs_offset_khz * unit_khz_dds_val; in dib8000_set_dds()
2706 dprintk("setting a DDS frequency offset of %c%dkHz\n", invert ? '-' : ' ', dds / unit_khz_dds_val); in dib8000_set_dds()
2708 if (abs_offset_khz <= (state->cfg.pll->internal / ratio)) { in dib8000_set_dds()
2718 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_set_frequency_offset()
2723 if (state->fe[0]->ops.tuner_ops.get_frequency) in dib8000_set_frequency_offset()
2724 state->fe[0]->ops.tuner_ops.get_frequency(state->fe[0], ¤t_rf); in dib8000_set_frequency_offset()
2726 current_rf = c->frequency; in dib8000_set_frequency_offset()
2728 total_dds_offset_khz = (int)current_rf - (int)c->frequency / 1000; in dib8000_set_frequency_offset()
2730 if (c->isdbt_sb_mode) { in dib8000_set_frequency_offset()
2731 state->subchannel = c->isdbt_sb_subchannel; in dib8000_set_frequency_offset()
2734 dib8000_write_word(state, 26, c->inversion ^ i); in dib8000_set_frequency_offset()
2736 if (state->cfg.pll->ifreq == 0) { /* low if tuner */ in dib8000_set_frequency_offset()
2737 if ((c->inversion ^ i) == 0) in dib8000_set_frequency_offset()
2740 if ((c->inversion ^ i) == 0) in dib8000_set_frequency_offset()
2741 total_dds_offset_khz *= -1; in dib8000_set_frequency_offset()
2745 …ncy = %dHz & current_rf = %dHz) total_dds_offset_hz = %d\n", c->frequency - current_rf, c->frequen… in dib8000_set_frequency_offset()
2755 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_get_symbol_duration()
2758 switch (c->transmission_mode) { in dib8000_get_symbol_duration()
2772 return (LUT_isdbt_symbol_duration[i] / (c->bandwidth_hz / 1000)) + 1; in dib8000_get_symbol_duration()
2777 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_set_isdbt_loop_params()
2782 if (c->isdbt_sb_mode) { in dib8000_set_isdbt_loop_params()
2783 if (c->isdbt_partial_reception == 0) { in dib8000_set_isdbt_loop_params()
2784 …reg_32 = ((11 - state->mode) << 12) | (6 << 8) | 0x40; /* P_timf_alpha = (11-P_mode), P_corm_alpha… in dib8000_set_isdbt_loop_params()
2785 …g_37 = (3 << 5) | (0 << 4) | (10 - state->mode); /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_… in dib8000_set_isdbt_loop_params()
2787 …reg_32 = ((10 - state->mode) << 12) | (6 << 8) | 0x60; /* P_timf_alpha = (10-P_mode), P_corm_alpha… in dib8000_set_isdbt_loop_params()
2788 …eg_37 = (3 << 5) | (0 << 4) | (9 - state->mode); /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_… in dib8000_set_isdbt_loop_params()
2790 } else { /* 13-seg start conf offset loop parameters */ in dib8000_set_isdbt_loop_params()
2791 …reg_32 = ((9 - state->mode) << 12) | (6 << 8) | 0x80; /* P_timf_alpha = (9-P_mode, P_corm_alpha=6,… in dib8000_set_isdbt_loop_params()
2792 …reg_37 = (3 << 5) | (0 << 4) | (8 - state->mode); /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P… in dib8000_set_isdbt_loop_params()
2796 if (c->isdbt_sb_mode) { in dib8000_set_isdbt_loop_params()
2797 if (c->isdbt_partial_reception == 0) { /* Sound Broadcasting mode 1 seg */ in dib8000_set_isdbt_loop_params()
2798 …reg_32 = ((13-state->mode) << 12) | (6 << 8) | 0x40; /* P_timf_alpha = (13-P_mode) , P_corm_alpha=… in dib8000_set_isdbt_loop_params()
2799 reg_37 = (12-state->mode) | ((5 + state->mode) << 5); in dib8000_set_isdbt_loop_params()
2801 …reg_32 = ((12-state->mode) << 12) | (6 << 8) | 0x60; /* P_timf_alpha = (12-P_mode) , P_corm_alpha=… in dib8000_set_isdbt_loop_params()
2802 reg_37 = (11-state->mode) | ((5 + state->mode) << 5); in dib8000_set_isdbt_loop_params()
2805 …reg_32 = ((11-state->mode) << 12) | (6 << 8) | 0x80; /* P_timf_alpha = 8 , P_corm_alpha=6, P_corm_… in dib8000_set_isdbt_loop_params()
2806 reg_37 = ((5+state->mode) << 5) | (10 - state->mode); in dib8000_set_isdbt_loop_params()
2823 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_set_sync_wait()
2826 /* P_dvsy_sync_wait - reuse mode */ in dib8000_set_sync_wait()
2827 switch (c->transmission_mode) { in dib8000_set_sync_wait()
2840 if (state->cfg.diversity_delay == 0) in dib8000_set_sync_wait()
2841 …sync_wait = (sync_wait * (1 << (c->guard_interval)) * 3) / 2 + 48; /* add 50% SFN margin + compens… in dib8000_set_sync_wait()
2843 …t = (sync_wait * (1 << (c->guard_interval)) * 3) / 2 + state->cfg.diversity_delay; /* add 50% SFN … in dib8000_set_sync_wait()
2851 delay *= state->symbol_duration; in dib8000_get_timeout()
2858 struct dib8000_state *state = fe->demodulator_priv; in dib8000_get_status()
2859 return state->status; in dib8000_get_status()
2864 struct dib8000_state *state = fe->demodulator_priv; in dib8000_get_tune_state()
2865 return state->tune_state; in dib8000_get_tune_state()
2870 struct dib8000_state *state = fe->demodulator_priv; in dib8000_set_tune_state()
2872 state->tune_state = tune_state; in dib8000_set_tune_state()
2878 struct dib8000_state *state = fe->demodulator_priv; in dib8000_tune_restart_from_demod()
2880 state->status = FE_STATUS_TUNE_PENDING; in dib8000_tune_restart_from_demod()
2881 state->tune_state = CT_DEMOD_START; in dib8000_tune_restart_from_demod()
2887 struct dib8000_state *state = fe->demodulator_priv; in dib8000_read_lock()
2889 if (state->revision == 0x8090) in dib8000_read_lock()
2912 * is_manual_mode - Check if TMCC should be used for parameters settings
2920 * It requires that both per-layer and per-transponder parameters to be
2930 /* Use auto mode on DVB-T compat mode */ in is_manual_mode()
2931 if (c->delivery_system != SYS_ISDBT) in is_manual_mode()
2937 if (c->transmission_mode == TRANSMISSION_MODE_AUTO) { in is_manual_mode()
2945 if (c->guard_interval == GUARD_INTERVAL_AUTO) { in is_manual_mode()
2954 if (!c->isdbt_layer_enabled) { in is_manual_mode()
2960 * Check if the per-layer parameters aren't auto and in is_manual_mode()
2964 if (!(c->isdbt_layer_enabled & 1 << i)) in is_manual_mode()
2967 if ((c->layer[i].segment_count > 13) || in is_manual_mode()
2968 (c->layer[i].segment_count == 0)) { in is_manual_mode()
2969 c->isdbt_layer_enabled &= ~(1 << i); in is_manual_mode()
2973 n_segs += c->layer[i].segment_count; in is_manual_mode()
2975 if ((c->layer[i].modulation == QAM_AUTO) || in is_manual_mode()
2976 (c->layer[i].fec == FEC_AUTO)) { in is_manual_mode()
2998 struct dib8000_state *state = fe->demodulator_priv; in dib8000_tune()
2999 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_tune()
3000 enum frontend_tune_state *tune_state = &state->tune_state; in dib8000_tune()
3005 unsigned long *timeout = &state->timeout; in dib8000_tune()
3017 state->channel_parameters_set, *tune_state, state->autosearch_state, now); in dib8000_tune()
3024 if (state->revision == 0x8090) in dib8000_tune()
3026 state->status = FE_STATUS_TUNE_PENDING; in dib8000_tune()
3027 state->channel_parameters_set = is_manual_mode(c); in dib8000_tune()
3030 state->channel_parameters_set ? "manual" : "auto"); in dib8000_tune()
3038 dib8000_set_bandwidth(fe, c->bandwidth_hz / 1000); in dib8000_tune()
3040 if (state->channel_parameters_set == 0) { /* The channel struct is unknown, search it ! */ in dib8000_tune()
3042 if (state->revision != 0x8090) { in dib8000_tune()
3043 state->agc1_max = dib8000_read_word(state, 108); in dib8000_tune()
3044 state->agc1_min = dib8000_read_word(state, 109); in dib8000_tune()
3045 state->agc2_max = dib8000_read_word(state, 110); in dib8000_tune()
3046 state->agc2_min = dib8000_read_word(state, 111); in dib8000_tune()
3055 state->autosearch_state = AS_SEARCHING_FFT; in dib8000_tune()
3056 state->found_nfft = TRANSMISSION_MODE_AUTO; in dib8000_tune()
3057 state->found_guard = GUARD_INTERVAL_AUTO; in dib8000_tune()
3060 state->autosearch_state = AS_DONE; in dib8000_tune()
3063 state->symbol_duration = dib8000_get_symbol_duration(state); in dib8000_tune()
3068 if (state->revision == 0x8090) in dib8000_tune()
3078 state->status = FE_STATUS_TUNE_FAILED; in dib8000_tune()
3079 state->autosearch_state = AS_DONE; in dib8000_tune()
3083 …state->status = FE_STATUS_FFT_SUCCESS; /* signal to the upper layer, that there was a channel foun… in dib8000_tune()
3085 if (state->autosearch_state == AS_SEARCHING_GUARD) in dib8000_tune()
3088 state->autosearch_state = AS_DONE; in dib8000_tune()
3097 switch (state->autosearch_state) { in dib8000_tune()
3100 if (state->revision == 0x8090) { in dib8000_tune()
3119 state->found_nfft = TRANSMISSION_MODE_2K; in dib8000_tune()
3122 state->found_nfft = TRANSMISSION_MODE_4K; in dib8000_tune()
3126 state->found_nfft = TRANSMISSION_MODE_8K; in dib8000_tune()
3132 state->autosearch_state = AS_SEARCHING_GUARD; in dib8000_tune()
3133 if (state->revision == 0x8090) in dib8000_tune()
3140 if (state->revision == 0x8090) in dib8000_tune()
3141 state->found_guard = dib8000_read_word(state, 572) & 0x3; in dib8000_tune()
3143 state->found_guard = dib8000_read_word(state, 570) & 0x3; in dib8000_tune()
3144 /* dprintk("guard interval found=%i\n", state->found_guard); */ in dib8000_tune()
3150 state->status = FE_STATUS_TUNE_FAILED; in dib8000_tune()
3151 state->autosearch_state = AS_DONE; in dib8000_tune()
3167 dib8000_set_diversity_in(state->fe[0], state->diversity_onoff); in dib8000_tune()
3177 if (locks & (0x3 << 11)) { /* coff-lock and off_cpil_lock achieved */ in dib8000_tune()
3178 dib8000_update_timf(state); /* we achieved a coff_cpil_lock - it's time to update the timf */ in dib8000_tune()
3179 if (!state->differential_constellation) { in dib8000_tune()
3192 if ((state->fe[1] != NULL) && (state->output_mode != OUTMODE_DIVERSITY)) { in dib8000_tune()
3194 …if (dib8000_get_status(state->fe[1]) <= FE_STATUS_STD_SUCCESS) /* Something is locked on the input… in dib8000_tune()
3196 …else if (dib8000_get_status(state->fe[1]) >= FE_STATUS_TUNE_TIME_TOO_SHORT) { /* fe in input faile… in dib8000_tune()
3200 state->status = FE_STATUS_TUNE_FAILED; in dib8000_tune()
3206 state->status = FE_STATUS_TUNE_FAILED; in dib8000_tune()
3224 if (c->isdbt_sb_mode in dib8000_tune()
3225 && c->isdbt_sb_subchannel < 14 in dib8000_tune()
3226 && !state->differential_constellation) { in dib8000_tune()
3227 state->subchannel = 0; in dib8000_tune()
3231 state->status = FE_STATUS_LOCKED; in dib8000_tune()
3236 …if ((state->revision == 0x8090) || ((dib8000_read_word(state, 1291) >> 9) & 0x1)) { /* fe capable … in dib8000_tune()
3239 if (c->layer[i].interleaving >= deeper_interleaver) { in dib8000_tune()
3240 dprintk("layer%i: time interleaver = %d\n", i, c->layer[i].interleaving); in dib8000_tune()
3241 if (c->layer[i].segment_count > 0) { /* valid layer */ in dib8000_tune()
3242 deeper_interleaver = c->layer[0].interleaving; in dib8000_tune()
3243 state->longest_intlv_layer = i; in dib8000_tune()
3255 if (state->diversity_onoff != 0) /* because of diversity sync */ in dib8000_tune()
3260 deeper_interleaver, state->longest_intlv_layer, locks, *timeout); in dib8000_tune()
3269 if (locks&(1<<(7-state->longest_intlv_layer))) { /* mpeg lock : check the longest one */ in dib8000_tune()
3270 dprintk("ISDB-T layer locks: Layer A %s, Layer B %s, Layer C %s\n", in dib8000_tune()
3271 c->layer[0].segment_count ? (locks >> 7) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled", in dib8000_tune()
3272 c->layer[1].segment_count ? (locks >> 6) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled", in dib8000_tune()
3273 c->layer[2].segment_count ? (locks >> 5) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled"); in dib8000_tune()
3274 if (c->isdbt_sb_mode in dib8000_tune()
3275 && c->isdbt_sb_subchannel < 14 in dib8000_tune()
3276 && !state->differential_constellation) in dib8000_tune()
3278 state->status = FE_STATUS_DEMOD_SUCCESS; in dib8000_tune()
3280 state->status = FE_STATUS_DATA_LOCKED; in dib8000_tune()
3283 if (c->isdbt_sb_mode in dib8000_tune()
3284 && c->isdbt_sb_subchannel < 14 in dib8000_tune()
3285 && !state->differential_constellation) { /* continue to try init prbs autosearch */ in dib8000_tune()
3286 state->subchannel += 3; in dib8000_tune()
3290 dprintk("Not all ISDB-T layers locked in %d ms: Layer A %s, Layer B %s, Layer C %s\n", in dib8000_tune()
3291 jiffies_to_msecs(now - *timeout), in dib8000_tune()
3292 c->layer[0].segment_count ? (locks >> 7) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled", in dib8000_tune()
3293 c->layer[1].segment_count ? (locks >> 6) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled", in dib8000_tune()
3294 c->layer[2].segment_count ? (locks >> 5) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled"); in dib8000_tune()
3296 state->status = FE_STATUS_DATA_LOCKED; in dib8000_tune()
3298 state->status = FE_STATUS_TUNE_FAILED; in dib8000_tune()
3305 if (state->subchannel <= 41) { in dib8000_tune()
3306 dib8000_set_subchannel_prbs(state, dib8000_get_init_prbs(state, state->subchannel)); in dib8000_tune()
3310 state->status = FE_STATUS_TUNE_FAILED; in dib8000_tune()
3318 /* tuning is finished - cleanup the demod */ in dib8000_tune()
3322 if ((state->revision != 0x8090) && (state->agc1_max != 0)) { in dib8000_tune()
3323 dib8000_write_word(state, 108, state->agc1_max); in dib8000_tune()
3324 dib8000_write_word(state, 109, state->agc1_min); in dib8000_tune()
3325 dib8000_write_word(state, 110, state->agc2_max); in dib8000_tune()
3326 dib8000_write_word(state, 111, state->agc2_min); in dib8000_tune()
3327 state->agc1_max = 0; in dib8000_tune()
3328 state->agc1_min = 0; in dib8000_tune()
3329 state->agc2_max = 0; in dib8000_tune()
3330 state->agc2_min = 0; in dib8000_tune()
3340 return ret * state->symbol_duration; in dib8000_tune()
3341 if ((ret > 0) && (ret < state->symbol_duration)) in dib8000_tune()
3342 return state->symbol_duration; /* at least one symbol */ in dib8000_tune()
3348 struct dib8000_state *state = fe->demodulator_priv; in dib8000_wakeup()
3355 dprintk("could not start Slow ADC\n"); in dib8000_wakeup()
3357 if (state->revision == 0x8090) in dib8000_wakeup()
3360 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_wakeup()
3361 ret = state->fe[index_frontend]->ops.init(state->fe[index_frontend]); in dib8000_wakeup()
3371 struct dib8000_state *state = fe->demodulator_priv; in dib8000_sleep()
3375 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_sleep()
3376 ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]); in dib8000_sleep()
3381 if (state->revision != 0x8090) in dib8000_sleep()
3392 struct dib8000_state *state = fe->demodulator_priv; in dib8000_get_frontend()
3397 c->bandwidth_hz = 6000000; in dib8000_get_frontend()
3401 * not lock or not sync. This causes dvbv5-scan/dvbv5-zap to fail. in dib8000_get_frontend()
3409 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_get_frontend()
3410 state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat); in dib8000_get_frontend()
3414 state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend], c); in dib8000_get_frontend()
3415 …for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_inde… in dib8000_get_frontend()
3417 …state->fe[sub_index_frontend]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_p… in dib8000_get_frontend()
3418 …state->fe[sub_index_frontend]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_prope… in dib8000_get_frontend()
3419 …state->fe[sub_index_frontend]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->d… in dib8000_get_frontend()
3420 …state->fe[sub_index_frontend]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_… in dib8000_get_frontend()
3421 …state->fe[sub_index_frontend]->dtv_property_cache.isdbt_partial_reception = state->fe[index_fronte… in dib8000_get_frontend()
3423 …state->fe[sub_index_frontend]->dtv_property_cache.layer[i].segment_count = state->fe[index_fronten… in dib8000_get_frontend()
3424 …state->fe[sub_index_frontend]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend… in dib8000_get_frontend()
3425 …state->fe[sub_index_frontend]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_pr… in dib8000_get_frontend()
3426 …state->fe[sub_index_frontend]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]-… in dib8000_get_frontend()
3434 c->isdbt_sb_mode = dib8000_read_word(state, 508) & 0x1; in dib8000_get_frontend()
3436 if (state->revision == 0x8090) in dib8000_get_frontend()
3440 c->inversion = (val & 0x40) >> 6; in dib8000_get_frontend()
3443 c->transmission_mode = TRANSMISSION_MODE_2K; in dib8000_get_frontend()
3447 c->transmission_mode = TRANSMISSION_MODE_4K; in dib8000_get_frontend()
3452 c->transmission_mode = TRANSMISSION_MODE_8K; in dib8000_get_frontend()
3459 c->guard_interval = GUARD_INTERVAL_1_32; in dib8000_get_frontend()
3463 c->guard_interval = GUARD_INTERVAL_1_16; in dib8000_get_frontend()
3468 c->guard_interval = GUARD_INTERVAL_1_8; in dib8000_get_frontend()
3472 c->guard_interval = GUARD_INTERVAL_1_4; in dib8000_get_frontend()
3477 c->isdbt_partial_reception = val & 1; in dib8000_get_frontend()
3478 dprintk("dib8000_get_frontend: partial_reception = %d\n", c->isdbt_partial_reception); in dib8000_get_frontend()
3484 c->layer[i].segment_count = val; in dib8000_get_frontend()
3493 i, c->layer[i].segment_count); in dib8000_get_frontend()
3499 c->layer[i].interleaving = val; in dib8000_get_frontend()
3502 i, c->layer[i].interleaving); in dib8000_get_frontend()
3507 c->layer[i].fec = FEC_1_2; in dib8000_get_frontend()
3512 c->layer[i].fec = FEC_2_3; in dib8000_get_frontend()
3517 c->layer[i].fec = FEC_3_4; in dib8000_get_frontend()
3522 c->layer[i].fec = FEC_5_6; in dib8000_get_frontend()
3527 c->layer[i].fec = FEC_7_8; in dib8000_get_frontend()
3536 c->layer[i].modulation = DQPSK; in dib8000_get_frontend()
3541 c->layer[i].modulation = QPSK; in dib8000_get_frontend()
3546 c->layer[i].modulation = QAM_16; in dib8000_get_frontend()
3552 c->layer[i].modulation = QAM_64; in dib8000_get_frontend()
3560 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_get_frontend()
3561 state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode = c->isdbt_sb_mode; in dib8000_get_frontend()
3562 state->fe[index_frontend]->dtv_property_cache.inversion = c->inversion; in dib8000_get_frontend()
3563 state->fe[index_frontend]->dtv_property_cache.transmission_mode = c->transmission_mode; in dib8000_get_frontend()
3564 state->fe[index_frontend]->dtv_property_cache.guard_interval = c->guard_interval; in dib8000_get_frontend()
3565 …state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception = c->isdbt_partial_reception; in dib8000_get_frontend()
3567 state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count = c->layer[i].segment_count; in dib8000_get_frontend()
3568 state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving = c->layer[i].interleaving; in dib8000_get_frontend()
3569 state->fe[index_frontend]->dtv_property_cache.layer[i].fec = c->layer[i].fec; in dib8000_get_frontend()
3570 state->fe[index_frontend]->dtv_property_cache.layer[i].modulation = c->layer[i].modulation; in dib8000_get_frontend()
3578 struct dib8000_state *state = fe->demodulator_priv; in dib8000_set_frontend()
3579 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_set_frontend()
3584 if (c->frequency == 0) { in dib8000_set_frontend()
3589 if (c->bandwidth_hz == 0) { in dib8000_set_frontend()
3591 c->bandwidth_hz = 6000000; in dib8000_set_frontend()
3594 …for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_set_frontend()
3596 state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_ISDBT; in dib8000_set_frontend()
3597 …memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_… in dib8000_set_frontend()
3600 if (state->revision != 0x8090) { in dib8000_set_frontend()
3601 dib8000_set_diversity_in(state->fe[index_frontend], 1); in dib8000_set_frontend()
3603 dib8000_set_output_mode(state->fe[index_frontend], in dib8000_set_frontend()
3606 dib8000_set_output_mode(state->fe[0], OUTMODE_HIGH_Z); in dib8000_set_frontend()
3608 dib8096p_set_diversity_in(state->fe[index_frontend], 1); in dib8000_set_frontend()
3610 dib8096p_set_output_mode(state->fe[index_frontend], in dib8000_set_frontend()
3613 dib8096p_set_output_mode(state->fe[0], OUTMODE_HIGH_Z); in dib8000_set_frontend()
3617 if (state->fe[index_frontend]->ops.tuner_ops.set_params) in dib8000_set_frontend()
3618 state->fe[index_frontend]->ops.tuner_ops.set_params(state->fe[index_frontend]); in dib8000_set_frontend()
3620 dib8000_set_tune_state(state->fe[index_frontend], CT_AGC_START); in dib8000_set_frontend()
3624 if (state->revision != 0x8090) in dib8000_set_frontend()
3625 dib8000_set_diversity_in(state->fe[index_frontend - 1], 0); in dib8000_set_frontend()
3627 dib8096p_set_diversity_in(state->fe[index_frontend - 1], 0); in dib8000_set_frontend()
3631 time = dib8000_agc_startup(state->fe[0]); in dib8000_set_frontend()
3632 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_set_frontend()
3633 time_slave = dib8000_agc_startup(state->fe[index_frontend]); in dib8000_set_frontend()
3653 …for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_set_frontend()
3654 if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_AGC_STOP) { in dib8000_set_frontend()
3661 …for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_set_frontend()
3662 dib8000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START); in dib8000_set_frontend()
3667 …for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_set_frontend()
3668 delay = dib8000_tune(state->fe[index_frontend]); in dib8000_set_frontend()
3676 if (state->channel_parameters_set == 0) { /* searching */ in dib8000_set_frontend()
3677 …if ((dib8000_get_status(state->fe[index_frontend]) == FE_STATUS_DEMOD_SUCCESS) || (dib8000_get_sta… in dib8000_set_frontend()
3679 …dib8000_get_frontend(state->fe[index_frontend], c); /* we read the channel parameters from the fro… in dib8000_set_frontend()
3680 state->channel_parameters_set = 1; in dib8000_set_frontend()
3682 for (l = 0; (l < MAX_NUMBER_OF_FRONTENDS) && (state->fe[l] != NULL); l++) { in dib8000_set_frontend()
3685 dib8000_tune_restart_from_demod(state->fe[l]); in dib8000_set_frontend()
3687 …state->fe[l]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_property_cache.isd… in dib8000_set_frontend()
3688 …state->fe[l]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_property_cache.inversi… in dib8000_set_frontend()
3689 …state->fe[l]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->dtv_property_cache… in dib8000_set_frontend()
3690 …state->fe[l]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_property_cache.gu… in dib8000_set_frontend()
3691 …state->fe[l]->dtv_property_cache.isdbt_partial_reception = state->fe[index_frontend]->dtv_property… in dib8000_set_frontend()
3693 …state->fe[l]->dtv_property_cache.layer[i].segment_count = state->fe[index_frontend]->dtv_property_… in dib8000_set_frontend()
3694 …state->fe[l]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend]->dtv_property_c… in dib8000_set_frontend()
3695 …state->fe[l]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_property_cache.laye… in dib8000_set_frontend()
3696 …state->fe[l]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]->dtv_property_cac… in dib8000_set_frontend()
3705 if (dib8000_get_status(state->fe[0]) == FE_STATUS_TUNE_FAILED || in dib8000_set_frontend()
3706 dib8000_get_status(state->fe[0]) == FE_STATUS_LOCKED || in dib8000_set_frontend()
3707 dib8000_get_status(state->fe[0]) == FE_STATUS_DATA_LOCKED) { in dib8000_set_frontend()
3710 …for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_set_frontend()
3711 if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_DEMOD_STOP) in dib8000_set_frontend()
3715 dprintk("tuning done with status %d\n", dib8000_get_status(state->fe[0])); in dib8000_set_frontend()
3728 if (state->revision != 0x8090) in dib8000_set_frontend()
3729 dib8000_set_output_mode(state->fe[0], state->cfg.output_mode); in dib8000_set_frontend()
3731 dib8096p_set_output_mode(state->fe[0], state->cfg.output_mode); in dib8000_set_frontend()
3732 if (state->cfg.enMpegOutput == 0) { in dib8000_set_frontend()
3745 struct dib8000_state *state = fe->demodulator_priv; in dib8000_read_status()
3750 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_read_status()
3751 lock_slave |= dib8000_read_lock(state->fe[index_frontend]); in dib8000_read_status()
3787 struct dib8000_state *state = fe->demodulator_priv; in dib8000_read_ber()
3790 if (state->revision == 0x8090) in dib8000_read_ber()
3801 struct dib8000_state *state = fe->demodulator_priv; in dib8000_read_unc_blocks()
3804 if (state->revision == 0x8090) in dib8000_read_unc_blocks()
3813 struct dib8000_state *state = fe->demodulator_priv; in dib8000_read_signal_strength()
3818 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_read_signal_strength()
3819 state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val); in dib8000_read_signal_strength()
3820 if (val > 65535 - *strength) in dib8000_read_signal_strength()
3826 val = 65535 - dib8000_read_word(state, 390); in dib8000_read_signal_strength()
3827 if (val > 65535 - *strength) in dib8000_read_signal_strength()
3836 struct dib8000_state *state = fe->demodulator_priv; in dib8000_get_snr()
3840 if (state->revision != 0x8090) in dib8000_get_snr()
3847 exp -= 0x40; in dib8000_get_snr()
3850 if (state->revision != 0x8090) in dib8000_get_snr()
3857 exp -= 0x40; in dib8000_get_snr()
3862 return t + ((s << 16) - n*t) / n; in dib8000_get_snr()
3869 struct dib8000_state *state = fe->demodulator_priv; in dib8000_read_snr()
3874 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_read_snr()
3875 snr_master += dib8000_get_snr(state->fe[index_frontend]); in dib8000_read_snr()
3905 * strength generated by a DTA-2111 RF generator directly connected into
3906 * a dib8076 device (a PixelView PV-D231U stick), using a good quality
3911 * Yet, it is better to use this measure in dB than a random non-linear
3917 { 55953, 108500 }, /* -22.5 dBm */
3930 { 50117, 96000 }, /* -35 dBm */
3946 { 42010, 80000 }, /* -51 dBm */
3960 if (value < segments[len-1].x) in interpolate_value()
3961 return segments[len-1].y; in interpolate_value()
3963 for (i = 1; i < len - 1; i++) { in interpolate_value()
3972 dy = segments[i - 1].y - segments[i].y; in interpolate_value()
3973 dx = segments[i - 1].x - segments[i].x; in interpolate_value()
3975 tmp64 = value - segments[i].x; in interpolate_value()
3985 struct dib8000_state *state = fe->demodulator_priv; in dib8000_get_time_us()
3986 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_get_time_us()
4001 switch (c->guard_interval) { in dib8000_get_time_us()
4017 switch (c->transmission_mode) { in dib8000_get_time_us()
4032 nsegs = c->layer[i].segment_count; in dib8000_get_time_us()
4036 switch (c->layer[i].modulation) { in dib8000_get_time_us()
4050 switch (c->layer[i].fec) { in dib8000_get_time_us()
4074 interleaving = c->layer[i].interleaving; in dib8000_get_time_us()
4099 struct dib8000_state *state = fe->demodulator_priv; in dib8000_get_stats()
4100 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_get_stats()
4113 ARRAY_SIZE(strength_to_db_table)) - 131000; in dib8000_get_stats()
4114 c->strength.stat[0].svalue = db; in dib8000_get_stats()
4118 c->cnr.len = 1; in dib8000_get_stats()
4119 c->block_count.len = 1; in dib8000_get_stats()
4120 c->block_error.len = 1; in dib8000_get_stats()
4121 c->post_bit_error.len = 1; in dib8000_get_stats()
4122 c->post_bit_count.len = 1; in dib8000_get_stats()
4123 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in dib8000_get_stats()
4124 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in dib8000_get_stats()
4125 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in dib8000_get_stats()
4126 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in dib8000_get_stats()
4127 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in dib8000_get_stats()
4132 if (time_after(jiffies, state->per_jiffies_stats)) { in dib8000_get_stats()
4133 state->per_jiffies_stats = jiffies + msecs_to_jiffies(1000); in dib8000_get_stats()
4138 if (state->fe[i]) in dib8000_get_stats()
4139 snr += dib8000_get_snr(state->fe[i]); in dib8000_get_stats()
4149 c->cnr.stat[0].svalue = snr; in dib8000_get_stats()
4150 c->cnr.stat[0].scale = FE_SCALE_DECIBEL; in dib8000_get_stats()
4154 if (val < state->init_ucb) in dib8000_get_stats()
4155 state->init_ucb += 0x100000000LL; in dib8000_get_stats()
4157 c->block_error.stat[0].scale = FE_SCALE_COUNTER; in dib8000_get_stats()
4158 c->block_error.stat[0].uvalue = val + state->init_ucb; in dib8000_get_stats()
4162 time_us = dib8000_get_time_us(fe, -1); in dib8000_get_stats()
4167 c->block_count.stat[0].scale = FE_SCALE_COUNTER; in dib8000_get_stats()
4168 c->block_count.stat[0].uvalue += blocks; in dib8000_get_stats()
4174 /* Get post-BER measures */ in dib8000_get_stats()
4175 if (time_after(jiffies, state->ber_jiffies_stats)) { in dib8000_get_stats()
4176 time_us = dib8000_get_time_us(fe, -1); in dib8000_get_stats()
4177 state->ber_jiffies_stats = jiffies + msecs_to_jiffies((time_us + 500) / 1000); in dib8000_get_stats()
4182 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; in dib8000_get_stats()
4183 c->post_bit_error.stat[0].uvalue += val; in dib8000_get_stats()
4185 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; in dib8000_get_stats()
4186 c->post_bit_count.stat[0].uvalue += 100000000; in dib8000_get_stats()
4189 if (state->revision < 0x8002) in dib8000_get_stats()
4192 c->block_error.len = 4; in dib8000_get_stats()
4193 c->post_bit_error.len = 4; in dib8000_get_stats()
4194 c->post_bit_count.len = 4; in dib8000_get_stats()
4197 unsigned nsegs = c->layer[i].segment_count; in dib8000_get_stats()
4204 if (time_after(jiffies, state->ber_jiffies_stats_layer[i])) { in dib8000_get_stats()
4207 state->ber_jiffies_stats_layer[i] = jiffies + msecs_to_jiffies((time_us + 500) / 1000); in dib8000_get_stats()
4212 c->post_bit_error.stat[1 + i].scale = FE_SCALE_COUNTER; in dib8000_get_stats()
4213 c->post_bit_error.stat[1 + i].uvalue += val; in dib8000_get_stats()
4215 c->post_bit_count.stat[1 + i].scale = FE_SCALE_COUNTER; in dib8000_get_stats()
4216 c->post_bit_count.stat[1 + i].uvalue += 100000000; in dib8000_get_stats()
4222 c->block_error.stat[1 + i].scale = FE_SCALE_COUNTER; in dib8000_get_stats()
4223 c->block_error.stat[1 + i].uvalue += val; in dib8000_get_stats()
4230 c->block_count.stat[0].scale = FE_SCALE_COUNTER; in dib8000_get_stats()
4231 c->block_count.stat[0].uvalue += blocks; in dib8000_get_stats()
4240 struct dib8000_state *state = fe->demodulator_priv; in dib8000_set_slave_frontend()
4243 while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL)) in dib8000_set_slave_frontend()
4247 state->fe[index_frontend] = fe_slave; in dib8000_set_slave_frontend()
4252 return -ENOMEM; in dib8000_set_slave_frontend()
4257 struct dib8000_state *state = fe->demodulator_priv; in dib8000_get_slave_frontend()
4261 return state->fe[slave_index]; in dib8000_get_slave_frontend()
4274 return -ENOMEM; in dib8000_i2c_enumeration()
4279 ret = -ENOMEM; in dib8000_i2c_enumeration()
4285 ret = -ENOMEM; in dib8000_i2c_enumeration()
4290 for (k = no_of_demods - 1; k >= 0; k--) { in dib8000_i2c_enumeration()
4304 ret = -EINVAL; in dib8000_i2c_enumeration()
4309 /* start diversity to pull_down div_str - just for i2c-enumeration */ in dib8000_i2c_enumeration()
4327 /* deactivate div - it was just for i2c-enumeration */ in dib8000_i2c_enumeration()
4343 tune->min_delay_ms = 1000; in dib8000_fe_get_tune_settings()
4344 tune->step_size = 0; in dib8000_fe_get_tune_settings()
4345 tune->max_drift = 0; in dib8000_fe_get_tune_settings()
4351 struct dib8000_state *st = fe->demodulator_priv; in dib8000_release()
4354 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (st->fe[index_frontend] != … in dib8000_release()
4355 dvb_frontend_detach(st->fe[index_frontend]); in dib8000_release()
4357 dibx000_exit_i2c_master(&st->i2c_master); in dib8000_release()
4358 i2c_del_adapter(&st->dib8096p_tuner_adap); in dib8000_release()
4359 kfree(st->fe[0]); in dib8000_release()
4365 struct dib8000_state *st = fe->demodulator_priv; in dib8000_get_i2c_master()
4366 return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating); in dib8000_get_i2c_master()
4371 struct dib8000_state *st = fe->demodulator_priv; in dib8000_pid_filter_ctrl()
4381 struct dib8000_state *st = fe->demodulator_priv; in dib8000_pid_filter()
4389 .name = "DiBcom 8000 ISDB-T",
4430 memcpy(&state->cfg, cfg, sizeof(struct dib8000_config)); in dib8000_init()
4431 state->i2c.adap = i2c_adap; in dib8000_init()
4432 state->i2c.addr = i2c_addr; in dib8000_init()
4433 state->i2c.i2c_write_buffer = state->i2c_write_buffer; in dib8000_init()
4434 state->i2c.i2c_read_buffer = state->i2c_read_buffer; in dib8000_init()
4435 mutex_init(&state->i2c_buffer_lock); in dib8000_init()
4436 state->i2c.i2c_buffer_lock = &state->i2c_buffer_lock; in dib8000_init()
4437 state->gpio_val = cfg->gpio_val; in dib8000_init()
4438 state->gpio_dir = cfg->gpio_dir; in dib8000_init()
4443 …if ((state->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (state->cfg.output_mode != OUTMODE_MPEG2_P… in dib8000_init()
4444 state->cfg.output_mode = OUTMODE_MPEG2_FIFO; in dib8000_init()
4446 state->fe[0] = fe; in dib8000_init()
4447 fe->demodulator_priv = state; in dib8000_init()
4448 memcpy(&state->fe[0]->ops, &dib8000_ops, sizeof(struct dvb_frontend_ops)); in dib8000_init()
4450 state->timf_default = cfg->pll->timf; in dib8000_init()
4452 if (dib8000_identify(&state->i2c) == 0) in dib8000_init()
4455 dibx000_init_i2c_master(&state->i2c_master, DIB8000, state->i2c.adap, state->i2c.addr); in dib8000_init()
4458 strscpy(state->dib8096p_tuner_adap.name, "DiB8096P tuner interface", in dib8000_init()
4459 sizeof(state->dib8096p_tuner_adap.name)); in dib8000_init()
4460 state->dib8096p_tuner_adap.algo = &dib8096p_tuner_xfer_algo; in dib8000_init()
4461 state->dib8096p_tuner_adap.algo_data = NULL; in dib8000_init()
4462 state->dib8096p_tuner_adap.dev.parent = state->i2c.adap->dev.parent; in dib8000_init()
4463 i2c_set_adapdata(&state->dib8096p_tuner_adap, state); in dib8000_init()
4464 i2c_add_adapter(&state->dib8096p_tuner_adap); in dib8000_init()
4469 state->current_demod_bw = 6000; in dib8000_init()
4483 ops->pwm_agc_reset = dib8000_pwm_agc_reset; in dib8000_attach()
4484 ops->get_dc_power = dib8090p_get_dc_power; in dib8000_attach()
4485 ops->set_gpio = dib8000_set_gpio; in dib8000_attach()
4486 ops->get_slave_frontend = dib8000_get_slave_frontend; in dib8000_attach()
4487 ops->set_tune_state = dib8000_set_tune_state; in dib8000_attach()
4488 ops->pid_filter_ctrl = dib8000_pid_filter_ctrl; in dib8000_attach()
4489 ops->get_adc_power = dib8000_get_adc_power; in dib8000_attach()
4490 ops->update_pll = dib8000_update_pll; in dib8000_attach()
4491 ops->tuner_sleep = dib8096p_tuner_sleep; in dib8000_attach()
4492 ops->get_tune_state = dib8000_get_tune_state; in dib8000_attach()
4493 ops->get_i2c_tuner = dib8096p_get_i2c_tuner; in dib8000_attach()
4494 ops->set_slave_frontend = dib8000_set_slave_frontend; in dib8000_attach()
4495 ops->pid_filter = dib8000_pid_filter; in dib8000_attach()
4496 ops->ctrl_timf = dib8000_ctrl_timf; in dib8000_attach()
4497 ops->init = dib8000_init; in dib8000_attach()
4498 ops->get_i2c_master = dib8000_get_i2c_master; in dib8000_attach()
4499 ops->i2c_enumeration = dib8000_i2c_enumeration; in dib8000_attach()
4500 ops->set_wbd_ref = dib8000_set_wbd_ref; in dib8000_attach()
4507 MODULE_DESCRIPTION("Driver for the DiBcom 8000 ISDB-T demodulator");