53 	spinlock_t lock; /* protect access to IPCC registers */
83 	struct stm32_ipcc *ipcc = data;  in stm32_ipcc_rx_irq()  local
84 	struct device *dev = ipcc->controller.dev;  in stm32_ipcc_rx_irq()
90 	proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST;  in stm32_ipcc_rx_irq()
91 	tosr = readl_relaxed(ipcc->reg_proc + proc_offset + IPCC_XTOYSR);  in stm32_ipcc_rx_irq()
92 	mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);  in stm32_ipcc_rx_irq()
97 	for (chan = 0; chan < ipcc->n_chans; chan++) {  in stm32_ipcc_rx_irq()
103 		mbox_chan_received_data(&ipcc->controller.chans[chan], NULL);  in stm32_ipcc_rx_irq()
105 		stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR,  in stm32_ipcc_rx_irq()
116 	struct stm32_ipcc *ipcc = data;  in stm32_ipcc_tx_irq()  local
117 	struct device *dev = ipcc->controller.dev;  in stm32_ipcc_tx_irq()
121 	tosr = readl_relaxed(ipcc->reg_proc + IPCC_XTOYSR);  in stm32_ipcc_tx_irq()
122 	mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);  in stm32_ipcc_tx_irq()
127 	for (chan = 0; chan < ipcc->n_chans ; chan++) {  in stm32_ipcc_tx_irq()
134 		stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,  in stm32_ipcc_tx_irq()
137 		mbox_chan_txdone(&ipcc->controller.chans[chan], 0);  in stm32_ipcc_tx_irq()
148 	struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,  in stm32_ipcc_send_data()  local
151 	dev_dbg(ipcc->controller.dev, "%s: chan:%d\n", __func__, chan);  in stm32_ipcc_send_data()
154 	stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR,  in stm32_ipcc_send_data()
158 	stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,  in stm32_ipcc_send_data()
167 	struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,  in stm32_ipcc_startup()  local
171 	ret = clk_prepare_enable(ipcc->clk);  in stm32_ipcc_startup()
173 		dev_err(ipcc->controller.dev, "can not enable the clock\n");  in stm32_ipcc_startup()
178 	stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,  in stm32_ipcc_startup()
187 	struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,  in stm32_ipcc_shutdown()  local
191 	stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,  in stm32_ipcc_shutdown()
194 	clk_disable_unprepare(ipcc->clk);  in stm32_ipcc_shutdown()
207 	struct stm32_ipcc *ipcc;  in stm32_ipcc_probe()  local
220 	ipcc = devm_kzalloc(dev, sizeof(*ipcc), GFP_KERNEL);  in stm32_ipcc_probe()
221 	if (!ipcc)  in stm32_ipcc_probe()
224 	spin_lock_init(&ipcc->lock);  in stm32_ipcc_probe()
227 	if (of_property_read_u32(np, "st,proc-id", &ipcc->proc_id)) {  in stm32_ipcc_probe()
232 	if (ipcc->proc_id >= STM32_MAX_PROCS) {  in stm32_ipcc_probe()
233 		dev_err(dev, "Invalid proc_id (%d)\n", ipcc->proc_id);  in stm32_ipcc_probe()
239 	ipcc->reg_base = devm_ioremap_resource(dev, res);  in stm32_ipcc_probe()
240 	if (IS_ERR(ipcc->reg_base))  in stm32_ipcc_probe()
241 		return PTR_ERR(ipcc->reg_base);  in stm32_ipcc_probe()
243 	ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST;  in stm32_ipcc_probe()
246 	ipcc->clk = devm_clk_get(dev, NULL);  in stm32_ipcc_probe()
247 	if (IS_ERR(ipcc->clk))  in stm32_ipcc_probe()
248 		return PTR_ERR(ipcc->clk);  in stm32_ipcc_probe()
250 	ret = clk_prepare_enable(ipcc->clk);  in stm32_ipcc_probe()
258 		ipcc->irqs[i] = platform_get_irq_byname(pdev, irq_name[i]);  in stm32_ipcc_probe()
259 		if (ipcc->irqs[i] < 0) {  in stm32_ipcc_probe()
260 			if (ipcc->irqs[i] != -EPROBE_DEFER)  in stm32_ipcc_probe()
263 			ret = ipcc->irqs[i];  in stm32_ipcc_probe()
267 		ret = devm_request_threaded_irq(dev, ipcc->irqs[i], NULL,  in stm32_ipcc_probe()
269 						dev_name(dev), ipcc);  in stm32_ipcc_probe()
277 	stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,  in stm32_ipcc_probe()
279 	stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XCR,  in stm32_ipcc_probe()
286 		ret = dev_pm_set_wake_irq(dev, ipcc->irqs[IPCC_IRQ_RX]);  in stm32_ipcc_probe()
294 	ipcc->n_chans = readl_relaxed(ipcc->reg_base + IPCC_HWCFGR);  in stm32_ipcc_probe()
295 	ipcc->n_chans &= IPCFGR_CHAN_MASK;  in stm32_ipcc_probe()
297 	ipcc->controller.dev = dev;  in stm32_ipcc_probe()
298 	ipcc->controller.txdone_irq = true;  in stm32_ipcc_probe()
299 	ipcc->controller.ops = &stm32_ipcc_ops;  in stm32_ipcc_probe()
300 	ipcc->controller.num_chans = ipcc->n_chans;  in stm32_ipcc_probe()
301 	ipcc->controller.chans = devm_kcalloc(dev, ipcc->controller.num_chans,  in stm32_ipcc_probe()
302 					      sizeof(*ipcc->controller.chans),  in stm32_ipcc_probe()
304 	if (!ipcc->controller.chans) {  in stm32_ipcc_probe()
309 	for (i = 0; i < ipcc->controller.num_chans; i++)  in stm32_ipcc_probe()
310 		ipcc->controller.chans[i].con_priv = (void *)i;  in stm32_ipcc_probe()
312 	ret = devm_mbox_controller_register(dev, &ipcc->controller);  in stm32_ipcc_probe()
316 	platform_set_drvdata(pdev, ipcc);  in stm32_ipcc_probe()
318 	ip_ver = readl_relaxed(ipcc->reg_base + IPCC_VER);  in stm32_ipcc_probe()
320 	dev_info(dev, "ipcc rev:%ld.%ld enabled, %d chans, proc %d\n",  in stm32_ipcc_probe()
323 		 ipcc->controller.num_chans, ipcc->proc_id);  in stm32_ipcc_probe()
325 	clk_disable_unprepare(ipcc->clk);  in stm32_ipcc_probe()
334 	clk_disable_unprepare(ipcc->clk);  in stm32_ipcc_probe()
353 	struct stm32_ipcc *ipcc = dev_get_drvdata(dev);  in stm32_ipcc_suspend()  local
355 	ipcc->xmr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);  in stm32_ipcc_suspend()
356 	ipcc->xcr = readl_relaxed(ipcc->reg_proc + IPCC_XCR);  in stm32_ipcc_suspend()
363 	struct stm32_ipcc *ipcc = dev_get_drvdata(dev);  in stm32_ipcc_resume()  local
365 	writel_relaxed(ipcc->xmr, ipcc->reg_proc + IPCC_XMR);  in stm32_ipcc_resume()
366 	writel_relaxed(ipcc->xcr, ipcc->reg_proc + IPCC_XCR);  in stm32_ipcc_resume()
376 	{ .compatible = "st,stm32mp1-ipcc" },
383 		.name = "stm32-ipcc",
395 MODULE_DESCRIPTION("STM32 IPCC driver");