Lines Matching full:hw
103 spinlock_t lock; /* HW access lock */
267 struct inf_hw *hw = dev_id; in diva_irq() local
270 spin_lock(&hw->lock); in diva_irq()
271 val = inb((u32)hw->cfg.start + DIVA_PCI_CTRL); in diva_irq()
273 spin_unlock(&hw->lock); in diva_irq()
276 hw->irqcnt++; in diva_irq()
277 mISDNipac_irq(&hw->ipac, irqloops); in diva_irq()
278 spin_unlock(&hw->lock); in diva_irq()
285 struct inf_hw *hw = dev_id; in diva20x_irq() local
288 spin_lock(&hw->lock); in diva20x_irq()
289 val = readb(hw->cfg.p); in diva20x_irq()
291 spin_unlock(&hw->lock); in diva20x_irq()
294 hw->irqcnt++; in diva20x_irq()
295 mISDNipac_irq(&hw->ipac, irqloops); in diva20x_irq()
296 writeb(PITA_INT0_STATUS, hw->cfg.p); /* ACK PITA INT0 */ in diva20x_irq()
297 spin_unlock(&hw->lock); in diva20x_irq()
304 struct inf_hw *hw = dev_id; in tiger_irq() local
307 spin_lock(&hw->lock); in tiger_irq()
308 val = inb((u32)hw->cfg.start + TIGER_AUX_STATUS); in tiger_irq()
310 spin_unlock(&hw->lock); in tiger_irq()
313 hw->irqcnt++; in tiger_irq()
314 mISDNipac_irq(&hw->ipac, irqloops); in tiger_irq()
315 spin_unlock(&hw->lock); in tiger_irq()
322 struct inf_hw *hw = dev_id; in elsa_irq() local
325 spin_lock(&hw->lock); in elsa_irq()
326 val = inb((u32)hw->cfg.start + ELSA_IRQ_ADDR); in elsa_irq()
328 spin_unlock(&hw->lock); in elsa_irq()
331 hw->irqcnt++; in elsa_irq()
332 mISDNipac_irq(&hw->ipac, irqloops); in elsa_irq()
333 spin_unlock(&hw->lock); in elsa_irq()
340 struct inf_hw *hw = dev_id; in niccy_irq() local
343 spin_lock(&hw->lock); in niccy_irq()
344 val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); in niccy_irq()
346 spin_unlock(&hw->lock); in niccy_irq()
349 outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); in niccy_irq()
350 hw->irqcnt++; in niccy_irq()
351 mISDNipac_irq(&hw->ipac, irqloops); in niccy_irq()
352 spin_unlock(&hw->lock); in niccy_irq()
359 struct inf_hw *hw = dev_id; in gazel_irq() local
362 spin_lock(&hw->lock); in gazel_irq()
363 ret = mISDNipac_irq(&hw->ipac, irqloops); in gazel_irq()
364 spin_unlock(&hw->lock); in gazel_irq()
371 struct inf_hw *hw = dev_id; in ipac_irq() local
374 spin_lock(&hw->lock); in ipac_irq()
375 val = hw->ipac.read_reg(hw, IPAC_ISTA); in ipac_irq()
377 spin_unlock(&hw->lock); in ipac_irq()
380 hw->irqcnt++; in ipac_irq()
381 mISDNipac_irq(&hw->ipac, irqloops); in ipac_irq()
382 spin_unlock(&hw->lock); in ipac_irq()
387 enable_hwirq(struct inf_hw *hw) in enable_hwirq() argument
392 switch (hw->ci->typ) { in enable_hwirq()
395 writel(PITA_INT0_ENABLE, hw->cfg.p); in enable_hwirq()
399 outb(TIGER_IRQ_BIT, (u32)hw->cfg.start + TIGER_AUX_IRQMASK); in enable_hwirq()
402 outb(QS1000_IRQ_ON, (u32)hw->cfg.start + ELSA_IRQ_ADDR); in enable_hwirq()
405 outb(QS3000_IRQ_ON, (u32)hw->cfg.start + ELSA_IRQ_ADDR); in enable_hwirq()
408 val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); in enable_hwirq()
410 outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); in enable_hwirq()
413 w = inw((u32)hw->cfg.start + SCT_PLX_IRQ_ADDR); in enable_hwirq()
415 outw(w, (u32)hw->cfg.start + SCT_PLX_IRQ_ADDR); in enable_hwirq()
419 (u32)hw->cfg.start + GAZEL_INCSR); in enable_hwirq()
423 (u32)hw->cfg.start + GAZEL_INCSR); in enable_hwirq()
431 disable_hwirq(struct inf_hw *hw) in disable_hwirq() argument
436 switch (hw->ci->typ) { in disable_hwirq()
439 writel(0, hw->cfg.p); in disable_hwirq()
443 outb(0, (u32)hw->cfg.start + TIGER_AUX_IRQMASK); in disable_hwirq()
446 outb(QS1000_IRQ_OFF, (u32)hw->cfg.start + ELSA_IRQ_ADDR); in disable_hwirq()
449 outb(QS3000_IRQ_OFF, (u32)hw->cfg.start + ELSA_IRQ_ADDR); in disable_hwirq()
452 val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); in disable_hwirq()
454 outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); in disable_hwirq()
457 w = inw((u32)hw->cfg.start + SCT_PLX_IRQ_ADDR); in disable_hwirq()
459 outw(w, (u32)hw->cfg.start + SCT_PLX_IRQ_ADDR); in disable_hwirq()
463 outb(0, (u32)hw->cfg.start + GAZEL_INCSR); in disable_hwirq()
471 ipac_chip_reset(struct inf_hw *hw) in ipac_chip_reset() argument
473 hw->ipac.write_reg(hw, IPAC_POTA2, 0x20); in ipac_chip_reset()
475 hw->ipac.write_reg(hw, IPAC_POTA2, 0x00); in ipac_chip_reset()
477 hw->ipac.write_reg(hw, IPAC_CONF, hw->ipac.conf); in ipac_chip_reset()
478 hw->ipac.write_reg(hw, IPAC_MASK, 0xc0); in ipac_chip_reset()
482 reset_inf(struct inf_hw *hw) in reset_inf() argument
488 pr_notice("%s: resetting card\n", hw->name); in reset_inf()
489 switch (hw->ci->typ) { in reset_inf()
492 outb(0, (u32)hw->cfg.start + DIVA_PCI_CTRL); in reset_inf()
494 outb(DIVA_RESET_BIT, (u32)hw->cfg.start + DIVA_PCI_CTRL); in reset_inf()
497 outb(9, (u32)hw->cfg.start + 0x69); in reset_inf()
499 (u32)hw->cfg.start + DIVA_PCI_CTRL); in reset_inf()
503 hw->cfg.p + PITA_MISC_REG); in reset_inf()
505 writel(PITA_PARA_MPX_MODE, hw->cfg.p + PITA_MISC_REG); in reset_inf()
510 hw->cfg.p + PITA_MISC_REG); in reset_inf()
513 hw->cfg.p + PITA_MISC_REG); in reset_inf()
518 ipac_chip_reset(hw); in reset_inf()
519 hw->ipac.write_reg(hw, IPAC_ACFG, 0xff); in reset_inf()
520 hw->ipac.write_reg(hw, IPAC_AOE, 0x00); in reset_inf()
521 hw->ipac.write_reg(hw, IPAC_PCFG, 0x12); in reset_inf()
525 ipac_chip_reset(hw); in reset_inf()
526 hw->ipac.write_reg(hw, IPAC_ACFG, 0x00); in reset_inf()
527 hw->ipac.write_reg(hw, IPAC_AOE, 0x3c); in reset_inf()
528 hw->ipac.write_reg(hw, IPAC_ATX, 0xff); in reset_inf()
533 w = inw((u32)hw->cfg.start + SCT_PLX_RESET_ADDR); in reset_inf()
535 outw(w, (u32)hw->cfg.start + SCT_PLX_RESET_ADDR); in reset_inf()
537 w = inw((u32)hw->cfg.start + SCT_PLX_RESET_ADDR); in reset_inf()
539 outw(w, (u32)hw->cfg.start + SCT_PLX_RESET_ADDR); in reset_inf()
543 val = inl((u32)hw->cfg.start + GAZEL_CNTRL); in reset_inf()
545 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); in reset_inf()
548 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); in reset_inf()
550 hw->ipac.isac.adf2 = 0x87; in reset_inf()
551 hw->ipac.hscx[0].slot = 0x1f; in reset_inf()
552 hw->ipac.hscx[1].slot = 0x23; in reset_inf()
555 val = inl((u32)hw->cfg.start + GAZEL_CNTRL); in reset_inf()
557 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); in reset_inf()
560 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); in reset_inf()
562 ipac_chip_reset(hw); in reset_inf()
563 hw->ipac.write_reg(hw, IPAC_ACFG, 0xff); in reset_inf()
564 hw->ipac.write_reg(hw, IPAC_AOE, 0x00); in reset_inf()
565 hw->ipac.conf = 0x01; /* IOM off */ in reset_inf()
570 enable_hwirq(hw); in reset_inf()
574 inf_ctrl(struct inf_hw *hw, u32 cmd, u_long arg) in inf_ctrl() argument
580 reset_inf(hw); in inf_ctrl()
584 hw->name, __func__, cmd, arg); in inf_ctrl()
592 init_irq(struct inf_hw *hw) in init_irq() argument
597 if (!hw->ci->irqfunc) in init_irq()
599 ret = request_irq(hw->irq, hw->ci->irqfunc, IRQF_SHARED, hw->name, hw); in init_irq()
601 pr_info("%s: couldn't get interrupt %d\n", hw->name, hw->irq); in init_irq()
605 spin_lock_irqsave(&hw->lock, flags); in init_irq()
606 reset_inf(hw); in init_irq()
607 ret = hw->ipac.init(&hw->ipac); in init_irq()
609 spin_unlock_irqrestore(&hw->lock, flags); in init_irq()
611 hw->name, ret); in init_irq()
614 spin_unlock_irqrestore(&hw->lock, flags); in init_irq()
617 pr_notice("%s: IRQ %d count %d\n", hw->name, in init_irq()
618 hw->irq, hw->irqcnt); in init_irq()
619 if (!hw->irqcnt) { in init_irq()
621 hw->name, hw->irq, 3 - cnt); in init_irq()
625 free_irq(hw->irq, hw); in init_irq()
630 release_io(struct inf_hw *hw) in release_io() argument
632 if (hw->cfg.mode) { in release_io()
633 if (hw->cfg.p) { in release_io()
634 release_mem_region(hw->cfg.start, hw->cfg.size); in release_io()
635 iounmap(hw->cfg.p); in release_io()
637 release_region(hw->cfg.start, hw->cfg.size); in release_io()
638 hw->cfg.mode = AM_NONE; in release_io()
640 if (hw->addr.mode) { in release_io()
641 if (hw->addr.p) { in release_io()
642 release_mem_region(hw->addr.start, hw->addr.size); in release_io()
643 iounmap(hw->addr.p); in release_io()
645 release_region(hw->addr.start, hw->addr.size); in release_io()
646 hw->addr.mode = AM_NONE; in release_io()
651 setup_io(struct inf_hw *hw) in setup_io() argument
655 if (hw->ci->cfg_mode) { in setup_io()
656 hw->cfg.start = pci_resource_start(hw->pdev, hw->ci->cfg_bar); in setup_io()
657 hw->cfg.size = pci_resource_len(hw->pdev, hw->ci->cfg_bar); in setup_io()
658 if (hw->ci->cfg_mode == AM_MEMIO) { in setup_io()
659 if (!request_mem_region(hw->cfg.start, hw->cfg.size, in setup_io()
660 hw->name)) in setup_io()
663 if (!request_region(hw->cfg.start, hw->cfg.size, in setup_io()
664 hw->name)) in setup_io()
669 "already in use\n", hw->name, in setup_io()
670 (ulong)hw->cfg.start, (ulong)hw->cfg.size); in setup_io()
673 if (hw->ci->cfg_mode == AM_MEMIO) in setup_io()
674 hw->cfg.p = ioremap(hw->cfg.start, hw->cfg.size); in setup_io()
675 hw->cfg.mode = hw->ci->cfg_mode; in setup_io()
678 hw->name, (ulong)hw->cfg.start, in setup_io()
679 (ulong)hw->cfg.size, hw->ci->cfg_mode); in setup_io()
682 if (hw->ci->addr_mode) { in setup_io()
683 hw->addr.start = pci_resource_start(hw->pdev, hw->ci->addr_bar); in setup_io()
684 hw->addr.size = pci_resource_len(hw->pdev, hw->ci->addr_bar); in setup_io()
685 if (hw->ci->addr_mode == AM_MEMIO) { in setup_io()
686 if (!request_mem_region(hw->addr.start, hw->addr.size, in setup_io()
687 hw->name)) in setup_io()
690 if (!request_region(hw->addr.start, hw->addr.size, in setup_io()
691 hw->name)) in setup_io()
696 "already in use\n", hw->name, in setup_io()
697 (ulong)hw->addr.start, (ulong)hw->addr.size); in setup_io()
700 if (hw->ci->addr_mode == AM_MEMIO) { in setup_io()
701 hw->addr.p = ioremap(hw->addr.start, hw->addr.size); in setup_io()
702 if (unlikely(!hw->addr.p)) in setup_io()
705 hw->addr.mode = hw->ci->addr_mode; in setup_io()
708 hw->name, (ulong)hw->addr.start, in setup_io()
709 (ulong)hw->addr.size, hw->ci->addr_mode); in setup_io()
713 switch (hw->ci->typ) { in setup_io()
716 hw->ipac.type = IPAC_TYPE_ISAC | IPAC_TYPE_HSCX; in setup_io()
717 hw->isac.mode = hw->cfg.mode; in setup_io()
718 hw->isac.a.io.ale = (u32)hw->cfg.start + DIVA_ISAC_ALE; in setup_io()
719 hw->isac.a.io.port = (u32)hw->cfg.start + DIVA_ISAC_PORT; in setup_io()
720 hw->hscx.mode = hw->cfg.mode; in setup_io()
721 hw->hscx.a.io.ale = (u32)hw->cfg.start + DIVA_HSCX_ALE; in setup_io()
722 hw->hscx.a.io.port = (u32)hw->cfg.start + DIVA_HSCX_PORT; in setup_io()
725 hw->ipac.type = IPAC_TYPE_IPAC; in setup_io()
726 hw->ipac.isac.off = 0x80; in setup_io()
727 hw->isac.mode = hw->addr.mode; in setup_io()
728 hw->isac.a.p = hw->addr.p; in setup_io()
729 hw->hscx.mode = hw->addr.mode; in setup_io()
730 hw->hscx.a.p = hw->addr.p; in setup_io()
733 hw->ipac.type = IPAC_TYPE_IPACX; in setup_io()
734 hw->isac.mode = hw->addr.mode; in setup_io()
735 hw->isac.a.p = hw->addr.p; in setup_io()
736 hw->hscx.mode = hw->addr.mode; in setup_io()
737 hw->hscx.a.p = hw->addr.p; in setup_io()
741 hw->ipac.type = IPAC_TYPE_IPAC; in setup_io()
742 hw->ipac.isac.off = 0x80; in setup_io()
743 hw->isac.mode = hw->cfg.mode; in setup_io()
744 hw->isac.a.io.ale = (u32)hw->cfg.start + TIGER_IPAC_ALE; in setup_io()
745 hw->isac.a.io.port = (u32)hw->cfg.start + TIGER_IPAC_PORT; in setup_io()
746 hw->hscx.mode = hw->cfg.mode; in setup_io()
747 hw->hscx.a.io.ale = (u32)hw->cfg.start + TIGER_IPAC_ALE; in setup_io()
748 hw->hscx.a.io.port = (u32)hw->cfg.start + TIGER_IPAC_PORT; in setup_io()
749 outb(0xff, (ulong)hw->cfg.start); in setup_io()
751 outb(0x00, (ulong)hw->cfg.start); in setup_io()
753 outb(TIGER_IOMASK, (ulong)hw->cfg.start + TIGER_AUX_CTRL); in setup_io()
757 hw->ipac.type = IPAC_TYPE_IPAC; in setup_io()
758 hw->ipac.isac.off = 0x80; in setup_io()
759 hw->isac.a.io.ale = (u32)hw->addr.start; in setup_io()
760 hw->isac.a.io.port = (u32)hw->addr.start + 1; in setup_io()
761 hw->isac.mode = hw->addr.mode; in setup_io()
762 hw->hscx.a.io.ale = (u32)hw->addr.start; in setup_io()
763 hw->hscx.a.io.port = (u32)hw->addr.start + 1; in setup_io()
764 hw->hscx.mode = hw->addr.mode; in setup_io()
767 hw->ipac.type = IPAC_TYPE_ISAC | IPAC_TYPE_HSCX; in setup_io()
768 hw->isac.mode = hw->addr.mode; in setup_io()
769 hw->isac.a.io.ale = (u32)hw->addr.start + NICCY_ISAC_ALE; in setup_io()
770 hw->isac.a.io.port = (u32)hw->addr.start + NICCY_ISAC_PORT; in setup_io()
771 hw->hscx.mode = hw->addr.mode; in setup_io()
772 hw->hscx.a.io.ale = (u32)hw->addr.start + NICCY_HSCX_ALE; in setup_io()
773 hw->hscx.a.io.port = (u32)hw->addr.start + NICCY_HSCX_PORT; in setup_io()
776 hw->ipac.type = IPAC_TYPE_IPAC; in setup_io()
777 hw->ipac.isac.off = 0x80; in setup_io()
778 hw->isac.a.io.ale = (u32)hw->addr.start; in setup_io()
779 hw->isac.a.io.port = hw->isac.a.io.ale + 4; in setup_io()
780 hw->isac.mode = hw->addr.mode; in setup_io()
781 hw->hscx.a.io.ale = hw->isac.a.io.ale; in setup_io()
782 hw->hscx.a.io.port = hw->isac.a.io.port; in setup_io()
783 hw->hscx.mode = hw->addr.mode; in setup_io()
786 hw->ipac.type = IPAC_TYPE_IPAC; in setup_io()
787 hw->ipac.isac.off = 0x80; in setup_io()
788 hw->isac.a.io.ale = (u32)hw->addr.start + 0x08; in setup_io()
789 hw->isac.a.io.port = hw->isac.a.io.ale + 4; in setup_io()
790 hw->isac.mode = hw->addr.mode; in setup_io()
791 hw->hscx.a.io.ale = hw->isac.a.io.ale; in setup_io()
792 hw->hscx.a.io.port = hw->isac.a.io.port; in setup_io()
793 hw->hscx.mode = hw->addr.mode; in setup_io()
796 hw->ipac.type = IPAC_TYPE_IPAC; in setup_io()
797 hw->ipac.isac.off = 0x80; in setup_io()
798 hw->isac.a.io.ale = (u32)hw->addr.start + 0x10; in setup_io()
799 hw->isac.a.io.port = hw->isac.a.io.ale + 4; in setup_io()
800 hw->isac.mode = hw->addr.mode; in setup_io()
801 hw->hscx.a.io.ale = hw->isac.a.io.ale; in setup_io()
802 hw->hscx.a.io.port = hw->isac.a.io.port; in setup_io()
803 hw->hscx.mode = hw->addr.mode; in setup_io()
806 hw->ipac.type = IPAC_TYPE_IPAC; in setup_io()
807 hw->ipac.isac.off = 0x80; in setup_io()
808 hw->isac.a.io.ale = (u32)hw->addr.start + 0x20; in setup_io()
809 hw->isac.a.io.port = hw->isac.a.io.ale + 4; in setup_io()
810 hw->isac.mode = hw->addr.mode; in setup_io()
811 hw->hscx.a.io.ale = hw->isac.a.io.ale; in setup_io()
812 hw->hscx.a.io.port = hw->isac.a.io.port; in setup_io()
813 hw->hscx.mode = hw->addr.mode; in setup_io()
816 hw->ipac.type = IPAC_TYPE_ISAC | IPAC_TYPE_HSCX; in setup_io()
817 hw->ipac.isac.off = 0x80; in setup_io()
818 hw->isac.mode = hw->addr.mode; in setup_io()
819 hw->isac.a.io.port = (u32)hw->addr.start; in setup_io()
820 hw->hscx.mode = hw->addr.mode; in setup_io()
821 hw->hscx.a.io.port = hw->isac.a.io.port; in setup_io()
824 hw->ipac.type = IPAC_TYPE_IPAC; in setup_io()
825 hw->ipac.isac.off = 0x80; in setup_io()
826 hw->isac.mode = hw->addr.mode; in setup_io()
827 hw->isac.a.io.ale = (u32)hw->addr.start; in setup_io()
828 hw->isac.a.io.port = (u32)hw->addr.start + GAZEL_IPAC_DATA_PORT; in setup_io()
829 hw->hscx.mode = hw->addr.mode; in setup_io()
830 hw->hscx.a.io.ale = hw->isac.a.io.ale; in setup_io()
831 hw->hscx.a.io.port = hw->isac.a.io.port; in setup_io()
836 switch (hw->isac.mode) { in setup_io()
838 ASSIGN_FUNC_IPAC(MIO, hw->ipac); in setup_io()
841 ASSIGN_FUNC_IPAC(IND, hw->ipac); in setup_io()
844 ASSIGN_FUNC_IPAC(IO, hw->ipac); in setup_io()