6  * Maxime Ripard <maxime.ripard@free-electrons.com>
31 #define SUN4I_IRQ_ENABLE_REG(data, x)	((data)->enable_reg_offset + 0x4 * x)
32 #define SUN4I_IRQ_MASK_REG(data, x)	((data)->mask_reg_offset + 0x4 * x)
56 	writel(BIT(0), irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0));  in sun4i_irq_ack()
66 	val = readl(irq_ic_data->irq_base +  in sun4i_irq_mask()
69 	       irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg));  in sun4i_irq_mask()
79 	val = readl(irq_ic_data->irq_base +  in sun4i_irq_unmask()
82 	       irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg));  in sun4i_irq_unmask()
110 	irq_ic_data->irq_base = of_iomap(node, 0);  in sun4i_of_init()
111 	if (!irq_ic_data->irq_base)  in sun4i_of_init()
112 		panic("%pOF: unable to map IC registers\n",  in sun4i_of_init()
116 	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 0));  in sun4i_of_init()
117 	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 1));  in sun4i_of_init()
118 	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 2));  in sun4i_of_init()
121 	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 0));  in sun4i_of_init()
122 	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 1));  in sun4i_of_init()
123 	writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 2));  in sun4i_of_init()
126 	writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0));  in sun4i_of_init()
127 	writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(1));  in sun4i_of_init()
128 	writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(2));  in sun4i_of_init()
131 	writel(0x01, irq_ic_data->irq_base + SUN4I_IRQ_PROTECTION_REG);  in sun4i_of_init()
134 	writel(0x00, irq_ic_data->irq_base + SUN4I_IRQ_NMI_CTRL_REG);  in sun4i_of_init()
136 	irq_ic_data->irq_domain = irq_domain_add_linear(node, 3 * 32,  in sun4i_of_init()
138 	if (!irq_ic_data->irq_domain)  in sun4i_of_init()
152 		return -ENOMEM;  in sun4i_ic_of_init()
155 	irq_ic_data->enable_reg_offset = SUN4I_IRQ_ENABLE_REG_OFFSET;  in sun4i_ic_of_init()
156 	irq_ic_data->mask_reg_offset = SUN4I_IRQ_MASK_REG_OFFSET;  in sun4i_ic_of_init()
161 IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_ic_of_init);
169 		return -ENOMEM;  in suniv_ic_of_init()
172 	irq_ic_data->enable_reg_offset = SUNIV_IRQ_ENABLE_REG_OFFSET;  in suniv_ic_of_init()
173 	irq_ic_data->mask_reg_offset = SUNIV_IRQ_MASK_REG_OFFSET;  in suniv_ic_of_init()
178 IRQCHIP_DECLARE(allwinner_sunvi_ic, "allwinner,suniv-f1c100s-ic",
190 	 * So if we immediately get a reading of 0, check the irq-pending reg  in sun4i_handle_irq()
193 	 * read the vector-reg once.  in sun4i_handle_irq()
195 	hwirq = readl(irq_ic_data->irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;  in sun4i_handle_irq()
197 		  !(readl(irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0)) &  in sun4i_handle_irq()
202 		handle_domain_irq(irq_ic_data->irq_domain, hwirq, regs);  in sun4i_handle_irq()
203 		hwirq = readl(irq_ic_data->irq_base +  in sun4i_handle_irq()