1 // SPDX-License-Identifier: GPL-2.0
4  * Copyright (C) 2017-2018 SiFive
8 #define pr_fmt(fmt) "riscv-intc: " fmt
11 #include <linux/cpu.h>
24 	unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;  in riscv_intc_irq()
34 		 * non-SMP system gets one, then we don't know what to do.  in riscv_intc_irq()
46  * On RISC-V systems local interrupts are masked or unmasked by writing
54 	csr_clear(CSR_IE, BIT(d->hwirq));  in riscv_intc_irq_mask()
59 	csr_set(CSR_IE, BIT(d->hwirq));  in riscv_intc_irq_unmask()
62 static int riscv_intc_cpu_starting(unsigned int cpu)  in riscv_intc_cpu_starting()  argument
68 static int riscv_intc_cpu_dying(unsigned int cpu)  in riscv_intc_cpu_dying()  argument
75 	.name = "RISC-V INTC",
84 	irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data,  in riscv_intc_domain_map()
107 	 * The DT will have one INTC DT node under each CPU (or HART)  in riscv_intc_init()
109 	 * for each INTC DT node. We only need to do INTC initialization  in riscv_intc_init()
110 	 * for the INTC DT node belonging to boot CPU (or boot HART).  in riscv_intc_init()
119 		return -ENXIO;  in riscv_intc_init()
129 			  "irqchip/riscv/intc:starting",  in riscv_intc_init()
138 IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);