28 #define PJ1_INT_SEL		0x10c
29 #define PJ4_INT_SEL		0x104
33 #define SEL_INT_NUM_MASK	0x3f
75 	if (data == &icu_data[0]) {  in icu_mask_ack_irq()
99 	if (data == &icu_data[0]) {  in icu_mask_irq()
128 	if (data == &icu_data[0]) {  in icu_unmask_irq()
172 		if (status == 0)  in icu_mux_irq_demux()
187 	return 0;  in mmp_irq_domain_map()
195 	*out_hwirq = intspec[0];  in mmp_irq_domain_xlate()
196 	return 0;  in mmp_irq_domain_xlate()
205 	.conf_enable	= 0x51,
206 	.conf_disable	= 0x0,
207 	.conf_mask	= 0x7f,
211 	.conf_enable	= 0x20,
212 	.conf_disable	= 0x0,
218 	.conf_enable	= 0x20,
219 	.conf_disable	= 0x0,
222 	.conf2_mask	= 0xf0,
233 	handle_domain_irq(icu_data[0].domain, hwirq, regs);  in mmp_handle_irq()
244 	handle_domain_irq(icu_data[0].domain, hwirq, regs);  in mmp2_handle_irq()
253 	mmp_icu_base = ioremap(0xd4282000, 0x1000);  in icu_init_irq()
254 	icu_data[0].conf_enable = mmp_conf.conf_enable;  in icu_init_irq()
255 	icu_data[0].conf_disable = mmp_conf.conf_disable;  in icu_init_irq()
256 	icu_data[0].conf_mask = mmp_conf.conf_mask;  in icu_init_irq()
257 	icu_data[0].nr_irqs = 64;  in icu_init_irq()
258 	icu_data[0].virq_base = 0;  in icu_init_irq()
259 	icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,  in icu_init_irq()
261 						   &icu_data[0]);  in icu_init_irq()
262 	for (irq = 0; irq < 64; irq++) {  in icu_init_irq()
266 	irq_set_default_host(icu_data[0].domain);  in icu_init_irq()
276 	mmp_icu_base = ioremap(0xd4282000, 0x1000);  in mmp2_init_icu()
277 	icu_data[0].conf_enable = mmp2_conf.conf_enable;  in mmp2_init_icu()
278 	icu_data[0].conf_disable = mmp2_conf.conf_disable;  in mmp2_init_icu()
279 	icu_data[0].conf_mask = mmp2_conf.conf_mask;  in mmp2_init_icu()
280 	icu_data[0].nr_irqs = 64;  in mmp2_init_icu()
281 	icu_data[0].virq_base = 0;  in mmp2_init_icu()
282 	icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,  in mmp2_init_icu()
284 						   &icu_data[0]);  in mmp2_init_icu()
285 	icu_data[1].reg_status = mmp_icu_base + 0x150;  in mmp2_init_icu()
286 	icu_data[1].reg_mask = mmp_icu_base + 0x168;  in mmp2_init_icu()
287 	icu_data[1].clr_mfp_irq_base = icu_data[0].virq_base +  in mmp2_init_icu()
288 				icu_data[0].nr_irqs;  in mmp2_init_icu()
292 	icu_data[1].virq_base = icu_data[0].virq_base + icu_data[0].nr_irqs;  in mmp2_init_icu()
294 						   icu_data[1].virq_base, 0,  in mmp2_init_icu()
297 	icu_data[2].reg_status = mmp_icu_base + 0x154;  in mmp2_init_icu()
298 	icu_data[2].reg_mask = mmp_icu_base + 0x16c;  in mmp2_init_icu()
303 						   icu_data[2].virq_base, 0,  in mmp2_init_icu()
306 	icu_data[3].reg_status = mmp_icu_base + 0x180;  in mmp2_init_icu()
307 	icu_data[3].reg_mask = mmp_icu_base + 0x17c;  in mmp2_init_icu()
312 						   icu_data[3].virq_base, 0,  in mmp2_init_icu()
315 	icu_data[4].reg_status = mmp_icu_base + 0x158;  in mmp2_init_icu()
316 	icu_data[4].reg_mask = mmp_icu_base + 0x170;  in mmp2_init_icu()
321 						   icu_data[4].virq_base, 0,  in mmp2_init_icu()
324 	icu_data[5].reg_status = mmp_icu_base + 0x15c;  in mmp2_init_icu()
325 	icu_data[5].reg_mask = mmp_icu_base + 0x174;  in mmp2_init_icu()
330 						   icu_data[5].virq_base, 0,  in mmp2_init_icu()
333 	icu_data[6].reg_status = mmp_icu_base + 0x160;  in mmp2_init_icu()
334 	icu_data[6].reg_mask = mmp_icu_base + 0x178;  in mmp2_init_icu()
339 						   icu_data[6].virq_base, 0,  in mmp2_init_icu()
342 	icu_data[7].reg_status = mmp_icu_base + 0x188;  in mmp2_init_icu()
343 	icu_data[7].reg_mask = mmp_icu_base + 0x184;  in mmp2_init_icu()
348 						   icu_data[7].virq_base, 0,  in mmp2_init_icu()
352 	for (irq = 0; irq < end; irq++) {  in mmp2_init_icu()
368 	irq_set_default_host(icu_data[0].domain);  in mmp2_init_icu()
375 	int ret, nr_irqs, irq, i = 0;  in mmp_init_bases()
383 	mmp_icu_base = of_iomap(node, 0);  in mmp_init_bases()
389 	icu_data[0].virq_base = 0;  in mmp_init_bases()
390 	icu_data[0].domain = irq_domain_add_linear(node, nr_irqs,  in mmp_init_bases()
392 						   &icu_data[0]);  in mmp_init_bases()
393 	for (irq = 0; irq < nr_irqs; irq++) {  in mmp_init_bases()
394 		ret = irq_create_mapping(icu_data[0].domain, irq);  in mmp_init_bases()
400 			icu_data[0].virq_base = ret;  in mmp_init_bases()
402 	icu_data[0].nr_irqs = nr_irqs;  in mmp_init_bases()
403 	return 0;  in mmp_init_bases()
405 	if (icu_data[0].virq_base) {  in mmp_init_bases()
406 		for (i = 0; i < irq; i++)  in mmp_init_bases()
407 			irq_dispose_mapping(icu_data[0].virq_base + i);  in mmp_init_bases()
409 	irq_domain_remove(icu_data[0].domain);  in mmp_init_bases()
420 	if (ret < 0)  in mmp_of_init()
423 	icu_data[0].conf_enable = mmp_conf.conf_enable;  in mmp_of_init()
424 	icu_data[0].conf_disable = mmp_conf.conf_disable;  in mmp_of_init()
425 	icu_data[0].conf_mask = mmp_conf.conf_mask;  in mmp_of_init()
428 	return 0;  in mmp_of_init()
438 	if (ret < 0)  in mmp2_of_init()
441 	icu_data[0].conf_enable = mmp2_conf.conf_enable;  in mmp2_of_init()
442 	icu_data[0].conf_disable = mmp2_conf.conf_disable;  in mmp2_of_init()
443 	icu_data[0].conf_mask = mmp2_conf.conf_mask;  in mmp2_of_init()
446 	return 0;  in mmp2_of_init()
462 	if (ret < 0) {  in mmp3_of_init()
467 	icu_data[0].conf_enable = mmp3_conf.conf_enable;  in mmp3_of_init()
468 	icu_data[0].conf_disable = mmp3_conf.conf_disable;  in mmp3_of_init()
469 	icu_data[0].conf_mask = mmp3_conf.conf_mask;  in mmp3_of_init()
470 	icu_data[0].conf2_mask = mmp3_conf.conf2_mask;  in mmp3_of_init()
478 	return 0;  in mmp3_of_init()
485 	int i, ret, irq, j = 0;  in mmp2_mux_of_init()
509 	if (ret < 0) {  in mmp2_mux_of_init()
513 	icu_data[i].reg_status = mmp_icu_base + reg[0];  in mmp2_mux_of_init()
515 	icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);  in mmp2_mux_of_init()
519 	icu_data[i].virq_base = 0;  in mmp2_mux_of_init()
523 	for (irq = 0; irq < nr_irqs; irq++) {  in mmp2_mux_of_init()
541 	return 0;  in mmp2_mux_of_init()
544 		for (j = 0; j < irq; j++)  in mmp2_mux_of_init()