1 // SPDX-License-Identifier: GPL-2.0
53 	struct irq_chip_generic *gc = handler->priv->gc;  in liointc_chained_handle_irq()
58 	pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS);  in liointc_chained_handle_irq()
62 		if (handler->priv->has_lpc_irq_errata &&  in liointc_chained_handle_irq()
63 			(handler->parent_int_map & gc->mask_cache &  in liointc_chained_handle_irq()
73 		generic_handle_irq(irq_find_mapping(gc->domain, bit));  in liointc_chained_handle_irq()
85 		writel(readl(gc->reg_base + offset) | mask,  in liointc_set_bit()
86 				gc->reg_base + offset);  in liointc_set_bit()
88 		writel(readl(gc->reg_base + offset) & ~mask,  in liointc_set_bit()
89 				gc->reg_base + offset);  in liointc_set_bit()
95 	u32 mask = data->mask;  in liointc_set_type()
118 		return -EINVAL;  in liointc_set_type()
128 	struct liointc_priv *priv = gc->private;  in liointc_resume()
134 	writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE);  in liointc_resume()
137 		writeb(priv->map_cache[i], gc->reg_base + i);  in liointc_resume()
139 	writel(gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);  in liointc_resume()
160 		return -ENOMEM;  in liointc_of_init()
164 		err = -ENODEV;  in liointc_of_init()
174 		err = -ENODEV;  in liointc_of_init()
184 		pr_err("loongson-liointc: No parent_int_map\n");  in liointc_of_init()
185 		err = -ENODEV;  in liointc_of_init()
190 		priv->handler[i].parent_int_map = of_parent_int_map[i];  in liointc_of_init()
196 		pr_err("loongson-liointc: cannot add IRQ domain\n");  in liointc_of_init()
197 		err = -EINVAL;  in liointc_of_init()
201 	err = irq_alloc_domain_generic_chips(domain, 32, 1,  in liointc_of_init()
202 					node->full_name, handle_level_irq,  in liointc_of_init()
205 		pr_err("loongson-liointc: unable to register IRQ domain\n");  in liointc_of_init()
217 		u32 pending = priv->handler[i].parent_int_map;  in liointc_of_init()
222 			priv->map_cache[bit] = BIT(i) << LIOINTC_SHIFT_INTx;  in liointc_of_init()
229 		priv->map_cache[i] |= BIT(loongson_sysconf.boot_cpu_id);  in liointc_of_init()
230 		writeb(priv->map_cache[i], base + i);  in liointc_of_init()
234 	gc->private = priv;  in liointc_of_init()
235 	gc->reg_base = base;  in liointc_of_init()
236 	gc->domain = domain;  in liointc_of_init()
237 	gc->resume = liointc_resume;  in liointc_of_init()
239 	ct = gc->chip_types;  in liointc_of_init()
240 	ct->regs.enable = LIOINTC_REG_INTC_ENABLE;  in liointc_of_init()
241 	ct->regs.disable = LIOINTC_REG_INTC_DISABLE;  in liointc_of_init()
242 	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;  in liointc_of_init()
243 	ct->chip.irq_mask = irq_gc_mask_disable_reg;  in liointc_of_init()
244 	ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;  in liointc_of_init()
245 	ct->chip.irq_set_type = liointc_set_type;  in liointc_of_init()
247 	gc->mask_cache = 0;  in liointc_of_init()
248 	priv->gc = gc;  in liointc_of_init()
254 		priv->handler[i].priv = priv;  in liointc_of_init()
256 				liointc_chained_handle_irq, &priv->handler[i]);  in liointc_of_init()
271 IRQCHIP_DECLARE(loongson_liointc_1_0, "loongson,liointc-1.0", liointc_of_init);
272 IRQCHIP_DECLARE(loongson_liointc_1_0a, "loongson,liointc-1.0a", liointc_of_init);