1 // SPDX-License-Identifier: GPL-2.0
3  * irqchip for the IXP4xx interrupt controller
6  * Based on arch/arm/mach-ixp4xx/common.c
8  * Copyright 2003-2004 (C) MontaVista, Software, Inc.
16 #include <linux/irqchip/irq-ixp4xx.h>
27 #define IXP4XX_ICPR	0x00 /* Interrupt Status */
28 #define IXP4XX_ICMR	0x04 /* Interrupt Enable */
29 #define IXP4XX_ICLR	0x08 /* Interrupt IRQ/FIQ Select */
32 #define IXP4XX_ICHR	0x14 /* Interrupt Priority */
36 /* IXP43x and IXP46x-only */
37 #define	IXP4XX_ICPR2	0x20 /* Interrupt Status 2 */
38 #define	IXP4XX_ICMR2	0x24 /* Interrupt Enable 2 */
39 #define	IXP4XX_ICLR2	0x28 /* Interrupt IRQ/FIQ Select 2 */
45  * struct ixp4xx_irq - state container for the Faraday IRQ controller
47  * @is_356: if this is an IXP43x, IXP45x or IX46x SoC (with 64 IRQs)
69 		return -EINVAL;  in ixp4xx_set_irq_type()
78 	if (ixi->is_356 && d->hwirq >= 32) {  in ixp4xx_irq_mask()
79 		val = __raw_readl(ixi->irqbase + IXP4XX_ICMR2);  in ixp4xx_irq_mask()
80 		val &= ~BIT(d->hwirq - 32);  in ixp4xx_irq_mask()
81 		__raw_writel(val, ixi->irqbase + IXP4XX_ICMR2);  in ixp4xx_irq_mask()
83 		val = __raw_readl(ixi->irqbase + IXP4XX_ICMR);  in ixp4xx_irq_mask()
84 		val &= ~BIT(d->hwirq);  in ixp4xx_irq_mask()
85 		__raw_writel(val, ixi->irqbase + IXP4XX_ICMR);  in ixp4xx_irq_mask()
91  * interrupt condition disappears.
98 	if (ixi->is_356 && d->hwirq >= 32) {  in ixp4xx_irq_unmask()
99 		val = __raw_readl(ixi->irqbase + IXP4XX_ICMR2);  in ixp4xx_irq_unmask()
100 		val |= BIT(d->hwirq - 32);  in ixp4xx_irq_unmask()
101 		__raw_writel(val, ixi->irqbase + IXP4XX_ICMR2);  in ixp4xx_irq_unmask()
103 		val = __raw_readl(ixi->irqbase + IXP4XX_ICMR);  in ixp4xx_irq_unmask()
104 		val |= BIT(d->hwirq);  in ixp4xx_irq_unmask()
105 		__raw_writel(val, ixi->irqbase + IXP4XX_ICMR);  in ixp4xx_irq_unmask()
115 	status = __raw_readl(ixi->irqbase + IXP4XX_ICIP);  in ixp4xx_handle_irq()
117 		handle_domain_irq(ixi->domain, i, regs);  in ixp4xx_handle_irq()
122 	if (ixi->is_356) {  in ixp4xx_handle_irq()
123 		status = __raw_readl(ixi->irqbase + IXP4XX_ICIP2);  in ixp4xx_handle_irq()
125 			handle_domain_irq(ixi->domain, i + 32, regs);  in ixp4xx_handle_irq()
135 	if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) {  in ixp4xx_irq_domain_translate()
136 		*hwirq = fwspec->param[0];  in ixp4xx_irq_domain_translate()
137 		*type = fwspec->param[1];  in ixp4xx_irq_domain_translate()
141 	if (is_fwnode_irqchip(fwspec->fwnode)) {  in ixp4xx_irq_domain_translate()
142 		if (fwspec->param_count != 2)  in ixp4xx_irq_domain_translate()
143 			return -EINVAL;  in ixp4xx_irq_domain_translate()
144 		*hwirq = fwspec->param[0];  in ixp4xx_irq_domain_translate()
145 		*type = fwspec->param[1];  in ixp4xx_irq_domain_translate()
150 	return -EINVAL;  in ixp4xx_irq_domain_translate()
157 	struct ixp4xx_irq *ixi = d->host_data;  in ixp4xx_irq_domain_alloc()
178 				    &ixi->irqchip,  in ixp4xx_irq_domain_alloc()
199  * ixp4xx_get_irq_domain() - retrieve the ixp4xx irq domain
207 	return ixi->domain;  in ixp4xx_get_irq_domain()
216  * the GPIO driver using . This is a step-gap solution.
249  * ixp4x_irq_setup() - Common setup code for the IXP4xx interrupt controller
251  * @irqbase: Virtual memory base for the interrupt controller
253  * @is_356: if this is an IXP43x, IXP45x or IXP46x SoC variant
262 	ixi->irqbase = irqbase;  in ixp4xx_irq_setup()
263 	ixi->is_356 = is_356;  in ixp4xx_irq_setup()
266 	__raw_writel(0x0, ixi->irqbase + IXP4XX_ICLR);  in ixp4xx_irq_setup()
269 	__raw_writel(0x0, ixi->irqbase + IXP4XX_ICMR);  in ixp4xx_irq_setup()
273 		__raw_writel(0x0, ixi->irqbase + IXP4XX_ICLR2);  in ixp4xx_irq_setup()
276 		__raw_writel(0x0, ixi->irqbase + IXP4XX_ICMR2);  in ixp4xx_irq_setup()
283 	ixi->irqchip.name = "IXP4xx";  in ixp4xx_irq_setup()
284 	ixi->irqchip.irq_mask = ixp4xx_irq_mask;  in ixp4xx_irq_setup()
285 	ixi->irqchip.irq_unmask	= ixp4xx_irq_unmask;  in ixp4xx_irq_setup()
286 	ixi->irqchip.irq_set_type = ixp4xx_set_irq_type;  in ixp4xx_irq_setup()
288 	ixi->domain = irq_domain_create_linear(fwnode, nr_irqs,  in ixp4xx_irq_setup()
291 	if (!ixi->domain) {  in ixp4xx_irq_setup()
293 		return -ENODEV;  in ixp4xx_irq_setup()
302  * ixp4xx_irq_init() - Function to initialize the irqchip from boardfiles
304  * @is_356: if this is an IXP43x, IXP45x or IXP46x SoC variant
319 		pr_crit("IXP4XX: could not ioremap interrupt controller\n");  in ixp4xx_irq_init()
335 		nr_chunks--;  in ixp4xx_irq_init()
345 			chunk->irq, chunk->irq + chunk->nr_irqs - 1,  in ixp4xx_irq_init()
346 			chunk->hwirq, chunk->hwirq + chunk->nr_irqs - 1);  in ixp4xx_irq_init()
348 		fwspec.param[0] = chunk->hwirq;  in ixp4xx_irq_init()
351 		ret = __irq_domain_alloc_irqs(ixi->domain,  in ixp4xx_irq_init()
352 					      chunk->irq,  in ixp4xx_irq_init()
353 					      chunk->nr_irqs,  in ixp4xx_irq_init()
379 		pr_crit("IXP4XX: could not ioremap interrupt controller\n");  in ixp4xx_of_init_irq()
380 		return -ENODEV;  in ixp4xx_of_init_irq()
385 	is_356 = of_device_is_compatible(np, "intel,ixp43x-interrupt") ||  in ixp4xx_of_init_irq()
386 		of_device_is_compatible(np, "intel,ixp45x-interrupt") ||  in ixp4xx_of_init_irq()
387 		of_device_is_compatible(np, "intel,ixp46x-interrupt");  in ixp4xx_of_init_irq()
395 IRQCHIP_DECLARE(ixp42x, "intel,ixp42x-interrupt",
397 IRQCHIP_DECLARE(ixp43x, "intel,ixp43x-interrupt",
399 IRQCHIP_DECLARE(ixp45x, "intel,ixp45x-interrupt",
401 IRQCHIP_DECLARE(ixp46x, "intel,ixp46x-interrupt",