Lines Matching +full:m +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/intel-iommu.h>
110 static int iommu_regset_show(struct seq_file *m, void *unused) in iommu_regset_show() argument
120 if (!drhd->reg_base_addr) { in iommu_regset_show()
121 seq_puts(m, "IOMMU: Invalid base address\n"); in iommu_regset_show()
122 ret = -EINVAL; in iommu_regset_show()
126 seq_printf(m, "IOMMU: %s Register Base Address: %llx\n", in iommu_regset_show()
127 iommu->name, drhd->reg_base_addr); in iommu_regset_show()
128 seq_puts(m, "Name\t\t\tOffset\t\tContents\n"); in iommu_regset_show()
130 * Publish the contents of the 64-bit hardware registers in iommu_regset_show()
133 raw_spin_lock_irqsave(&iommu->register_lock, flag); in iommu_regset_show()
135 value = dmar_readl(iommu->reg + iommu_regs_32[i].offset); in iommu_regset_show()
136 seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n", in iommu_regset_show()
141 value = dmar_readq(iommu->reg + iommu_regs_64[i].offset); in iommu_regset_show()
142 seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n", in iommu_regset_show()
146 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in iommu_regset_show()
147 seq_putc(m, '\n'); in iommu_regset_show()
156 static inline void print_tbl_walk(struct seq_file *m) in print_tbl_walk() argument
158 struct tbl_walk *tbl_wlk = m->private; in print_tbl_walk()
160 seq_printf(m, "%02x:%02x.%x\t0x%016llx:0x%016llx\t0x%016llx:0x%016llx\t", in print_tbl_walk()
161 tbl_wlk->bus, PCI_SLOT(tbl_wlk->devfn), in print_tbl_walk()
162 PCI_FUNC(tbl_wlk->devfn), tbl_wlk->rt_entry->hi, in print_tbl_walk()
163 tbl_wlk->rt_entry->lo, tbl_wlk->ctx_entry->hi, in print_tbl_walk()
164 tbl_wlk->ctx_entry->lo); in print_tbl_walk()
167 * A legacy mode DMAR doesn't support PASID, hence default it to -1 in print_tbl_walk()
171 if (!tbl_wlk->pasid_tbl_entry) in print_tbl_walk()
172 seq_printf(m, "%-6d\t0x%016llx:0x%016llx:0x%016llx\n", -1, in print_tbl_walk()
175 seq_printf(m, "%-6d\t0x%016llx:0x%016llx:0x%016llx\n", in print_tbl_walk()
176 tbl_wlk->pasid, tbl_wlk->pasid_tbl_entry->val[2], in print_tbl_walk()
177 tbl_wlk->pasid_tbl_entry->val[1], in print_tbl_walk()
178 tbl_wlk->pasid_tbl_entry->val[0]); in print_tbl_walk()
181 static void pasid_tbl_walk(struct seq_file *m, struct pasid_entry *tbl_entry, in pasid_tbl_walk() argument
184 struct tbl_walk *tbl_wlk = m->private; in pasid_tbl_walk()
189 tbl_wlk->pasid_tbl_entry = tbl_entry; in pasid_tbl_walk()
190 tbl_wlk->pasid = (dir_idx << PASID_PDE_SHIFT) + tbl_idx; in pasid_tbl_walk()
191 print_tbl_walk(m); in pasid_tbl_walk()
198 static void pasid_dir_walk(struct seq_file *m, u64 pasid_dir_ptr, in pasid_dir_walk() argument
208 pasid_tbl_walk(m, pasid_tbl, dir_idx); in pasid_dir_walk()
214 static void ctx_tbl_walk(struct seq_file *m, struct intel_iommu *iommu, u16 bus) in ctx_tbl_walk() argument
224 * Scalable mode root entry points to upper scalable mode in ctx_tbl_walk()
225 * context table and lower scalable mode context table. Each in ctx_tbl_walk()
226 * scalable mode context table has 128 context entries where as in ctx_tbl_walk()
227 * legacy mode context table has 256 context entries. So in in ctx_tbl_walk()
228 * scalable mode, the context entries for former 128 devices are in ctx_tbl_walk()
229 * in the lower scalable mode context table, while the latter in ctx_tbl_walk()
230 * 128 devices are in the upper scalable mode context table. in ctx_tbl_walk()
231 * In scalable mode, when devfn > 127, iommu_context_addr() in ctx_tbl_walk()
232 * automatically refers to upper scalable mode context table and in ctx_tbl_walk()
234 * between scalable mode and non scalable mode. in ctx_tbl_walk()
245 tbl_wlk.rt_entry = &iommu->root_entry[bus]; in ctx_tbl_walk()
247 m->private = &tbl_wlk; in ctx_tbl_walk()
249 if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) { in ctx_tbl_walk()
250 pasid_dir_ptr = context->lo & VTD_PAGE_MASK; in ctx_tbl_walk()
252 pasid_dir_walk(m, pasid_dir_ptr, pasid_dir_size); in ctx_tbl_walk()
256 print_tbl_walk(m); in ctx_tbl_walk()
260 static void root_tbl_walk(struct seq_file *m, struct intel_iommu *iommu) in root_tbl_walk() argument
265 spin_lock_irqsave(&iommu->lock, flags); in root_tbl_walk()
266 seq_printf(m, "IOMMU %s: Root Table Address: 0x%llx\n", iommu->name, in root_tbl_walk()
267 (u64)virt_to_phys(iommu->root_entry)); in root_tbl_walk()
268 seq_puts(m, "B.D.F\tRoot_entry\t\t\t\tContext_entry\t\t\t\tPASID\tPASID_table_entry\n"); in root_tbl_walk()
276 ctx_tbl_walk(m, iommu, bus); in root_tbl_walk()
278 spin_unlock_irqrestore(&iommu->lock, flags); in root_tbl_walk()
281 static int dmar_translation_struct_show(struct seq_file *m, void *unused) in dmar_translation_struct_show() argument
289 sts = dmar_readl(iommu->reg + DMAR_GSTS_REG); in dmar_translation_struct_show()
291 seq_printf(m, "DMA Remapping is not enabled on %s\n", in dmar_translation_struct_show()
292 iommu->name); in dmar_translation_struct_show()
295 root_tbl_walk(m, iommu); in dmar_translation_struct_show()
296 seq_putc(m, '\n'); in dmar_translation_struct_show()
306 return BIT_ULL(VTD_PAGE_SHIFT + VTD_STRIDE_SHIFT * (level - 1)); in level_to_directory_size()
310 dump_page_info(struct seq_file *m, unsigned long iova, u64 *path) in dump_page_info() argument
312 seq_printf(m, "0x%013lx |\t0x%016llx\t0x%016llx\t0x%016llx\t0x%016llx\t0x%016llx\n", in dump_page_info()
317 static void pgtable_walk_level(struct seq_file *m, struct dma_pte *pde, in pgtable_walk_level() argument
331 path[level] = pde->val; in pgtable_walk_level()
333 dump_page_info(m, start, path); in pgtable_walk_level()
335 pgtable_walk_level(m, phys_to_virt(dma_pte_addr(pde)), in pgtable_walk_level()
336 level - 1, start, path); in pgtable_walk_level()
344 struct seq_file *m = data; in show_device_domain_translation() local
350 seq_printf(m, "Device %s with pasid %d @0x%llx\n", in show_device_domain_translation()
351 dev_name(dev), domain->default_pasid, in show_device_domain_translation()
352 (u64)virt_to_phys(domain->pgd)); in show_device_domain_translation()
353 seq_puts(m, "IOVA_PFN\t\tPML5E\t\t\tPML4E\t\t\tPDPE\t\t\tPDE\t\t\tPTE\n"); in show_device_domain_translation()
355 pgtable_walk_level(m, domain->pgd, domain->agaw + 2, 0, path); in show_device_domain_translation()
356 seq_putc(m, '\n'); in show_device_domain_translation()
361 static int domain_translation_struct_show(struct seq_file *m, void *unused) in domain_translation_struct_show() argument
367 ret = bus_for_each_dev(&pci_bus_type, NULL, m, in domain_translation_struct_show()
375 static void invalidation_queue_entry_show(struct seq_file *m, in invalidation_queue_entry_show() argument
382 if (ecap_smts(iommu->ecap)) in invalidation_queue_entry_show()
383 seq_puts(m, "Index\t\tqw0\t\t\tqw1\t\t\tqw2\t\t\tqw3\t\t\tstatus\n"); in invalidation_queue_entry_show()
385 seq_puts(m, "Index\t\tqw0\t\t\tqw1\t\t\tstatus\n"); in invalidation_queue_entry_show()
389 desc = iommu->qi->desc + offset; in invalidation_queue_entry_show()
390 if (ecap_smts(iommu->ecap)) in invalidation_queue_entry_show()
391 seq_printf(m, "%5d\t%016llx\t%016llx\t%016llx\t%016llx\t%016x\n", in invalidation_queue_entry_show()
392 index, desc->qw0, desc->qw1, in invalidation_queue_entry_show()
393 desc->qw2, desc->qw3, in invalidation_queue_entry_show()
394 iommu->qi->desc_status[index]); in invalidation_queue_entry_show()
396 seq_printf(m, "%5d\t%016llx\t%016llx\t%016x\n", in invalidation_queue_entry_show()
397 index, desc->qw0, desc->qw1, in invalidation_queue_entry_show()
398 iommu->qi->desc_status[index]); in invalidation_queue_entry_show()
402 static int invalidation_queue_show(struct seq_file *m, void *unused) in invalidation_queue_show() argument
412 qi = iommu->qi; in invalidation_queue_show()
415 if (!qi || !ecap_qis(iommu->ecap)) in invalidation_queue_show()
418 seq_printf(m, "Invalidation queue on IOMMU: %s\n", iommu->name); in invalidation_queue_show()
420 raw_spin_lock_irqsave(&qi->q_lock, flags); in invalidation_queue_show()
421 seq_printf(m, " Base: 0x%llx\tHead: %lld\tTail: %lld\n", in invalidation_queue_show()
422 (u64)virt_to_phys(qi->desc), in invalidation_queue_show()
423 dmar_readq(iommu->reg + DMAR_IQH_REG) >> shift, in invalidation_queue_show()
424 dmar_readq(iommu->reg + DMAR_IQT_REG) >> shift); in invalidation_queue_show()
425 invalidation_queue_entry_show(m, iommu); in invalidation_queue_show()
426 raw_spin_unlock_irqrestore(&qi->q_lock, flags); in invalidation_queue_show()
427 seq_putc(m, '\n'); in invalidation_queue_show()
436 static void ir_tbl_remap_entry_show(struct seq_file *m, in ir_tbl_remap_entry_show() argument
443 seq_puts(m, " Entry SrcID DstID Vct IRTE_high\t\tIRTE_low\n"); in ir_tbl_remap_entry_show()
447 ri_entry = &iommu->ir_table->base[idx]; in ir_tbl_remap_entry_show()
448 if (!ri_entry->present || ri_entry->p_pst) in ir_tbl_remap_entry_show()
451 seq_printf(m, " %-5d %02x:%02x.%01x %08x %02x %016llx\t%016llx\n", in ir_tbl_remap_entry_show()
452 idx, PCI_BUS_NUM(ri_entry->sid), in ir_tbl_remap_entry_show()
453 PCI_SLOT(ri_entry->sid), PCI_FUNC(ri_entry->sid), in ir_tbl_remap_entry_show()
454 ri_entry->dest_id, ri_entry->vector, in ir_tbl_remap_entry_show()
455 ri_entry->high, ri_entry->low); in ir_tbl_remap_entry_show()
460 static void ir_tbl_posted_entry_show(struct seq_file *m, in ir_tbl_posted_entry_show() argument
467 seq_puts(m, " Entry SrcID PDA_high PDA_low Vct IRTE_high\t\tIRTE_low\n"); in ir_tbl_posted_entry_show()
471 pi_entry = &iommu->ir_table->base[idx]; in ir_tbl_posted_entry_show()
472 if (!pi_entry->present || !pi_entry->p_pst) in ir_tbl_posted_entry_show()
475 seq_printf(m, " %-5d %02x:%02x.%01x %08x %08x %02x %016llx\t%016llx\n", in ir_tbl_posted_entry_show()
476 idx, PCI_BUS_NUM(pi_entry->sid), in ir_tbl_posted_entry_show()
477 PCI_SLOT(pi_entry->sid), PCI_FUNC(pi_entry->sid), in ir_tbl_posted_entry_show()
478 pi_entry->pda_h, pi_entry->pda_l << 6, in ir_tbl_posted_entry_show()
479 pi_entry->vector, pi_entry->high, in ir_tbl_posted_entry_show()
480 pi_entry->low); in ir_tbl_posted_entry_show()
490 static int ir_translation_struct_show(struct seq_file *m, void *unused) in ir_translation_struct_show() argument
499 if (!ecap_ir_support(iommu->ecap)) in ir_translation_struct_show()
502 seq_printf(m, "Remapped Interrupt supported on IOMMU: %s\n", in ir_translation_struct_show()
503 iommu->name); in ir_translation_struct_show()
505 sts = dmar_readl(iommu->reg + DMAR_GSTS_REG); in ir_translation_struct_show()
506 if (iommu->ir_table && (sts & DMA_GSTS_IRES)) { in ir_translation_struct_show()
507 irta = virt_to_phys(iommu->ir_table->base); in ir_translation_struct_show()
508 seq_printf(m, " IR table address:%llx\n", irta); in ir_translation_struct_show()
509 ir_tbl_remap_entry_show(m, iommu); in ir_translation_struct_show()
511 seq_puts(m, "Interrupt Remapping is not enabled\n"); in ir_translation_struct_show()
513 seq_putc(m, '\n'); in ir_translation_struct_show()
516 seq_puts(m, "****\n\n"); in ir_translation_struct_show()
519 if (!cap_pi_support(iommu->cap)) in ir_translation_struct_show()
522 seq_printf(m, "Posted Interrupt supported on IOMMU: %s\n", in ir_translation_struct_show()
523 iommu->name); in ir_translation_struct_show()
525 if (iommu->ir_table) { in ir_translation_struct_show()
526 irta = virt_to_phys(iommu->ir_table->base); in ir_translation_struct_show()
527 seq_printf(m, " IR table address:%llx\n", irta); in ir_translation_struct_show()
528 ir_tbl_posted_entry_show(m, iommu); in ir_translation_struct_show()
530 seq_puts(m, "Interrupt Remapping is not enabled\n"); in ir_translation_struct_show()
532 seq_putc(m, '\n'); in ir_translation_struct_show()