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307 #define V2_CQC_BYTE_4_CEQN_M GENMASK(23, 15)
313 #define V2_CQC_BYTE_8_CQN_M GENMASK(23, 0)
334 #define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_M GENMASK(23, 0)
337 #define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_M GENMASK(23, 0)
348 #define	V2_CQC_BYTE_52_CQE_CNT_M GENMASK(23, 0)
357 #define	V2_CQC_BYTE_64_SE_CQE_IDX_M GENMASK(23, 0)
394 #define SRQC_BYTE_12_SRQ_XRCD_M GENMASK(23, 0)
406 #define SRQC_BYTE_28_PD_M GENMASK(23, 0)
418 #define SRQC_BYTE_44_SRQ_IDX_HOP_NUM_M GENMASK(23, 22)
430 #define SRQC_BYTE_56_SRQ_XRC_CQN_M GENMASK(23, 0)
566 #define V2_QPC_BYTE_20_SGID_IDX_M GENMASK(23, 16)
587 #define V2_QPC_BYTE_28_SL_M GENMASK(23, 20)
605 #define V2_QPC_BYTE_56_DQPN_M GENMASK(23, 0)
634 #define V2_QPC_BYTE_76_SRQN_M GENMASK(23, 0)
648 #define V2_QPC_BYTE_80_RX_CQN_M GENMASK(23, 0)
666 #define V2_QPC_BYTE_96_RX_REQ_MSN_M GENMASK(23, 0)
704 #define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M GENMASK(23, 16)
710 #define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M GENMASK(23, 0)
718 #define V2_QPC_BYTE_148_RQ_MSN_M GENMASK(23, 0)
724 #define V2_QPC_BYTE_152_RAQ_PSN_M GENMASK(23, 0)
730 #define V2_QPC_BYTE_156_RAQ_USE_PKTN_M GENMASK(23, 0)
746 #define V2_QPC_BYTE_168_LP_SGEN_INI_M GENMASK(23, 22)
766 #define V2_QPC_BYTE_176_MSG_USE_PKTN_M GENMASK(23, 0)
778 #define V2_QPC_BYTE_192_CUR_SGE_IDX_M GENMASK(23, 0)
808 #define V2_QPC_BYTE_212_LSN_M GENMASK(23, 0)
851 #define V2_QPC_BYTE_244_RX_ACK_EPSN_M GENMASK(23, 0)
863 #define V2_QPC_BYTE_248_IRRL_PSN_M GENMASK(23, 0)
877 #define V2_QPC_BYTE_252_TX_CQN_M GENMASK(23, 0)
925 #define V2_CQE_BYTE_12_XRC_SRQN_M GENMASK(23, 0)
928 #define V2_CQE_BYTE_16_LCL_QPN_M GENMASK(23, 0)
948 #define V2_CQE_BYTE_32_RMT_QPN_M GENMASK(23, 0)
1040 #define V2_DB_BYTE_4_TAG_M GENMASK(23, 0)
1052 #define V2_CQ_DB_BYTE_4_TAG_M GENMASK(23, 0)
1058 #define V2_CQ_DB_PARAMETER_CONS_IDX_M GENMASK(23, 0)
1091 #define V2_UD_SEND_WQE_BYTE_16_PD_M GENMASK(23, 0)
1097 #define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0)
1103 #define V2_UD_SEND_WQE_BYTE_32_DQPN_M GENMASK(23, 0)
1109 #define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M GENMASK(23, 16)
1118 #define V2_UD_SEND_WQE_BYTE_40_SL_M GENMASK(23, 20)
1134 #define V2_UD_SEND_WQE_DMAC_2_M GENMASK(23, 16)
1146 #define V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M GENMASK(23, 16)
1187 #define V2_RC_FRMR_WQE_BYTE_4_LW_S 23
1190 #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_M GENMASK(23, 0)
1196 #define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0)
1670 #define V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_M GENMASK(23, 22)
1686 #define V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_M GENMASK(23, 22)
1855 #define HNS_ROCE_V2_EQN_M GENMASK(23, 0)
1857 #define HNS_ROCE_V2_CONS_IDX_M GENMASK(23, 0)
1949 #define HNS_ROCE_V2_CEQE_COMP_CQN_M GENMASK(23, 0)
1964 #define HNS_ROCE_V2_EQ_DB_PARA_M GENMASK(23, 0)
1967 #define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M GENMASK(23, 0)