Lines Matching +full:supports +full:- +full:cqe
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 * Copyright 2018-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
71 struct efa_com_mmio_read *mmio_read = &edev->mmio_read; in efa_com_reg_read32()
77 read_resp = mmio_read->read_resp; in efa_com_reg_read32()
79 spin_lock(&mmio_read->lock); in efa_com_reg_read32()
80 mmio_read->seq_num++; in efa_com_reg_read32()
83 read_resp->req_id = mmio_read->seq_num + 0x9aL; in efa_com_reg_read32()
86 mmio_read->seq_num); in efa_com_reg_read32()
88 writel(mmio_read_reg, edev->reg_bar + EFA_REGS_MMIO_REG_READ_OFF); in efa_com_reg_read32()
90 exp_time = jiffies + usecs_to_jiffies(mmio_read->mmio_read_timeout); in efa_com_reg_read32()
92 if (READ_ONCE(read_resp->req_id) == mmio_read->seq_num) in efa_com_reg_read32()
97 if (read_resp->req_id != mmio_read->seq_num) { in efa_com_reg_read32()
99 edev->efa_dev, in efa_com_reg_read32()
101 mmio_read->seq_num, offset, read_resp->req_id, in efa_com_reg_read32()
102 read_resp->reg_off); in efa_com_reg_read32()
107 if (read_resp->reg_off != offset) { in efa_com_reg_read32()
109 edev->efa_dev, in efa_com_reg_read32()
115 err = read_resp->reg_val; in efa_com_reg_read32()
117 spin_unlock(&mmio_read->lock); in efa_com_reg_read32()
123 struct efa_com_admin_queue *aq = &edev->aq; in efa_com_admin_init_sq()
124 struct efa_com_admin_sq *sq = &aq->sq; in efa_com_admin_init_sq()
125 u16 size = aq->depth * sizeof(*sq->entries); in efa_com_admin_init_sq()
130 sq->entries = in efa_com_admin_init_sq()
131 dma_alloc_coherent(aq->dmadev, size, &sq->dma_addr, GFP_KERNEL); in efa_com_admin_init_sq()
132 if (!sq->entries) in efa_com_admin_init_sq()
133 return -ENOMEM; in efa_com_admin_init_sq()
135 spin_lock_init(&sq->lock); in efa_com_admin_init_sq()
137 sq->cc = 0; in efa_com_admin_init_sq()
138 sq->pc = 0; in efa_com_admin_init_sq()
139 sq->phase = 1; in efa_com_admin_init_sq()
141 sq->db_addr = (u32 __iomem *)(edev->reg_bar + EFA_REGS_AQ_PROD_DB_OFF); in efa_com_admin_init_sq()
143 addr_high = EFA_DMA_ADDR_TO_UINT32_HIGH(sq->dma_addr); in efa_com_admin_init_sq()
144 addr_low = EFA_DMA_ADDR_TO_UINT32_LOW(sq->dma_addr); in efa_com_admin_init_sq()
146 writel(addr_low, edev->reg_bar + EFA_REGS_AQ_BASE_LO_OFF); in efa_com_admin_init_sq()
147 writel(addr_high, edev->reg_bar + EFA_REGS_AQ_BASE_HI_OFF); in efa_com_admin_init_sq()
149 EFA_SET(&aq_caps, EFA_REGS_AQ_CAPS_AQ_DEPTH, aq->depth); in efa_com_admin_init_sq()
153 writel(aq_caps, edev->reg_bar + EFA_REGS_AQ_CAPS_OFF); in efa_com_admin_init_sq()
160 struct efa_com_admin_queue *aq = &edev->aq; in efa_com_admin_init_cq()
161 struct efa_com_admin_cq *cq = &aq->cq; in efa_com_admin_init_cq()
162 u16 size = aq->depth * sizeof(*cq->entries); in efa_com_admin_init_cq()
167 cq->entries = in efa_com_admin_init_cq()
168 dma_alloc_coherent(aq->dmadev, size, &cq->dma_addr, GFP_KERNEL); in efa_com_admin_init_cq()
169 if (!cq->entries) in efa_com_admin_init_cq()
170 return -ENOMEM; in efa_com_admin_init_cq()
172 spin_lock_init(&cq->lock); in efa_com_admin_init_cq()
174 cq->cc = 0; in efa_com_admin_init_cq()
175 cq->phase = 1; in efa_com_admin_init_cq()
177 addr_high = EFA_DMA_ADDR_TO_UINT32_HIGH(cq->dma_addr); in efa_com_admin_init_cq()
178 addr_low = EFA_DMA_ADDR_TO_UINT32_LOW(cq->dma_addr); in efa_com_admin_init_cq()
180 writel(addr_low, edev->reg_bar + EFA_REGS_ACQ_BASE_LO_OFF); in efa_com_admin_init_cq()
181 writel(addr_high, edev->reg_bar + EFA_REGS_ACQ_BASE_HI_OFF); in efa_com_admin_init_cq()
183 EFA_SET(&acq_caps, EFA_REGS_ACQ_CAPS_ACQ_DEPTH, aq->depth); in efa_com_admin_init_cq()
187 aq->msix_vector_idx); in efa_com_admin_init_cq()
189 writel(acq_caps, edev->reg_bar + EFA_REGS_ACQ_CAPS_OFF); in efa_com_admin_init_cq()
197 struct efa_com_aenq *aenq = &edev->aenq; in efa_com_admin_init_aenq()
203 ibdev_err(edev->efa_dev, "aenq handlers pointer is NULL\n"); in efa_com_admin_init_aenq()
204 return -EINVAL; in efa_com_admin_init_aenq()
207 size = EFA_ASYNC_QUEUE_DEPTH * sizeof(*aenq->entries); in efa_com_admin_init_aenq()
208 aenq->entries = dma_alloc_coherent(edev->dmadev, size, &aenq->dma_addr, in efa_com_admin_init_aenq()
210 if (!aenq->entries) in efa_com_admin_init_aenq()
211 return -ENOMEM; in efa_com_admin_init_aenq()
213 aenq->aenq_handlers = aenq_handlers; in efa_com_admin_init_aenq()
214 aenq->depth = EFA_ASYNC_QUEUE_DEPTH; in efa_com_admin_init_aenq()
215 aenq->cc = 0; in efa_com_admin_init_aenq()
216 aenq->phase = 1; in efa_com_admin_init_aenq()
218 addr_low = EFA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr); in efa_com_admin_init_aenq()
219 addr_high = EFA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr); in efa_com_admin_init_aenq()
221 writel(addr_low, edev->reg_bar + EFA_REGS_AENQ_BASE_LO_OFF); in efa_com_admin_init_aenq()
222 writel(addr_high, edev->reg_bar + EFA_REGS_AENQ_BASE_HI_OFF); in efa_com_admin_init_aenq()
224 EFA_SET(&aenq_caps, EFA_REGS_AENQ_CAPS_AENQ_DEPTH, aenq->depth); in efa_com_admin_init_aenq()
228 aenq->msix_vector_idx); in efa_com_admin_init_aenq()
229 writel(aenq_caps, edev->reg_bar + EFA_REGS_AENQ_CAPS_OFF); in efa_com_admin_init_aenq()
235 writel(edev->aenq.cc, edev->reg_bar + EFA_REGS_AENQ_CONS_DB_OFF); in efa_com_admin_init_aenq()
245 spin_lock(&aq->comp_ctx_lock); in efa_com_alloc_ctx_id()
246 ctx_id = aq->comp_ctx_pool[aq->comp_ctx_pool_next]; in efa_com_alloc_ctx_id()
247 aq->comp_ctx_pool_next++; in efa_com_alloc_ctx_id()
248 spin_unlock(&aq->comp_ctx_lock); in efa_com_alloc_ctx_id()
256 spin_lock(&aq->comp_ctx_lock); in efa_com_dealloc_ctx_id()
257 aq->comp_ctx_pool_next--; in efa_com_dealloc_ctx_id()
258 aq->comp_ctx_pool[aq->comp_ctx_pool_next] = ctx_id; in efa_com_dealloc_ctx_id()
259 spin_unlock(&aq->comp_ctx_lock); in efa_com_dealloc_ctx_id()
265 u16 cmd_id = EFA_GET(&comp_ctx->user_cqe->acq_common_descriptor.command, in efa_com_put_comp_ctx()
267 u16 ctx_id = cmd_id & (aq->depth - 1); in efa_com_put_comp_ctx()
269 ibdev_dbg(aq->efa_dev, "Put completion command_id %#x\n", cmd_id); in efa_com_put_comp_ctx()
270 comp_ctx->occupied = 0; in efa_com_put_comp_ctx()
277 u16 ctx_id = cmd_id & (aq->depth - 1); in efa_com_get_comp_ctx()
279 if (aq->comp_ctx[ctx_id].occupied && capture) { in efa_com_get_comp_ctx()
281 aq->efa_dev, in efa_com_get_comp_ctx()
288 aq->comp_ctx[ctx_id].occupied = 1; in efa_com_get_comp_ctx()
289 ibdev_dbg(aq->efa_dev, in efa_com_get_comp_ctx()
293 return &aq->comp_ctx[ctx_id]; in efa_com_get_comp_ctx()
309 queue_size_mask = aq->depth - 1; in __efa_com_submit_admin_cmd()
310 pi = aq->sq.pc & queue_size_mask; in __efa_com_submit_admin_cmd()
316 cmd_id |= aq->sq.pc & ~queue_size_mask; in __efa_com_submit_admin_cmd()
319 cmd->aq_common_descriptor.command_id = cmd_id; in __efa_com_submit_admin_cmd()
320 EFA_SET(&cmd->aq_common_descriptor.flags, in __efa_com_submit_admin_cmd()
321 EFA_ADMIN_AQ_COMMON_DESC_PHASE, aq->sq.phase); in __efa_com_submit_admin_cmd()
326 return ERR_PTR(-EINVAL); in __efa_com_submit_admin_cmd()
329 comp_ctx->status = EFA_CMD_SUBMITTED; in __efa_com_submit_admin_cmd()
330 comp_ctx->comp_size = comp_size_in_bytes; in __efa_com_submit_admin_cmd()
331 comp_ctx->user_cqe = comp; in __efa_com_submit_admin_cmd()
332 comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode; in __efa_com_submit_admin_cmd()
334 reinit_completion(&comp_ctx->wait_event); in __efa_com_submit_admin_cmd()
336 aqe = &aq->sq.entries[pi]; in __efa_com_submit_admin_cmd()
340 aq->sq.pc++; in __efa_com_submit_admin_cmd()
341 atomic64_inc(&aq->stats.submitted_cmd); in __efa_com_submit_admin_cmd()
343 if ((aq->sq.pc & queue_size_mask) == 0) in __efa_com_submit_admin_cmd()
344 aq->sq.phase = !aq->sq.phase; in __efa_com_submit_admin_cmd()
347 writel(aq->sq.pc, aq->sq.db_addr); in __efa_com_submit_admin_cmd()
354 size_t pool_size = aq->depth * sizeof(*aq->comp_ctx_pool); in efa_com_init_comp_ctxt()
355 size_t size = aq->depth * sizeof(struct efa_comp_ctx); in efa_com_init_comp_ctxt()
359 aq->comp_ctx = devm_kzalloc(aq->dmadev, size, GFP_KERNEL); in efa_com_init_comp_ctxt()
360 aq->comp_ctx_pool = devm_kzalloc(aq->dmadev, pool_size, GFP_KERNEL); in efa_com_init_comp_ctxt()
361 if (!aq->comp_ctx || !aq->comp_ctx_pool) { in efa_com_init_comp_ctxt()
362 devm_kfree(aq->dmadev, aq->comp_ctx_pool); in efa_com_init_comp_ctxt()
363 devm_kfree(aq->dmadev, aq->comp_ctx); in efa_com_init_comp_ctxt()
364 return -ENOMEM; in efa_com_init_comp_ctxt()
367 for (i = 0; i < aq->depth; i++) { in efa_com_init_comp_ctxt()
370 init_completion(&comp_ctx->wait_event); in efa_com_init_comp_ctxt()
372 aq->comp_ctx_pool[i] = i; in efa_com_init_comp_ctxt()
375 spin_lock_init(&aq->comp_ctx_lock); in efa_com_init_comp_ctxt()
377 aq->comp_ctx_pool_next = 0; in efa_com_init_comp_ctxt()
390 spin_lock(&aq->sq.lock); in efa_com_submit_admin_cmd()
391 if (!test_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state)) { in efa_com_submit_admin_cmd()
392 ibdev_err_ratelimited(aq->efa_dev, "Admin queue is closed\n"); in efa_com_submit_admin_cmd()
393 spin_unlock(&aq->sq.lock); in efa_com_submit_admin_cmd()
394 return ERR_PTR(-ENODEV); in efa_com_submit_admin_cmd()
399 spin_unlock(&aq->sq.lock); in efa_com_submit_admin_cmd()
401 clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state); in efa_com_submit_admin_cmd()
407 struct efa_admin_acq_entry *cqe) in efa_com_handle_single_admin_completion() argument
412 cmd_id = EFA_GET(&cqe->acq_common_descriptor.command, in efa_com_handle_single_admin_completion()
417 ibdev_err(aq->efa_dev, in efa_com_handle_single_admin_completion()
419 clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state); in efa_com_handle_single_admin_completion()
423 comp_ctx->status = EFA_CMD_COMPLETED; in efa_com_handle_single_admin_completion()
424 comp_ctx->comp_status = cqe->acq_common_descriptor.status; in efa_com_handle_single_admin_completion()
425 if (comp_ctx->user_cqe) in efa_com_handle_single_admin_completion()
426 memcpy(comp_ctx->user_cqe, cqe, comp_ctx->comp_size); in efa_com_handle_single_admin_completion()
428 if (!test_bit(EFA_AQ_STATE_POLLING_BIT, &aq->state)) in efa_com_handle_single_admin_completion()
429 complete(&comp_ctx->wait_event); in efa_com_handle_single_admin_completion()
434 struct efa_admin_acq_entry *cqe; in efa_com_handle_admin_completion() local
440 queue_size_mask = aq->depth - 1; in efa_com_handle_admin_completion()
442 ci = aq->cq.cc & queue_size_mask; in efa_com_handle_admin_completion()
443 phase = aq->cq.phase; in efa_com_handle_admin_completion()
445 cqe = &aq->cq.entries[ci]; in efa_com_handle_admin_completion()
448 while ((READ_ONCE(cqe->acq_common_descriptor.flags) & in efa_com_handle_admin_completion()
455 efa_com_handle_single_admin_completion(aq, cqe); in efa_com_handle_admin_completion()
459 if (ci == aq->depth) { in efa_com_handle_admin_completion()
464 cqe = &aq->cq.entries[ci]; in efa_com_handle_admin_completion()
467 aq->cq.cc += comp_num; in efa_com_handle_admin_completion()
468 aq->cq.phase = phase; in efa_com_handle_admin_completion()
469 aq->sq.cc += comp_num; in efa_com_handle_admin_completion()
470 atomic64_add(comp_num, &aq->stats.completed_cmd); in efa_com_handle_admin_completion()
479 return -ENOMEM; in efa_com_comp_status_to_errno()
481 return -EOPNOTSUPP; in efa_com_comp_status_to_errno()
486 return -EINVAL; in efa_com_comp_status_to_errno()
488 return -EINVAL; in efa_com_comp_status_to_errno()
499 timeout = jiffies + usecs_to_jiffies(aq->completion_timeout); in efa_com_wait_and_process_admin_cq_polling()
502 spin_lock_irqsave(&aq->cq.lock, flags); in efa_com_wait_and_process_admin_cq_polling()
504 spin_unlock_irqrestore(&aq->cq.lock, flags); in efa_com_wait_and_process_admin_cq_polling()
506 if (comp_ctx->status != EFA_CMD_SUBMITTED) in efa_com_wait_and_process_admin_cq_polling()
511 aq->efa_dev, in efa_com_wait_and_process_admin_cq_polling()
514 atomic64_inc(&aq->stats.no_completion); in efa_com_wait_and_process_admin_cq_polling()
516 clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state); in efa_com_wait_and_process_admin_cq_polling()
517 err = -ETIME; in efa_com_wait_and_process_admin_cq_polling()
521 msleep(aq->poll_interval); in efa_com_wait_and_process_admin_cq_polling()
524 err = efa_com_comp_status_to_errno(comp_ctx->comp_status); in efa_com_wait_and_process_admin_cq_polling()
536 wait_for_completion_timeout(&comp_ctx->wait_event, in efa_com_wait_and_process_admin_cq_interrupts()
537 usecs_to_jiffies(aq->completion_timeout)); in efa_com_wait_and_process_admin_cq_interrupts()
543 * 2) There is completion but the device didn't get any msi-x interrupt. in efa_com_wait_and_process_admin_cq_interrupts()
545 if (comp_ctx->status == EFA_CMD_SUBMITTED) { in efa_com_wait_and_process_admin_cq_interrupts()
546 spin_lock_irqsave(&aq->cq.lock, flags); in efa_com_wait_and_process_admin_cq_interrupts()
548 spin_unlock_irqrestore(&aq->cq.lock, flags); in efa_com_wait_and_process_admin_cq_interrupts()
550 atomic64_inc(&aq->stats.no_completion); in efa_com_wait_and_process_admin_cq_interrupts()
552 if (comp_ctx->status == EFA_CMD_COMPLETED) in efa_com_wait_and_process_admin_cq_interrupts()
554 aq->efa_dev, in efa_com_wait_and_process_admin_cq_interrupts()
555 …"The device sent a completion but the driver didn't receive any MSI-X interrupt for admin cmd %s(%… in efa_com_wait_and_process_admin_cq_interrupts()
556 efa_com_cmd_str(comp_ctx->cmd_opcode), in efa_com_wait_and_process_admin_cq_interrupts()
557 comp_ctx->cmd_opcode, comp_ctx->status, in efa_com_wait_and_process_admin_cq_interrupts()
558 comp_ctx, aq->sq.pc, aq->sq.cc, aq->cq.cc); in efa_com_wait_and_process_admin_cq_interrupts()
561 aq->efa_dev, in efa_com_wait_and_process_admin_cq_interrupts()
563 efa_com_cmd_str(comp_ctx->cmd_opcode), in efa_com_wait_and_process_admin_cq_interrupts()
564 comp_ctx->cmd_opcode, comp_ctx->status, in efa_com_wait_and_process_admin_cq_interrupts()
565 comp_ctx, aq->sq.pc, aq->sq.cc, aq->cq.cc); in efa_com_wait_and_process_admin_cq_interrupts()
567 clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state); in efa_com_wait_and_process_admin_cq_interrupts()
568 err = -ETIME; in efa_com_wait_and_process_admin_cq_interrupts()
572 err = efa_com_comp_status_to_errno(comp_ctx->comp_status); in efa_com_wait_and_process_admin_cq_interrupts()
580 * Polling mode - wait until the completion is available.
581 * Async mode - wait on wait queue until the completion is ready
589 if (test_bit(EFA_AQ_STATE_POLLING_BIT, &aq->state)) in efa_com_wait_and_process_admin_cq()
596 * efa_com_cmd_exec - Execute admin command
606 * @return - 0 on success, negative value on failure.
620 down(&aq->avail_cmds); in efa_com_cmd_exec()
622 ibdev_dbg(aq->efa_dev, "%s (opcode %d)\n", in efa_com_cmd_exec()
623 efa_com_cmd_str(cmd->aq_common_descriptor.opcode), in efa_com_cmd_exec()
624 cmd->aq_common_descriptor.opcode); in efa_com_cmd_exec()
628 aq->efa_dev, in efa_com_cmd_exec()
630 efa_com_cmd_str(cmd->aq_common_descriptor.opcode), in efa_com_cmd_exec()
631 cmd->aq_common_descriptor.opcode, PTR_ERR(comp_ctx)); in efa_com_cmd_exec()
633 up(&aq->avail_cmds); in efa_com_cmd_exec()
634 atomic64_inc(&aq->stats.cmd_err); in efa_com_cmd_exec()
641 aq->efa_dev, in efa_com_cmd_exec()
643 efa_com_cmd_str(cmd->aq_common_descriptor.opcode), in efa_com_cmd_exec()
644 cmd->aq_common_descriptor.opcode, comp_ctx->comp_status, in efa_com_cmd_exec()
646 atomic64_inc(&aq->stats.cmd_err); in efa_com_cmd_exec()
649 up(&aq->avail_cmds); in efa_com_cmd_exec()
655 * efa_com_admin_destroy - Destroy the admin and the async events queues.
660 struct efa_com_admin_queue *aq = &edev->aq; in efa_com_admin_destroy()
661 struct efa_com_aenq *aenq = &edev->aenq; in efa_com_admin_destroy()
662 struct efa_com_admin_cq *cq = &aq->cq; in efa_com_admin_destroy()
663 struct efa_com_admin_sq *sq = &aq->sq; in efa_com_admin_destroy()
666 clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state); in efa_com_admin_destroy()
668 devm_kfree(edev->dmadev, aq->comp_ctx_pool); in efa_com_admin_destroy()
669 devm_kfree(edev->dmadev, aq->comp_ctx); in efa_com_admin_destroy()
671 size = aq->depth * sizeof(*sq->entries); in efa_com_admin_destroy()
672 dma_free_coherent(edev->dmadev, size, sq->entries, sq->dma_addr); in efa_com_admin_destroy()
674 size = aq->depth * sizeof(*cq->entries); in efa_com_admin_destroy()
675 dma_free_coherent(edev->dmadev, size, cq->entries, cq->dma_addr); in efa_com_admin_destroy()
677 size = aenq->depth * sizeof(*aenq->entries); in efa_com_admin_destroy()
678 dma_free_coherent(edev->dmadev, size, aenq->entries, aenq->dma_addr); in efa_com_admin_destroy()
682 * efa_com_set_admin_polling_mode - Set the admin completion queue polling mode
695 writel(mask_value, edev->reg_bar + EFA_REGS_INTR_MASK_OFF); in efa_com_set_admin_polling_mode()
697 set_bit(EFA_AQ_STATE_POLLING_BIT, &edev->aq.state); in efa_com_set_admin_polling_mode()
699 clear_bit(EFA_AQ_STATE_POLLING_BIT, &edev->aq.state); in efa_com_set_admin_polling_mode()
704 atomic64_t *s = (atomic64_t *)&edev->aq.stats; in efa_com_stats_init()
707 for (i = 0; i < sizeof(edev->aq.stats) / sizeof(*s); i++, s++) in efa_com_stats_init()
712 * efa_com_admin_init - Init the admin and the async queues
719 * @return - 0 on success, negative value on failure.
724 struct efa_com_admin_queue *aq = &edev->aq; in efa_com_admin_init()
732 ibdev_err(edev->efa_dev, in efa_com_admin_init()
734 return -ENODEV; in efa_com_admin_init()
737 aq->depth = EFA_ADMIN_QUEUE_DEPTH; in efa_com_admin_init()
739 aq->dmadev = edev->dmadev; in efa_com_admin_init()
740 aq->efa_dev = edev->efa_dev; in efa_com_admin_init()
741 set_bit(EFA_AQ_STATE_POLLING_BIT, &aq->state); in efa_com_admin_init()
743 sema_init(&aq->avail_cmds, aq->depth); in efa_com_admin_init()
769 aq->completion_timeout = timeout * 100000; in efa_com_admin_init()
771 aq->completion_timeout = ADMIN_CMD_TIMEOUT_US; in efa_com_admin_init()
773 aq->poll_interval = EFA_POLL_INTERVAL_MS; in efa_com_admin_init()
775 set_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state); in efa_com_admin_init()
780 dma_free_coherent(edev->dmadev, aq->depth * sizeof(*aq->cq.entries), in efa_com_admin_init()
781 aq->cq.entries, aq->cq.dma_addr); in efa_com_admin_init()
783 dma_free_coherent(edev->dmadev, aq->depth * sizeof(*aq->sq.entries), in efa_com_admin_init()
784 aq->sq.entries, aq->sq.dma_addr); in efa_com_admin_init()
786 devm_kfree(edev->dmadev, aq->comp_ctx); in efa_com_admin_init()
792 * efa_com_admin_q_comp_intr_handler - admin queue interrupt handler
798 * @note: Should be called after MSI-X interrupt.
804 spin_lock_irqsave(&edev->aq.cq.lock, flags); in efa_com_admin_q_comp_intr_handler()
805 efa_com_handle_admin_completion(&edev->aq); in efa_com_admin_q_comp_intr_handler()
806 spin_unlock_irqrestore(&edev->aq.cq.lock, flags); in efa_com_admin_q_comp_intr_handler()
816 struct efa_aenq_handlers *aenq_handlers = edev->aenq.aenq_handlers; in efa_com_get_specific_aenq_cb()
818 if (group < EFA_MAX_HANDLERS && aenq_handlers->handlers[group]) in efa_com_get_specific_aenq_cb()
819 return aenq_handlers->handlers[group]; in efa_com_get_specific_aenq_cb()
821 return aenq_handlers->unimplemented_handler; in efa_com_get_specific_aenq_cb()
825 * efa_com_aenq_intr_handler - AENQ interrupt handler
834 struct efa_com_aenq *aenq = &edev->aenq; in efa_com_aenq_intr_handler()
841 ci = aenq->cc & (aenq->depth - 1); in efa_com_aenq_intr_handler()
842 phase = aenq->phase; in efa_com_aenq_intr_handler()
843 aenq_e = &aenq->entries[ci]; /* Get first entry */ in efa_com_aenq_intr_handler()
844 aenq_common = &aenq_e->aenq_common_desc; in efa_com_aenq_intr_handler()
847 while ((READ_ONCE(aenq_common->flags) & in efa_com_aenq_intr_handler()
857 aenq_common->group); in efa_com_aenq_intr_handler()
864 if (ci == aenq->depth) { in efa_com_aenq_intr_handler()
868 aenq_e = &aenq->entries[ci]; in efa_com_aenq_intr_handler()
869 aenq_common = &aenq_e->aenq_common_desc; in efa_com_aenq_intr_handler()
872 aenq->cc += processed; in efa_com_aenq_intr_handler()
873 aenq->phase = phase; in efa_com_aenq_intr_handler()
880 writel(aenq->cc, edev->reg_bar + EFA_REGS_AENQ_CONS_DB_OFF); in efa_com_aenq_intr_handler()
885 struct efa_com_mmio_read *mmio_read = &edev->mmio_read; in efa_com_mmio_reg_read_resp_addr_init()
890 addr_high = (mmio_read->read_resp_dma_addr >> 32) & GENMASK(31, 0); in efa_com_mmio_reg_read_resp_addr_init()
891 addr_low = mmio_read->read_resp_dma_addr & GENMASK(31, 0); in efa_com_mmio_reg_read_resp_addr_init()
893 writel(addr_high, edev->reg_bar + EFA_REGS_MMIO_RESP_HI_OFF); in efa_com_mmio_reg_read_resp_addr_init()
894 writel(addr_low, edev->reg_bar + EFA_REGS_MMIO_RESP_LO_OFF); in efa_com_mmio_reg_read_resp_addr_init()
899 struct efa_com_mmio_read *mmio_read = &edev->mmio_read; in efa_com_mmio_reg_read_init()
901 spin_lock_init(&mmio_read->lock); in efa_com_mmio_reg_read_init()
902 mmio_read->read_resp = in efa_com_mmio_reg_read_init()
903 dma_alloc_coherent(edev->dmadev, sizeof(*mmio_read->read_resp), in efa_com_mmio_reg_read_init()
904 &mmio_read->read_resp_dma_addr, GFP_KERNEL); in efa_com_mmio_reg_read_init()
905 if (!mmio_read->read_resp) in efa_com_mmio_reg_read_init()
906 return -ENOMEM; in efa_com_mmio_reg_read_init()
910 mmio_read->read_resp->req_id = 0; in efa_com_mmio_reg_read_init()
911 mmio_read->seq_num = 0; in efa_com_mmio_reg_read_init()
912 mmio_read->mmio_read_timeout = EFA_REG_READ_TIMEOUT_US; in efa_com_mmio_reg_read_init()
919 struct efa_com_mmio_read *mmio_read = &edev->mmio_read; in efa_com_mmio_reg_read_destroy()
921 dma_free_coherent(edev->dmadev, sizeof(*mmio_read->read_resp), in efa_com_mmio_reg_read_destroy()
922 mmio_read->read_resp, mmio_read->read_resp_dma_addr); in efa_com_mmio_reg_read_destroy()
941 ibdev_dbg(edev->efa_dev, "efa device version: %d.%d\n", in efa_com_validate_version()
950 ibdev_err(edev->efa_dev, in efa_com_validate_version()
951 "EFA version is lower than the minimal version the driver supports\n"); in efa_com_validate_version()
952 return -EOPNOTSUPP; in efa_com_validate_version()
956 edev->efa_dev, in efa_com_validate_version()
978 ibdev_err(edev->efa_dev, in efa_com_validate_version()
979 "EFA ctrl version is lower than the minimal ctrl version the driver supports\n"); in efa_com_validate_version()
980 return -EOPNOTSUPP; in efa_com_validate_version()
987 * efa_com_get_dma_width - Retrieve physical dma address width the device
988 * supports.
1002 ibdev_dbg(edev->efa_dev, "DMA width: %d\n", width); in efa_com_get_dma_width()
1005 ibdev_err(edev->efa_dev, "DMA width illegal value: %d\n", width); in efa_com_get_dma_width()
1006 return -EINVAL; in efa_com_get_dma_width()
1009 edev->dma_addr_bits = width; in efa_com_get_dma_width()
1024 ibdev_dbg(edev->efa_dev, "Reset indication val %d\n", val); in wait_for_reset_state()
1028 return -ETIME; in wait_for_reset_state()
1032 * efa_com_dev_reset - Perform device FLR to the device.
1036 * @return - 0 on success, negative value on failure.
1049 ibdev_err(edev->efa_dev, in efa_com_dev_reset()
1051 return -EINVAL; in efa_com_dev_reset()
1056 ibdev_err(edev->efa_dev, "Invalid timeout value\n"); in efa_com_dev_reset()
1057 return -EINVAL; in efa_com_dev_reset()
1063 writel(reset_val, edev->reg_bar + EFA_REGS_DEV_CTL_OFF); in efa_com_dev_reset()
1070 ibdev_err(edev->efa_dev, "Reset indication didn't turn on\n"); in efa_com_dev_reset()
1075 writel(0, edev->reg_bar + EFA_REGS_DEV_CTL_OFF); in efa_com_dev_reset()
1078 ibdev_err(edev->efa_dev, "Reset indication didn't turn off\n"); in efa_com_dev_reset()
1085 edev->aq.completion_timeout = timeout * 100000; in efa_com_dev_reset()
1087 edev->aq.completion_timeout = ADMIN_CMD_TIMEOUT_US; in efa_com_dev_reset()