1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/iio/timer/stm32-timer-trigger.h>
13 #include <linux/mfd/stm32-timers.h>
21 /* List the triggers created by each timer */
42 /* List the triggers accepted by each timer */
49 	{ }, /* timer 6 */
50 	{ }, /* timer 7 */
53 	{ }, /* timer 10 */
54 	{ }, /* timer 11 */
64 	{ }, /* timer 6 */
65 	{ }, /* timer 7 */
67 	{ }, /* timer 9 */
68 	{ }, /* timer 10 */
69 	{ }, /* timer 11 */
71 	{ }, /* timer 13 */
72 	{ }, /* timer 14 */
74 	{ }, /* timer 16 */
75 	{ }, /* timer 17 */
125 	div = (unsigned long long)clk_get_rate(priv->clk);  in stm32_timer_start()
135 	while (div > priv->max_arr) {  in stm32_timer_start()
143 		dev_err(priv->dev, "prescaler exceeds the maximum value\n");  in stm32_timer_start()
144 		return -EINVAL;  in stm32_timer_start()
147 	/* Check if nobody else use the timer */  in stm32_timer_start()
148 	regmap_read(priv->regmap, TIM_CCER, &ccer);  in stm32_timer_start()
150 		return -EBUSY;  in stm32_timer_start()
152 	mutex_lock(&priv->lock);  in stm32_timer_start()
153 	if (!priv->enabled) {  in stm32_timer_start()
154 		priv->enabled = true;  in stm32_timer_start()
155 		clk_enable(priv->clk);  in stm32_timer_start()
158 	regmap_write(priv->regmap, TIM_PSC, prescaler);  in stm32_timer_start()
159 	regmap_write(priv->regmap, TIM_ARR, prd - 1);  in stm32_timer_start()
160 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);  in stm32_timer_start()
163 	if (stm32_timer_is_trgo2_name(trig->name))  in stm32_timer_start()
164 		regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2,  in stm32_timer_start()
167 		regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS,  in stm32_timer_start()
171 	regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);  in stm32_timer_start()
174 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);  in stm32_timer_start()
175 	mutex_unlock(&priv->lock);  in stm32_timer_start()
185 	regmap_read(priv->regmap, TIM_CCER, &ccer);  in stm32_timer_stop()
189 	mutex_lock(&priv->lock);  in stm32_timer_stop()
190 	/* Stop timer */  in stm32_timer_stop()
191 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);  in stm32_timer_stop()
192 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);  in stm32_timer_stop()
193 	regmap_write(priv->regmap, TIM_PSC, 0);  in stm32_timer_stop()
194 	regmap_write(priv->regmap, TIM_ARR, 0);  in stm32_timer_stop()
197 	if (stm32_timer_is_trgo2_name(trig->name))  in stm32_timer_stop()
198 		regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);  in stm32_timer_stop()
200 		regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 0);  in stm32_timer_stop()
203 	regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);  in stm32_timer_stop()
205 	if (priv->enabled) {  in stm32_timer_stop()
206 		priv->enabled = false;  in stm32_timer_stop()
207 		clk_disable(priv->clk);  in stm32_timer_stop()
209 	mutex_unlock(&priv->lock);  in stm32_timer_stop()
244 	regmap_read(priv->regmap, TIM_CR1, &cr1);  in stm32_tt_read_frequency()
245 	regmap_read(priv->regmap, TIM_PSC, &psc);  in stm32_tt_read_frequency()
246 	regmap_read(priv->regmap, TIM_ARR, &arr);  in stm32_tt_read_frequency()
249 		freq = (unsigned long long)clk_get_rate(priv->clk);  in stm32_tt_read_frequency()
292 	regmap_read(priv->regmap, TIM_CR2, &cr2);  in stm32_tt_show_master_mode()
294 	if (stm32_timer_is_trgo2_name(trig->name))  in stm32_tt_show_master_mode()
311 	if (stm32_timer_is_trgo2_name(trig->name)) {  in stm32_tt_store_master_mode()
324 			mutex_lock(&priv->lock);  in stm32_tt_store_master_mode()
325 			if (!priv->enabled) {  in stm32_tt_store_master_mode()
327 				priv->enabled = true;  in stm32_tt_store_master_mode()
328 				clk_enable(priv->clk);  in stm32_tt_store_master_mode()
330 			regmap_update_bits(priv->regmap, TIM_CR2, mask,  in stm32_tt_store_master_mode()
332 			mutex_unlock(&priv->lock);  in stm32_tt_store_master_mode()
337 	return -EINVAL;  in stm32_tt_store_master_mode()
348 	if (stm32_timer_is_trgo2_name(trig->name))  in stm32_tt_show_master_mode_avail()
354 		len += scnprintf(buf + len, PAGE_SIZE - len,  in stm32_tt_show_master_mode_avail()
358 	buf[len - 1] = '\n';  in stm32_tt_show_master_mode_avail()
394 	list_for_each_entry(tr, &priv->tr_list, alloc_list)  in stm32_unregister_iio_triggers()
401 	const char * const *cur = priv->triggers;  in stm32_register_iio_triggers()
403 	INIT_LIST_HEAD(&priv->tr_list);  in stm32_register_iio_triggers()
410 		if (cur_is_trgo2 && !priv->has_trgo2) {  in stm32_register_iio_triggers()
415 		trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur);  in stm32_register_iio_triggers()
417 			return -ENOMEM;  in stm32_register_iio_triggers()
419 		trig->dev.parent = priv->dev->parent;  in stm32_register_iio_triggers()
420 		trig->ops = &timer_trigger_ops;  in stm32_register_iio_triggers()
427 			trig->dev.groups = stm32_trigger_attr_groups;  in stm32_register_iio_triggers()
437 		list_add_tail(&trig->alloc_list, &priv->tr_list);  in stm32_register_iio_triggers()
453 		regmap_read(priv->regmap, TIM_CNT, &dat);  in stm32_counter_read_raw()
458 		regmap_read(priv->regmap, TIM_CR1, &dat);  in stm32_counter_read_raw()
463 		regmap_read(priv->regmap, TIM_SMCR, &dat);  in stm32_counter_read_raw()
476 	return -EINVAL;  in stm32_counter_read_raw()
487 		return regmap_write(priv->regmap, TIM_CNT, val);  in stm32_counter_write_raw()
491 		return -EINVAL;  in stm32_counter_write_raw()
494 		mutex_lock(&priv->lock);  in stm32_counter_write_raw()
496 			if (!priv->enabled) {  in stm32_counter_write_raw()
497 				priv->enabled = true;  in stm32_counter_write_raw()
498 				clk_enable(priv->clk);  in stm32_counter_write_raw()
500 			regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,  in stm32_counter_write_raw()
503 			regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,  in stm32_counter_write_raw()
505 			if (priv->enabled) {  in stm32_counter_write_raw()
506 				priv->enabled = false;  in stm32_counter_write_raw()
507 				clk_disable(priv->clk);  in stm32_counter_write_raw()
510 		mutex_unlock(&priv->lock);  in stm32_counter_write_raw()
514 	return -EINVAL;  in stm32_counter_write_raw()
521 	const char * const *cur = priv->valids;  in stm32_counter_validate_trigger()
525 		return -EINVAL;  in stm32_counter_validate_trigger()
528 		if (!strncmp(trig->name, *cur, strlen(trig->name))) {  in stm32_counter_validate_trigger()
529 			regmap_update_bits(priv->regmap,  in stm32_counter_validate_trigger()
538 	return -EINVAL;  in stm32_counter_validate_trigger()
557 	regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, TIM_SMCR_SMS);  in stm32_set_trigger_mode()
568 	regmap_read(priv->regmap, TIM_SMCR, &smcr);  in stm32_get_trigger_mode()
570 	return (smcr & TIM_SMCR_SMS) == TIM_SMCR_SMS ? 0 : -EINVAL;  in stm32_get_trigger_mode()
597 	return -EINVAL;  in stm32_enable_mode2sms()
611 	 * enable counter clock, so it can use it. Keeps it in sync with CEN.  in stm32_set_enable_mode()
613 	mutex_lock(&priv->lock);  in stm32_set_enable_mode()
614 	if (sms == 6 && !priv->enabled) {  in stm32_set_enable_mode()
615 		clk_enable(priv->clk);  in stm32_set_enable_mode()
616 		priv->enabled = true;  in stm32_set_enable_mode()
618 	mutex_unlock(&priv->lock);  in stm32_set_enable_mode()
620 	regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);  in stm32_set_enable_mode()
636 	return -EINVAL;  in stm32_sms2enable_mode()
645 	regmap_read(priv->regmap, TIM_SMCR, &smcr);  in stm32_get_enable_mode()
666 	regmap_read(priv->regmap, TIM_ARR, &arr);  in stm32_count_get_preset()
685 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);  in stm32_count_set_preset()
686 	regmap_write(priv->regmap, TIM_ARR, preset);  in stm32_count_set_preset()
725 	indio_dev->name = dev_name(dev);  in stm32_setup_counter_device()
726 	indio_dev->info = &stm32_trigger_info;  in stm32_setup_counter_device()
727 	indio_dev->modes = INDIO_HARDWARE_TRIGGERED;  in stm32_setup_counter_device()
728 	indio_dev->num_channels = 1;  in stm32_setup_counter_device()
729 	indio_dev->channels = &stm32_trigger_channel;  in stm32_setup_counter_device()
742  * return true if the trigger is a valid stm32 iio timer trigger
747 	return (trig->ops == &timer_trigger_ops);  in is_stm32_timer_trigger()
757 	 * timer supports it.  in stm32_timer_detect_trgo2()
759 	regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, TIM_CR2_MMS2);  in stm32_timer_detect_trgo2()
760 	regmap_read(priv->regmap, TIM_CR2, &val);  in stm32_timer_detect_trgo2()
761 	regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);  in stm32_timer_detect_trgo2()
762 	priv->has_trgo2 = !!val;  in stm32_timer_detect_trgo2()
767 	struct device *dev = &pdev->dev;  in stm32_timer_trigger_probe()
769 	struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);  in stm32_timer_trigger_probe()
774 	if (of_property_read_u32(dev->of_node, "reg", &index))  in stm32_timer_trigger_probe()
775 		return -EINVAL;  in stm32_timer_trigger_probe()
778 		of_match_device(dev->driver->of_match_table, dev)->data;  in stm32_timer_trigger_probe()
781 	    index >= cfg->num_valids_table)  in stm32_timer_trigger_probe()
782 		return -EINVAL;  in stm32_timer_trigger_probe()
785 	if (*cfg->valids_table[index])  in stm32_timer_trigger_probe()
791 		return -ENOMEM;  in stm32_timer_trigger_probe()
793 	priv->dev = dev;  in stm32_timer_trigger_probe()
794 	priv->regmap = ddata->regmap;  in stm32_timer_trigger_probe()
795 	priv->clk = ddata->clk;  in stm32_timer_trigger_probe()
796 	priv->max_arr = ddata->max_arr;  in stm32_timer_trigger_probe()
797 	priv->triggers = triggers_table[index];  in stm32_timer_trigger_probe()
798 	priv->valids = cfg->valids_table[index];  in stm32_timer_trigger_probe()
800 	mutex_init(&priv->lock);  in stm32_timer_trigger_probe()
819 	/* Check if nobody else use the timer, then disable it */  in stm32_timer_trigger_remove()
820 	regmap_read(priv->regmap, TIM_CCER, &val);  in stm32_timer_trigger_remove()
822 		regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);  in stm32_timer_trigger_remove()
824 	if (priv->enabled)  in stm32_timer_trigger_remove()
825 		clk_disable(priv->clk);  in stm32_timer_trigger_remove()
834 	/* Only take care of enabled timer: don't disturb other MFD child */  in stm32_timer_trigger_suspend()
835 	if (priv->enabled) {  in stm32_timer_trigger_suspend()
837 		regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1);  in stm32_timer_trigger_suspend()
838 		regmap_read(priv->regmap, TIM_CR2, &priv->bak.cr2);  in stm32_timer_trigger_suspend()
839 		regmap_read(priv->regmap, TIM_PSC, &priv->bak.psc);  in stm32_timer_trigger_suspend()
840 		regmap_read(priv->regmap, TIM_ARR, &priv->bak.arr);  in stm32_timer_trigger_suspend()
841 		regmap_read(priv->regmap, TIM_CNT, &priv->bak.cnt);  in stm32_timer_trigger_suspend()
842 		regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr);  in stm32_timer_trigger_suspend()
844 		/* Disable the timer */  in stm32_timer_trigger_suspend()
845 		regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);  in stm32_timer_trigger_suspend()
846 		clk_disable(priv->clk);  in stm32_timer_trigger_suspend()
857 	if (priv->enabled) {  in stm32_timer_trigger_resume()
858 		ret = clk_enable(priv->clk);  in stm32_timer_trigger_resume()
863 		regmap_write(priv->regmap, TIM_SMCR, priv->bak.smcr);  in stm32_timer_trigger_resume()
864 		regmap_write(priv->regmap, TIM_CR2, priv->bak.cr2);  in stm32_timer_trigger_resume()
867 		regmap_write(priv->regmap, TIM_PSC, priv->bak.psc);  in stm32_timer_trigger_resume()
868 		regmap_write(priv->regmap, TIM_ARR, priv->bak.arr);  in stm32_timer_trigger_resume()
869 		regmap_write(priv->regmap, TIM_CNT, priv->bak.cnt);  in stm32_timer_trigger_resume()
871 		/* Also re-enables the timer */  in stm32_timer_trigger_resume()
872 		regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1);  in stm32_timer_trigger_resume()
894 		.compatible = "st,stm32-timer-trigger",
897 		.compatible = "st,stm32h7-timer-trigger",
908 		.name = "stm32-timer-trigger",
915 MODULE_ALIAS("platform: stm32-timer-trigger");
916 MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver");