Lines Matching +full:sleep +full:- +full:map
1 // SPDX-License-Identifier: GPL-2.0-or-later
91 /* 3-axis accel + temperature */
106 unsigned int sleep; in inv_icm42600_accel_update_scan_mode() local
109 mutex_lock(&st->lock); in inv_icm42600_accel_update_scan_mode()
130 ret = inv_icm42600_buffer_set_fifo_en(st, fifo_en | st->fifo.en); in inv_icm42600_accel_update_scan_mode()
137 mutex_unlock(&st->lock); in inv_icm42600_accel_update_scan_mode()
138 /* sleep maximum required time */ in inv_icm42600_accel_update_scan_mode()
140 sleep = sleep_accel; in inv_icm42600_accel_update_scan_mode()
142 sleep = sleep_temp; in inv_icm42600_accel_update_scan_mode()
143 if (sleep) in inv_icm42600_accel_update_scan_mode()
144 msleep(sleep); in inv_icm42600_accel_update_scan_mode()
152 struct device *dev = regmap_get_device(st->map); in inv_icm42600_accel_read_sensor()
158 if (chan->type != IIO_ACCEL) in inv_icm42600_accel_read_sensor()
159 return -EINVAL; in inv_icm42600_accel_read_sensor()
161 switch (chan->channel2) { in inv_icm42600_accel_read_sensor()
172 return -EINVAL; in inv_icm42600_accel_read_sensor()
176 mutex_lock(&st->lock); in inv_icm42600_accel_read_sensor()
185 data = (__be16 *)&st->buffer[0]; in inv_icm42600_accel_read_sensor()
186 ret = regmap_bulk_read(st->map, reg, data, sizeof(*data)); in inv_icm42600_accel_read_sensor()
192 ret = -EINVAL; in inv_icm42600_accel_read_sensor()
194 mutex_unlock(&st->lock); in inv_icm42600_accel_read_sensor()
202 /* +/- 16G => 0.004788403 m/s-2 */
205 /* +/- 8G => 0.002394202 m/s-2 */
208 /* +/- 4G => 0.001197101 m/s-2 */
211 /* +/- 2G => 0.000598550 m/s-2 */
221 idx = st->conf.accel.fs; in inv_icm42600_accel_read_scale()
231 struct device *dev = regmap_get_device(st->map); in inv_icm42600_accel_write_scale()
242 return -EINVAL; in inv_icm42600_accel_write_scale()
247 mutex_lock(&st->lock); in inv_icm42600_accel_write_scale()
251 mutex_unlock(&st->lock); in inv_icm42600_accel_write_scale()
295 odr = st->conf.accel.odr; in inv_icm42600_accel_read_odr()
302 return -EINVAL; in inv_icm42600_accel_read_odr()
315 struct device *dev = regmap_get_device(st->map); in inv_icm42600_accel_write_odr()
326 return -EINVAL; in inv_icm42600_accel_write_odr()
331 mutex_lock(&st->lock); in inv_icm42600_accel_write_odr()
345 mutex_unlock(&st->lock); in inv_icm42600_accel_write_odr()
354 * Value is limited to +/-1g coded on 12 bits signed. Step is 0.5mg.
357 -10, 42010, /* min: -10.042010 m/s² */
366 struct device *dev = regmap_get_device(st->map); in inv_icm42600_accel_read_offset()
374 if (chan->type != IIO_ACCEL) in inv_icm42600_accel_read_offset()
375 return -EINVAL; in inv_icm42600_accel_read_offset()
377 switch (chan->channel2) { in inv_icm42600_accel_read_offset()
388 return -EINVAL; in inv_icm42600_accel_read_offset()
392 mutex_lock(&st->lock); in inv_icm42600_accel_read_offset()
394 ret = regmap_bulk_read(st->map, reg, st->buffer, sizeof(data)); in inv_icm42600_accel_read_offset()
395 memcpy(data, st->buffer, sizeof(data)); in inv_icm42600_accel_read_offset()
397 mutex_unlock(&st->lock); in inv_icm42600_accel_read_offset()
404 switch (chan->channel2) { in inv_icm42600_accel_read_offset()
415 return -EINVAL; in inv_icm42600_accel_read_offset()
426 /* for rounding, add + or - divisor (10000) divided by 2 */ in inv_icm42600_accel_read_offset()
430 val64 -= 10000LL / 2LL; in inv_icm42600_accel_read_offset()
442 struct device *dev = regmap_get_device(st->map); in inv_icm42600_accel_write_offset()
449 if (chan->type != IIO_ACCEL) in inv_icm42600_accel_write_offset()
450 return -EINVAL; in inv_icm42600_accel_write_offset()
452 switch (chan->channel2) { in inv_icm42600_accel_write_offset()
463 return -EINVAL; in inv_icm42600_accel_write_offset()
466 /* inv_icm42600_accel_calibbias: min - step - max in micro */ in inv_icm42600_accel_write_offset()
473 return -EINVAL; in inv_icm42600_accel_write_offset()
483 /* for rounding, add + or - divisor (9806650 * 5) divided by 2 */ in inv_icm42600_accel_write_offset()
487 val64 -= 9806650 * 5 / 2; in inv_icm42600_accel_write_offset()
491 if (offset < -2048) in inv_icm42600_accel_write_offset()
492 offset = -2048; in inv_icm42600_accel_write_offset()
497 mutex_lock(&st->lock); in inv_icm42600_accel_write_offset()
499 switch (chan->channel2) { in inv_icm42600_accel_write_offset()
502 ret = regmap_read(st->map, INV_ICM42600_REG_OFFSET_USER4, in inv_icm42600_accel_write_offset()
506 st->buffer[0] = ((offset & 0xF00) >> 4) | (regval & 0x0F); in inv_icm42600_accel_write_offset()
507 st->buffer[1] = offset & 0xFF; in inv_icm42600_accel_write_offset()
511 ret = regmap_read(st->map, INV_ICM42600_REG_OFFSET_USER7, in inv_icm42600_accel_write_offset()
515 st->buffer[0] = offset & 0xFF; in inv_icm42600_accel_write_offset()
516 st->buffer[1] = ((offset & 0xF00) >> 8) | (regval & 0xF0); in inv_icm42600_accel_write_offset()
520 ret = regmap_read(st->map, INV_ICM42600_REG_OFFSET_USER7, in inv_icm42600_accel_write_offset()
524 st->buffer[0] = ((offset & 0xF00) >> 4) | (regval & 0x0F); in inv_icm42600_accel_write_offset()
525 st->buffer[1] = offset & 0xFF; in inv_icm42600_accel_write_offset()
528 ret = -EINVAL; in inv_icm42600_accel_write_offset()
532 ret = regmap_bulk_write(st->map, reg, st->buffer, 2); in inv_icm42600_accel_write_offset()
535 mutex_unlock(&st->lock); in inv_icm42600_accel_write_offset()
549 switch (chan->type) { in inv_icm42600_accel_read_raw()
555 return -EINVAL; in inv_icm42600_accel_read_raw()
576 return -EINVAL; in inv_icm42600_accel_read_raw()
585 if (chan->type != IIO_ACCEL) in inv_icm42600_accel_read_avail()
586 return -EINVAL; in inv_icm42600_accel_read_avail()
604 return -EINVAL; in inv_icm42600_accel_read_avail()
615 if (chan->type != IIO_ACCEL) in inv_icm42600_accel_write_raw()
616 return -EINVAL; in inv_icm42600_accel_write_raw()
636 return -EINVAL; in inv_icm42600_accel_write_raw()
644 if (chan->type != IIO_ACCEL) in inv_icm42600_accel_write_raw_get_fmt()
645 return -EINVAL; in inv_icm42600_accel_write_raw_get_fmt()
655 return -EINVAL; in inv_icm42600_accel_write_raw_get_fmt()
665 mutex_lock(&st->lock); in inv_icm42600_accel_hwfifo_set_watermark()
667 st->fifo.watermark.accel = val; in inv_icm42600_accel_hwfifo_set_watermark()
670 mutex_unlock(&st->lock); in inv_icm42600_accel_hwfifo_set_watermark()
684 mutex_lock(&st->lock); in inv_icm42600_accel_hwfifo_flush()
688 ret = st->fifo.nb.accel; in inv_icm42600_accel_hwfifo_flush()
690 mutex_unlock(&st->lock); in inv_icm42600_accel_hwfifo_flush()
708 struct device *dev = regmap_get_device(st->map); in inv_icm42600_accel_init()
715 name = devm_kasprintf(dev, GFP_KERNEL, "%s-accel", st->name); in inv_icm42600_accel_init()
717 return ERR_PTR(-ENOMEM); in inv_icm42600_accel_init()
721 return ERR_PTR(-ENOMEM); in inv_icm42600_accel_init()
725 return ERR_PTR(-ENOMEM); in inv_icm42600_accel_init()
728 inv_icm42600_timestamp_init(ts, inv_icm42600_odr_to_period(st->conf.accel.odr)); in inv_icm42600_accel_init()
731 indio_dev->name = name; in inv_icm42600_accel_init()
732 indio_dev->info = &inv_icm42600_accel_info; in inv_icm42600_accel_init()
733 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE; in inv_icm42600_accel_init()
734 indio_dev->channels = inv_icm42600_accel_channels; in inv_icm42600_accel_init()
735 indio_dev->num_channels = ARRAY_SIZE(inv_icm42600_accel_channels); in inv_icm42600_accel_init()
736 indio_dev->available_scan_masks = inv_icm42600_accel_scan_masks; in inv_icm42600_accel_init()
737 indio_dev->setup_ops = &inv_icm42600_buffer_ops; in inv_icm42600_accel_init()
761 for (i = 0, no = 0; i < st->fifo.count; i += size, ++no) { in inv_icm42600_accel_parse_fifo()
762 size = inv_icm42600_fifo_decode_packet(&st->fifo.data[i], in inv_icm42600_accel_parse_fifo()
774 inv_icm42600_timestamp_apply_odr(ts, st->fifo.period, in inv_icm42600_accel_parse_fifo()
775 st->fifo.nb.total, no); in inv_icm42600_accel_parse_fifo()