Lines Matching +full:stm32 +full:- +full:dma
1 // SPDX-License-Identifier: GPL-2.0
3 * This file is part of STM32 ADC driver
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
11 #include <linux/dma-mapping.h>
15 #include <linux/iio/timer/stm32-lptim-trigger.h>
16 #include <linux/iio/timer/stm32-timer-trigger.h>
29 #include "stm32-adc-core.h"
55 /* extsel - trigger mux selection value */
81 * struct stm32_adc_trig_info - ADC trigger info
91 * struct stm32_adc_calib - optional adc calibration data
105 * struct stm32_adc_regs - stm32 ADC misc registers & bitfield desc
117 * struct stm32_adc_regspec - stm32 registers definition
147 * struct stm32_adc_cfg - stm32 compatible configuration data
153 * @prepare: optional prepare routine (power-up, enable)
156 * @unprepare: optional unprepare routine (disable, power-down)
167 void (*start_conv)(struct iio_dev *, bool dma);
175 * struct stm32_adc - private data of each ADC IIO instance
188 * @dma_chan: dma channel
189 * @rx_buf: dma rx buffer cpu address
190 * @rx_dma_buf: dma rx buffer bus address
191 * @rx_buf_sz: dma rx buffer size
192 * @difsel: bitmask to set single-ended/differential channel
228 * struct stm32_adc_info - stm32 ADC, per instance config data
264 * stm32f4_sq - describe regular sequence registers
265 * - L: sequence len (register & bit field)
266 * - SQ1..SQ16: sequence entries (register & bit field)
311 * stm32f4_smp_bits[] - describe sampling time register index & bit fields
404 * stm32h7_smp_bits - describe sampling time register index & bit fields
453 * STM32 ADC registers access routines
454 * @adc: stm32 adc instance
462 return readl_relaxed(adc->common->base + adc->offset + reg); in stm32_adc_readl()
473 return readw_relaxed(adc->common->base + adc->offset + reg); in stm32_adc_readw()
478 writel_relaxed(val, adc->common->base + adc->offset + reg); in stm32_adc_writel()
485 spin_lock_irqsave(&adc->lock, flags); in stm32_adc_set_bits()
487 spin_unlock_irqrestore(&adc->lock, flags); in stm32_adc_set_bits()
494 spin_lock_irqsave(&adc->lock, flags); in stm32_adc_clr_bits()
496 spin_unlock_irqrestore(&adc->lock, flags); in stm32_adc_clr_bits()
500 * stm32_adc_conv_irq_enable() - Enable end of conversion interrupt
501 * @adc: stm32 adc instance
505 stm32_adc_set_bits(adc, adc->cfg->regs->ier_eoc.reg, in stm32_adc_conv_irq_enable()
506 adc->cfg->regs->ier_eoc.mask); in stm32_adc_conv_irq_enable()
510 * stm32_adc_conv_irq_disable() - Disable end of conversion interrupt
511 * @adc: stm32 adc instance
515 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_eoc.reg, in stm32_adc_conv_irq_disable()
516 adc->cfg->regs->ier_eoc.mask); in stm32_adc_conv_irq_disable()
521 stm32_adc_set_bits(adc, adc->cfg->regs->ier_ovr.reg, in stm32_adc_ovr_irq_enable()
522 adc->cfg->regs->ier_ovr.mask); in stm32_adc_ovr_irq_enable()
527 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_ovr.reg, in stm32_adc_ovr_irq_disable()
528 adc->cfg->regs->ier_ovr.mask); in stm32_adc_ovr_irq_disable()
533 const struct stm32_adc_regs *res = &adc->cfg->regs->res; in stm32_adc_set_res()
536 val = stm32_adc_readl(adc, res->reg); in stm32_adc_set_res()
537 val = (val & ~res->mask) | (adc->res << res->shift); in stm32_adc_set_res()
538 stm32_adc_writel(adc, res->reg, val); in stm32_adc_set_res()
546 if (adc->cfg->unprepare) in stm32_adc_hw_stop()
547 adc->cfg->unprepare(indio_dev); in stm32_adc_hw_stop()
549 if (adc->clk) in stm32_adc_hw_stop()
550 clk_disable_unprepare(adc->clk); in stm32_adc_hw_stop()
561 if (adc->clk) { in stm32_adc_hw_start()
562 ret = clk_prepare_enable(adc->clk); in stm32_adc_hw_start()
569 if (adc->cfg->prepare) { in stm32_adc_hw_start()
570 ret = adc->cfg->prepare(indio_dev); in stm32_adc_hw_start()
578 if (adc->clk) in stm32_adc_hw_start()
579 clk_disable_unprepare(adc->clk); in stm32_adc_hw_start()
585 * stm32f4_adc_start_conv() - Start conversions for regular channels.
587 * @dma: use dma to transfer conversion result
590 * Also take care of normal or DMA mode. Circular DMA may be used for regular
592 * DR read instead (e.g. read_raw, or triggered buffer mode without DMA).
594 static void stm32f4_adc_start_conv(struct iio_dev *indio_dev, bool dma) in stm32f4_adc_start_conv() argument
600 if (dma) in stm32f4_adc_start_conv()
606 /* Wait for Power-up time (tSTAB from datasheet) */ in stm32f4_adc_start_conv()
630 stm32_adc_clr_bits(adc, adc->cfg->regs->isr_eoc.reg, msk); in stm32f4_adc_irq_clear()
633 static void stm32h7_adc_start_conv(struct iio_dev *indio_dev, bool dma) in stm32h7_adc_start_conv() argument
640 if (dma) in stm32h7_adc_start_conv()
645 spin_lock_irqsave(&adc->lock, flags); in stm32h7_adc_start_conv()
649 spin_unlock_irqrestore(&adc->lock, flags); in stm32h7_adc_start_conv()
666 dev_warn(&indio_dev->dev, "stop failed\n"); in stm32h7_adc_stop_conv()
675 stm32_adc_set_bits(adc, adc->cfg->regs->isr_eoc.reg, msk); in stm32h7_adc_irq_clear()
688 if (adc->common->rate > STM32H7_BOOST_CLKRATE) in stm32h7_adc_exit_pwr_down()
692 if (!adc->cfg->has_vregready) { in stm32h7_adc_exit_pwr_down()
702 dev_err(&indio_dev->dev, "Failed to exit power down\n"); in stm32h7_adc_exit_pwr_down()
730 dev_err(&indio_dev->dev, "Failed to enable ADC\n"); in stm32h7_adc_enable()
751 dev_warn(&indio_dev->dev, "Failed to disable\n"); in stm32h7_adc_disable()
755 * stm32h7_adc_read_selfcalib() - read calibration shadow regs, save result
767 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) { in stm32h7_adc_read_selfcalib()
776 dev_err(&indio_dev->dev, "Failed to read calfact\n"); in stm32h7_adc_read_selfcalib()
781 adc->cal.lincalfact[i] = (val & STM32H7_LINCALFACT_MASK); in stm32h7_adc_read_selfcalib()
782 adc->cal.lincalfact[i] >>= STM32H7_LINCALFACT_SHIFT; in stm32h7_adc_read_selfcalib()
789 adc->cal.calfact_s = (val & STM32H7_CALFACT_S_MASK); in stm32h7_adc_read_selfcalib()
790 adc->cal.calfact_s >>= STM32H7_CALFACT_S_SHIFT; in stm32h7_adc_read_selfcalib()
791 adc->cal.calfact_d = (val & STM32H7_CALFACT_D_MASK); in stm32h7_adc_read_selfcalib()
792 adc->cal.calfact_d >>= STM32H7_CALFACT_D_SHIFT; in stm32h7_adc_read_selfcalib()
793 adc->cal.calibrated = true; in stm32h7_adc_read_selfcalib()
799 * stm32h7_adc_restore_selfcalib() - Restore saved self-calibration result
801 * Note: ADC must be enabled, with no on-going conversions.
809 val = (adc->cal.calfact_s << STM32H7_CALFACT_S_SHIFT) | in stm32h7_adc_restore_selfcalib()
810 (adc->cal.calfact_d << STM32H7_CALFACT_D_SHIFT); in stm32h7_adc_restore_selfcalib()
814 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) { in stm32h7_adc_restore_selfcalib()
820 val = adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT; in stm32h7_adc_restore_selfcalib()
827 dev_err(&indio_dev->dev, "Failed to write calfact\n"); in stm32h7_adc_restore_selfcalib()
833 * - It ensures bits LINCALRDYW[6..1] are kept cleared in stm32h7_adc_restore_selfcalib()
835 * - BTW, bit clear triggers a read, then check data has been in stm32h7_adc_restore_selfcalib()
843 dev_err(&indio_dev->dev, "Failed to read calfact\n"); in stm32h7_adc_restore_selfcalib()
847 if (val != adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT) { in stm32h7_adc_restore_selfcalib()
848 dev_err(&indio_dev->dev, "calfact not consistent\n"); in stm32h7_adc_restore_selfcalib()
849 return -EIO; in stm32h7_adc_restore_selfcalib()
861 * - low clock frequency
862 * - maximum prescalers
864 * - 131,072 ADC clock cycle for the linear calibration
865 * - 20 ADC clock cycle for the offset calibration
872 * stm32h7_adc_selfcalib() - Procedure to calibrate ADC
882 if (adc->cal.calibrated) in stm32h7_adc_selfcalib()
887 * - Offset calibration for single ended inputs in stm32h7_adc_selfcalib()
888 * - No linearity calibration (do it later, before reading it) in stm32h7_adc_selfcalib()
899 dev_err(&indio_dev->dev, "calibration failed\n"); in stm32h7_adc_selfcalib()
905 * - Offset calibration for differential input in stm32h7_adc_selfcalib()
906 * - Linearity calibration (needs to be done only once for single/diff) in stm32h7_adc_selfcalib()
916 dev_err(&indio_dev->dev, "calibration failed\n"); in stm32h7_adc_selfcalib()
928 * stm32h7_adc_prepare() - Leave power down mode to enable ADC.
934 * Pre-select channels that may be used in PCSEL (required by input MUX / IO):
935 * - Only one input is selected for single ended (e.g. 'vinp')
936 * - Two inputs are selected for differential channels (e.g. 'vinp' & 'vinn')
952 stm32_adc_writel(adc, STM32H7_ADC_DIFSEL, adc->difsel); in stm32h7_adc_prepare()
966 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, adc->pcsel); in stm32h7_adc_prepare()
987 * stm32_adc_conf_scan_seq() - Build regular channels scan sequence
1001 const struct stm32_adc_regs *sqr = adc->cfg->regs->sqr; in stm32_adc_conf_scan_seq()
1007 stm32_adc_writel(adc, adc->cfg->regs->smpr[0], adc->smpr_val[0]); in stm32_adc_conf_scan_seq()
1008 stm32_adc_writel(adc, adc->cfg->regs->smpr[1], adc->smpr_val[1]); in stm32_adc_conf_scan_seq()
1010 for_each_set_bit(bit, scan_mask, indio_dev->masklength) { in stm32_adc_conf_scan_seq()
1011 chan = indio_dev->channels + bit; in stm32_adc_conf_scan_seq()
1018 return -EINVAL; in stm32_adc_conf_scan_seq()
1020 dev_dbg(&indio_dev->dev, "%s chan %d to SQ%d\n", in stm32_adc_conf_scan_seq()
1021 __func__, chan->channel, i); in stm32_adc_conf_scan_seq()
1025 val |= chan->channel << sqr[i].shift; in stm32_adc_conf_scan_seq()
1030 return -EINVAL; in stm32_adc_conf_scan_seq()
1035 val |= ((i - 1) << sqr[0].shift); in stm32_adc_conf_scan_seq()
1042 * stm32_adc_get_trig_extsel() - Get external trigger selection
1046 * Returns trigger extsel value, if trig matches, -EINVAL otherwise.
1054 /* lookup triggers registered by stm32 timer trigger driver */ in stm32_adc_get_trig_extsel()
1055 for (i = 0; adc->cfg->trigs[i].name; i++) { in stm32_adc_get_trig_extsel()
1057 * Checking both stm32 timer trigger type and trig name in stm32_adc_get_trig_extsel()
1062 !strcmp(adc->cfg->trigs[i].name, trig->name)) { in stm32_adc_get_trig_extsel()
1063 return adc->cfg->trigs[i].extsel; in stm32_adc_get_trig_extsel()
1067 return -EINVAL; in stm32_adc_get_trig_extsel()
1071 * stm32_adc_set_trig() - Set a regular trigger
1076 * - if HW trigger disabled (e.g. trig == NULL, conversion launched by sw)
1077 * - if HW trigger enabled, set source & polarity
1094 exten = adc->trigger_polarity + STM32_EXTEN_HWTRIG_RISING_EDGE; in stm32_adc_set_trig()
1097 spin_lock_irqsave(&adc->lock, flags); in stm32_adc_set_trig()
1098 val = stm32_adc_readl(adc, adc->cfg->regs->exten.reg); in stm32_adc_set_trig()
1099 val &= ~(adc->cfg->regs->exten.mask | adc->cfg->regs->extsel.mask); in stm32_adc_set_trig()
1100 val |= exten << adc->cfg->regs->exten.shift; in stm32_adc_set_trig()
1101 val |= extsel << adc->cfg->regs->extsel.shift; in stm32_adc_set_trig()
1102 stm32_adc_writel(adc, adc->cfg->regs->exten.reg, val); in stm32_adc_set_trig()
1103 spin_unlock_irqrestore(&adc->lock, flags); in stm32_adc_set_trig()
1114 adc->trigger_polarity = type; in stm32_adc_set_trig_pol()
1124 return adc->trigger_polarity; in stm32_adc_get_trig_pol()
1128 "rising-edge", "falling-edge", "both-edges",
1139 * stm32_adc_single_conv() - Performs a single conversion
1145 * - Apply sampling time settings
1146 * - Program sequencer with one channel (e.g. in SQ1 with len = 1)
1147 * - Use SW trigger
1148 * - Start conversion, then wait for interrupt completion.
1155 struct device *dev = indio_dev->dev.parent; in stm32_adc_single_conv()
1156 const struct stm32_adc_regspec *regs = adc->cfg->regs; in stm32_adc_single_conv()
1161 reinit_completion(&adc->completion); in stm32_adc_single_conv()
1163 adc->bufi = 0; in stm32_adc_single_conv()
1172 stm32_adc_writel(adc, regs->smpr[0], adc->smpr_val[0]); in stm32_adc_single_conv()
1173 stm32_adc_writel(adc, regs->smpr[1], adc->smpr_val[1]); in stm32_adc_single_conv()
1176 val = stm32_adc_readl(adc, regs->sqr[1].reg); in stm32_adc_single_conv()
1177 val &= ~regs->sqr[1].mask; in stm32_adc_single_conv()
1178 val |= chan->channel << regs->sqr[1].shift; in stm32_adc_single_conv()
1179 stm32_adc_writel(adc, regs->sqr[1].reg, val); in stm32_adc_single_conv()
1182 stm32_adc_clr_bits(adc, regs->sqr[0].reg, regs->sqr[0].mask); in stm32_adc_single_conv()
1185 stm32_adc_clr_bits(adc, regs->exten.reg, regs->exten.mask); in stm32_adc_single_conv()
1189 adc->cfg->start_conv(indio_dev, false); in stm32_adc_single_conv()
1192 &adc->completion, STM32_ADC_TIMEOUT); in stm32_adc_single_conv()
1194 ret = -ETIMEDOUT; in stm32_adc_single_conv()
1198 *res = adc->buffer[0]; in stm32_adc_single_conv()
1202 adc->cfg->stop_conv(indio_dev); in stm32_adc_single_conv()
1224 if (chan->type == IIO_VOLTAGE) in stm32_adc_read_raw()
1227 ret = -EINVAL; in stm32_adc_read_raw()
1232 if (chan->differential) { in stm32_adc_read_raw()
1233 *val = adc->common->vref_mv * 2; in stm32_adc_read_raw()
1234 *val2 = chan->scan_type.realbits; in stm32_adc_read_raw()
1236 *val = adc->common->vref_mv; in stm32_adc_read_raw()
1237 *val2 = chan->scan_type.realbits; in stm32_adc_read_raw()
1242 if (chan->differential) in stm32_adc_read_raw()
1244 *val = -((1 << chan->scan_type.realbits) / 2); in stm32_adc_read_raw()
1250 return -EINVAL; in stm32_adc_read_raw()
1258 adc->cfg->irq_clear(indio_dev, msk); in stm32_adc_irq_clear()
1265 const struct stm32_adc_regspec *regs = adc->cfg->regs; in stm32_adc_threaded_isr()
1266 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg); in stm32_adc_threaded_isr()
1267 u32 mask = stm32_adc_readl(adc, regs->ier_eoc.reg); in stm32_adc_threaded_isr()
1270 if (status & regs->isr_ovr.mask) { in stm32_adc_threaded_isr()
1276 adc->cfg->stop_conv(indio_dev); in stm32_adc_threaded_isr()
1277 stm32_adc_irq_clear(indio_dev, regs->isr_ovr.mask); in stm32_adc_threaded_isr()
1278 dev_err(&indio_dev->dev, "Overrun, stopping: restart needed\n"); in stm32_adc_threaded_isr()
1283 dev_err_ratelimited(&indio_dev->dev, in stm32_adc_threaded_isr()
1294 const struct stm32_adc_regspec *regs = adc->cfg->regs; in stm32_adc_isr()
1295 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg); in stm32_adc_isr()
1296 u32 mask = stm32_adc_readl(adc, regs->ier_eoc.reg); in stm32_adc_isr()
1301 if (status & regs->isr_ovr.mask) { in stm32_adc_isr()
1307 * re-enabling it (e.g. write 0, then 1 to buffer/enable). in stm32_adc_isr()
1314 if (status & regs->isr_eoc.mask) { in stm32_adc_isr()
1316 adc->buffer[adc->bufi] = stm32_adc_readw(adc, regs->dr); in stm32_adc_isr()
1318 adc->bufi++; in stm32_adc_isr()
1319 if (adc->bufi >= adc->num_conv) { in stm32_adc_isr()
1321 iio_trigger_poll(indio_dev->trig); in stm32_adc_isr()
1324 complete(&adc->completion); in stm32_adc_isr()
1333 * stm32_adc_validate_trigger() - validate trigger for stm32 adc
1337 * Returns: 0 if trig matches one of the triggers registered by stm32 adc
1338 * driver, -EINVAL otherwise.
1343 return stm32_adc_get_trig_extsel(indio_dev, trig) < 0 ? -EINVAL : 0; in stm32_adc_validate_trigger()
1353 * dma cyclic transfers are used, buffer is split into two periods. in stm32_adc_set_watermark()
1355 * - always one buffer (period) dma is working on in stm32_adc_set_watermark()
1356 * - one buffer (period) driver can push with iio_trigger_poll(). in stm32_adc_set_watermark()
1359 adc->rx_buf_sz = min(rx_buf_sz, watermark * 2 * adc->num_conv); in stm32_adc_set_watermark()
1368 struct device *dev = indio_dev->dev.parent; in stm32_adc_update_scan_mode()
1377 adc->num_conv = bitmap_weight(scan_mask, indio_dev->masklength); in stm32_adc_update_scan_mode()
1391 for (i = 0; i < indio_dev->num_channels; i++) in stm32_adc_of_xlate()
1392 if (indio_dev->channels[i].channel == iiospec->args[0]) in stm32_adc_of_xlate()
1395 return -EINVAL; in stm32_adc_of_xlate()
1399 * stm32_adc_debugfs_reg_access - read or write register value
1417 struct device *dev = indio_dev->dev.parent; in stm32_adc_debugfs_reg_access()
1451 status = dmaengine_tx_status(adc->dma_chan, in stm32_adc_dma_residue()
1452 adc->dma_chan->cookie, in stm32_adc_dma_residue()
1456 unsigned int i = adc->rx_buf_sz - state.residue; in stm32_adc_dma_residue()
1460 if (i >= adc->bufi) in stm32_adc_dma_residue()
1461 size = i - adc->bufi; in stm32_adc_dma_residue()
1463 size = adc->rx_buf_sz + i - adc->bufi; in stm32_adc_dma_residue()
1478 * In DMA mode the trigger services of IIO are not used in stm32_adc_dma_buffer_done()
1482 * transfers are performed directly in DMA callback instead. in stm32_adc_dma_buffer_done()
1484 * may sleep, in an atomic context (DMA irq handler context). in stm32_adc_dma_buffer_done()
1486 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi); in stm32_adc_dma_buffer_done()
1488 while (residue >= indio_dev->scan_bytes) { in stm32_adc_dma_buffer_done()
1489 u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi]; in stm32_adc_dma_buffer_done()
1493 residue -= indio_dev->scan_bytes; in stm32_adc_dma_buffer_done()
1494 adc->bufi += indio_dev->scan_bytes; in stm32_adc_dma_buffer_done()
1495 if (adc->bufi >= adc->rx_buf_sz) in stm32_adc_dma_buffer_done()
1496 adc->bufi = 0; in stm32_adc_dma_buffer_done()
1507 if (!adc->dma_chan) in stm32_adc_dma_start()
1510 dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__, in stm32_adc_dma_start()
1511 adc->rx_buf_sz, adc->rx_buf_sz / 2); in stm32_adc_dma_start()
1513 /* Prepare a DMA cyclic transaction */ in stm32_adc_dma_start()
1514 desc = dmaengine_prep_dma_cyclic(adc->dma_chan, in stm32_adc_dma_start()
1515 adc->rx_dma_buf, in stm32_adc_dma_start()
1516 adc->rx_buf_sz, adc->rx_buf_sz / 2, in stm32_adc_dma_start()
1520 return -EBUSY; in stm32_adc_dma_start()
1522 desc->callback = stm32_adc_dma_buffer_done; in stm32_adc_dma_start()
1523 desc->callback_param = indio_dev; in stm32_adc_dma_start()
1528 dmaengine_terminate_sync(adc->dma_chan); in stm32_adc_dma_start()
1532 /* Issue pending DMA requests */ in stm32_adc_dma_start()
1533 dma_async_issue_pending(adc->dma_chan); in stm32_adc_dma_start()
1541 struct device *dev = indio_dev->dev.parent; in stm32_adc_buffer_postenable()
1550 ret = stm32_adc_set_trig(indio_dev, indio_dev->trig); in stm32_adc_buffer_postenable()
1552 dev_err(&indio_dev->dev, "Can't set trigger\n"); in stm32_adc_buffer_postenable()
1558 dev_err(&indio_dev->dev, "Can't start dma\n"); in stm32_adc_buffer_postenable()
1563 adc->bufi = 0; in stm32_adc_buffer_postenable()
1567 if (!adc->dma_chan) in stm32_adc_buffer_postenable()
1570 adc->cfg->start_conv(indio_dev, !!adc->dma_chan); in stm32_adc_buffer_postenable()
1586 struct device *dev = indio_dev->dev.parent; in stm32_adc_buffer_predisable()
1588 adc->cfg->stop_conv(indio_dev); in stm32_adc_buffer_predisable()
1589 if (!adc->dma_chan) in stm32_adc_buffer_predisable()
1594 if (adc->dma_chan) in stm32_adc_buffer_predisable()
1595 dmaengine_terminate_sync(adc->dma_chan); in stm32_adc_buffer_predisable()
1598 dev_err(&indio_dev->dev, "Can't clear trigger\n"); in stm32_adc_buffer_predisable()
1614 struct iio_dev *indio_dev = pf->indio_dev; in stm32_adc_trigger_handler()
1617 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi); in stm32_adc_trigger_handler()
1619 if (!adc->dma_chan) { in stm32_adc_trigger_handler()
1621 adc->bufi = 0; in stm32_adc_trigger_handler()
1622 iio_push_to_buffers_with_timestamp(indio_dev, adc->buffer, in stm32_adc_trigger_handler()
1623 pf->timestamp); in stm32_adc_trigger_handler()
1627 while (residue >= indio_dev->scan_bytes) { in stm32_adc_trigger_handler()
1628 u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi]; in stm32_adc_trigger_handler()
1631 pf->timestamp); in stm32_adc_trigger_handler()
1632 residue -= indio_dev->scan_bytes; in stm32_adc_trigger_handler()
1633 adc->bufi += indio_dev->scan_bytes; in stm32_adc_trigger_handler()
1634 if (adc->bufi >= adc->rx_buf_sz) in stm32_adc_trigger_handler()
1635 adc->bufi = 0; in stm32_adc_trigger_handler()
1639 iio_trigger_notify_done(indio_dev->trig); in stm32_adc_trigger_handler()
1641 /* re-enable eoc irq */ in stm32_adc_trigger_handler()
1642 if (!adc->dma_chan) in stm32_adc_trigger_handler()
1661 struct device_node *node = indio_dev->dev.of_node; in stm32_adc_of_get_resolution()
1666 if (of_property_read_u32(node, "assigned-resolution-bits", &res)) in stm32_adc_of_get_resolution()
1667 res = adc->cfg->adc_info->resolutions[0]; in stm32_adc_of_get_resolution()
1669 for (i = 0; i < adc->cfg->adc_info->num_res; i++) in stm32_adc_of_get_resolution()
1670 if (res == adc->cfg->adc_info->resolutions[i]) in stm32_adc_of_get_resolution()
1672 if (i >= adc->cfg->adc_info->num_res) { in stm32_adc_of_get_resolution()
1673 dev_err(&indio_dev->dev, "Bad resolution: %u bits\n", res); in stm32_adc_of_get_resolution()
1674 return -EINVAL; in stm32_adc_of_get_resolution()
1677 dev_dbg(&indio_dev->dev, "Using %u bits resolution\n", res); in stm32_adc_of_get_resolution()
1678 adc->res = i; in stm32_adc_of_get_resolution()
1685 const struct stm32_adc_regs *smpr = &adc->cfg->regs->smp_bits[channel]; in stm32_adc_smpr_init()
1686 u32 period_ns, shift = smpr->shift, mask = smpr->mask; in stm32_adc_smpr_init()
1687 unsigned int smp, r = smpr->reg; in stm32_adc_smpr_init()
1690 period_ns = NSEC_PER_SEC / adc->common->rate; in stm32_adc_smpr_init()
1692 if ((period_ns * adc->cfg->smp_cycles[smp]) >= smp_ns) in stm32_adc_smpr_init()
1697 /* pre-build sampling time registers (e.g. smpr1, smpr2) */ in stm32_adc_smpr_init()
1698 adc->smpr_val[r] = (adc->smpr_val[r] & ~mask) | (smp << shift); in stm32_adc_smpr_init()
1706 char *name = adc->chan_name[vinp]; in stm32_adc_chan_init_one()
1708 chan->type = IIO_VOLTAGE; in stm32_adc_chan_init_one()
1709 chan->channel = vinp; in stm32_adc_chan_init_one()
1711 chan->differential = 1; in stm32_adc_chan_init_one()
1712 chan->channel2 = vinn; in stm32_adc_chan_init_one()
1713 snprintf(name, STM32_ADC_CH_SZ, "in%d-in%d", vinp, vinn); in stm32_adc_chan_init_one()
1717 chan->datasheet_name = name; in stm32_adc_chan_init_one()
1718 chan->scan_index = scan_index; in stm32_adc_chan_init_one()
1719 chan->indexed = 1; in stm32_adc_chan_init_one()
1720 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); in stm32_adc_chan_init_one()
1721 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | in stm32_adc_chan_init_one()
1723 chan->scan_type.sign = 'u'; in stm32_adc_chan_init_one()
1724 chan->scan_type.realbits = adc->cfg->adc_info->resolutions[adc->res]; in stm32_adc_chan_init_one()
1725 chan->scan_type.storagebits = 16; in stm32_adc_chan_init_one()
1726 chan->ext_info = stm32_adc_ext_info; in stm32_adc_chan_init_one()
1728 /* pre-build selected channels mask */ in stm32_adc_chan_init_one()
1729 adc->pcsel |= BIT(chan->channel); in stm32_adc_chan_init_one()
1731 /* pre-build diff channels mask */ in stm32_adc_chan_init_one()
1732 adc->difsel |= BIT(chan->channel); in stm32_adc_chan_init_one()
1733 /* Also add negative input to pre-selected channels */ in stm32_adc_chan_init_one()
1734 adc->pcsel |= BIT(chan->channel2); in stm32_adc_chan_init_one()
1740 struct device_node *node = indio_dev->dev.of_node; in stm32_adc_chan_of_init()
1742 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; in stm32_adc_chan_of_init()
1750 ret = of_property_count_u32_elems(node, "st,adc-channels"); in stm32_adc_chan_of_init()
1751 if (ret > adc_info->max_channels) { in stm32_adc_chan_of_init()
1752 dev_err(&indio_dev->dev, "Bad st,adc-channels?\n"); in stm32_adc_chan_of_init()
1753 return -EINVAL; in stm32_adc_chan_of_init()
1758 ret = of_property_count_elems_of_size(node, "st,adc-diff-channels", in stm32_adc_chan_of_init()
1760 if (ret > adc_info->max_channels) { in stm32_adc_chan_of_init()
1761 dev_err(&indio_dev->dev, "Bad st,adc-diff-channels?\n"); in stm32_adc_chan_of_init()
1762 return -EINVAL; in stm32_adc_chan_of_init()
1768 ret = of_property_read_u32_array(node, "st,adc-diff-channels", in stm32_adc_chan_of_init()
1775 dev_err(&indio_dev->dev, "No channels configured\n"); in stm32_adc_chan_of_init()
1776 return -ENODATA; in stm32_adc_chan_of_init()
1780 ret = of_property_count_u32_elems(node, "st,min-sample-time-nsecs"); in stm32_adc_chan_of_init()
1782 dev_err(&indio_dev->dev, "Invalid st,min-sample-time-nsecs\n"); in stm32_adc_chan_of_init()
1783 return -EINVAL; in stm32_adc_chan_of_init()
1786 channels = devm_kcalloc(&indio_dev->dev, num_channels, in stm32_adc_chan_of_init()
1789 return -ENOMEM; in stm32_adc_chan_of_init()
1791 of_property_for_each_u32(node, "st,adc-channels", prop, cur, val) { in stm32_adc_chan_of_init()
1792 if (val >= adc_info->max_channels) { in stm32_adc_chan_of_init()
1793 dev_err(&indio_dev->dev, "Invalid channel %d\n", val); in stm32_adc_chan_of_init()
1794 return -EINVAL; in stm32_adc_chan_of_init()
1797 /* Channel can't be configured both as single-ended & diff */ in stm32_adc_chan_of_init()
1800 dev_err(&indio_dev->dev, in stm32_adc_chan_of_init()
1801 "channel %d miss-configured\n", val); in stm32_adc_chan_of_init()
1802 return -EINVAL; in stm32_adc_chan_of_init()
1811 if (diff[i].vinp >= adc_info->max_channels || in stm32_adc_chan_of_init()
1812 diff[i].vinn >= adc_info->max_channels) { in stm32_adc_chan_of_init()
1813 dev_err(&indio_dev->dev, "Invalid channel in%d-in%d\n", in stm32_adc_chan_of_init()
1815 return -EINVAL; in stm32_adc_chan_of_init()
1830 of_property_read_u32_index(node, "st,min-sample-time-nsecs", in stm32_adc_chan_of_init()
1836 indio_dev->num_channels = scan_index; in stm32_adc_chan_of_init()
1837 indio_dev->channels = channels; in stm32_adc_chan_of_init()
1848 adc->dma_chan = dma_request_chan(dev, "rx"); in stm32_adc_dma_request()
1849 if (IS_ERR(adc->dma_chan)) { in stm32_adc_dma_request()
1850 ret = PTR_ERR(adc->dma_chan); in stm32_adc_dma_request()
1851 if (ret != -ENODEV) in stm32_adc_dma_request()
1853 "DMA channel request failed with\n"); in stm32_adc_dma_request()
1855 /* DMA is optional: fall back to IRQ mode */ in stm32_adc_dma_request()
1856 adc->dma_chan = NULL; in stm32_adc_dma_request()
1860 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev, in stm32_adc_dma_request()
1862 &adc->rx_dma_buf, GFP_KERNEL); in stm32_adc_dma_request()
1863 if (!adc->rx_buf) { in stm32_adc_dma_request()
1864 ret = -ENOMEM; in stm32_adc_dma_request()
1868 /* Configure DMA channel to read data register */ in stm32_adc_dma_request()
1870 config.src_addr = (dma_addr_t)adc->common->phys_base; in stm32_adc_dma_request()
1871 config.src_addr += adc->offset + adc->cfg->regs->dr; in stm32_adc_dma_request()
1874 ret = dmaengine_slave_config(adc->dma_chan, &config); in stm32_adc_dma_request()
1881 dma_free_coherent(adc->dma_chan->device->dev, STM32_DMA_BUFFER_SIZE, in stm32_adc_dma_request()
1882 adc->rx_buf, adc->rx_dma_buf); in stm32_adc_dma_request()
1884 dma_release_channel(adc->dma_chan); in stm32_adc_dma_request()
1892 struct device *dev = &pdev->dev; in stm32_adc_probe()
1897 if (!pdev->dev.of_node) in stm32_adc_probe()
1898 return -ENODEV; in stm32_adc_probe()
1900 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc)); in stm32_adc_probe()
1902 return -ENOMEM; in stm32_adc_probe()
1905 adc->common = dev_get_drvdata(pdev->dev.parent); in stm32_adc_probe()
1906 spin_lock_init(&adc->lock); in stm32_adc_probe()
1907 init_completion(&adc->completion); in stm32_adc_probe()
1908 adc->cfg = (const struct stm32_adc_cfg *) in stm32_adc_probe()
1909 of_match_device(dev->driver->of_match_table, dev)->data; in stm32_adc_probe()
1911 indio_dev->name = dev_name(&pdev->dev); in stm32_adc_probe()
1912 indio_dev->dev.of_node = pdev->dev.of_node; in stm32_adc_probe()
1913 indio_dev->info = &stm32_adc_iio_info; in stm32_adc_probe()
1914 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_HARDWARE_TRIGGERED; in stm32_adc_probe()
1918 ret = of_property_read_u32(pdev->dev.of_node, "reg", &adc->offset); in stm32_adc_probe()
1920 dev_err(&pdev->dev, "missing reg property\n"); in stm32_adc_probe()
1921 return -EINVAL; in stm32_adc_probe()
1924 adc->irq = platform_get_irq(pdev, 0); in stm32_adc_probe()
1925 if (adc->irq < 0) in stm32_adc_probe()
1926 return adc->irq; in stm32_adc_probe()
1928 ret = devm_request_threaded_irq(&pdev->dev, adc->irq, stm32_adc_isr, in stm32_adc_probe()
1930 0, pdev->name, indio_dev); in stm32_adc_probe()
1932 dev_err(&pdev->dev, "failed to request IRQ\n"); in stm32_adc_probe()
1936 adc->clk = devm_clk_get(&pdev->dev, NULL); in stm32_adc_probe()
1937 if (IS_ERR(adc->clk)) { in stm32_adc_probe()
1938 ret = PTR_ERR(adc->clk); in stm32_adc_probe()
1939 if (ret == -ENOENT && !adc->cfg->clk_required) { in stm32_adc_probe()
1940 adc->clk = NULL; in stm32_adc_probe()
1942 dev_err(&pdev->dev, "Can't get clock\n"); in stm32_adc_probe()
1959 if (!adc->dma_chan) in stm32_adc_probe()
1966 dev_err(&pdev->dev, "buffer setup failed\n"); in stm32_adc_probe()
1970 /* Get stm32-adc-core PM online */ in stm32_adc_probe()
1983 dev_err(&pdev->dev, "iio dev register failed\n"); in stm32_adc_probe()
2002 if (adc->dma_chan) { in stm32_adc_probe()
2003 dma_free_coherent(adc->dma_chan->device->dev, in stm32_adc_probe()
2005 adc->rx_buf, adc->rx_dma_buf); in stm32_adc_probe()
2006 dma_release_channel(adc->dma_chan); in stm32_adc_probe()
2017 pm_runtime_get_sync(&pdev->dev); in stm32_adc_remove()
2019 stm32_adc_hw_stop(&pdev->dev); in stm32_adc_remove()
2020 pm_runtime_disable(&pdev->dev); in stm32_adc_remove()
2021 pm_runtime_set_suspended(&pdev->dev); in stm32_adc_remove()
2022 pm_runtime_put_noidle(&pdev->dev); in stm32_adc_remove()
2024 if (adc->dma_chan) { in stm32_adc_remove()
2025 dma_free_coherent(adc->dma_chan->device->dev, in stm32_adc_remove()
2027 adc->rx_buf, adc->rx_dma_buf); in stm32_adc_remove()
2028 dma_release_channel(adc->dma_chan); in stm32_adc_remove()
2058 indio_dev->active_scan_mask); in stm32_adc_resume()
2121 { .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_cfg },
2122 { .compatible = "st,stm32h7-adc", .data = (void *)&stm32h7_adc_cfg },
2123 { .compatible = "st,stm32mp1-adc", .data = (void *)&stm32mp1_adc_cfg },
2132 .name = "stm32-adc",
2140 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC IIO driver");
2142 MODULE_ALIAS("platform:stm32-adc");