17  *         revision A2.0 and up support UDMA mode 5 (100 MB/s)
43 #define SVWKS_CSB5_REVISION_NEW	0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
44 #define SVWKS_CSB6_REVISION	0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
63 	return 0;  in check_in_drive_lists()
71 		return 0x1f;  in svwks_udma_filter()
73 		return 0x07;  in svwks_udma_filter()
75 		u8 btr = 0, mode, mask;  in svwks_udma_filter()
77 		pci_read_config_byte(dev, 0x5A, &btr);  in svwks_udma_filter()
78 		mode = btr & 0x3;  in svwks_udma_filter()
86 		case 3:	 mask = 0x3f; break;  in svwks_udma_filter()
87 		case 2:	 mask = 0x1f; break;  in svwks_udma_filter()
88 		case 1:	 mask = 0x07; break;  in svwks_udma_filter()
89 		default: mask = 0x00; break;  in svwks_udma_filter()
107 	return 0;  in svwks_csb_check()
112 	static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };  in svwks_set_pio_mode()
113 	static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };  in svwks_set_pio_mode()
124 		u16 csb_pio = 0;  in svwks_set_pio_mode()
126 		pci_read_config_word(dev, 0x4a, &csb_pio);  in svwks_set_pio_mode()
128 		csb_pio &= ~(0x0f << (4 * drive->dn));  in svwks_set_pio_mode()
131 		pci_write_config_word(dev, 0x4a, csb_pio);  in svwks_set_pio_mode()
137 	static const u8 udma_modes[]		= { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };  in svwks_set_dma_mode()
138 	static const u8 dma_modes[]		= { 0x77, 0x21, 0x20 };  in svwks_set_dma_mode()
139 	static const u8 drive_pci2[]		= { 0x45, 0x44, 0x47, 0x46 };  in svwks_set_dma_mode()
145 	u8 ultra_enable	 = 0, ultra_timing = 0, dma_timing = 0;  in svwks_set_dma_mode()
150 	pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);  in svwks_set_dma_mode()
151 	pci_read_config_byte(dev, 0x54, &ultra_enable);  in svwks_set_dma_mode()
153 	ultra_timing	&= ~(0x0F << (4*unit));  in svwks_set_dma_mode()
154 	ultra_enable	&= ~(0x01 << drive->dn);  in svwks_set_dma_mode()
159 		ultra_enable |= (0x01 << drive->dn);  in svwks_set_dma_mode()
164 	pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);  in svwks_set_dma_mode()
165 	pci_write_config_byte(dev, 0x54, ultra_enable);  in svwks_set_dma_mode()
174 	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);  in init_chipset_svwks()
182 			pci_read_config_dword(isa_dev, 0x64, &reg);  in init_chipset_svwks()
183 			reg &= ~0x00002000; /* disable 600ns interrupt mask */  in init_chipset_svwks()
184 			if(!(reg & 0x00004000))  in init_chipset_svwks()
187 			reg |=  0x00004000; /* enable UDMA/33 support */  in init_chipset_svwks()
188 			pci_write_config_dword(isa_dev, 0x64, reg);  in init_chipset_svwks()
201 			u32 reg4c = 0;  in init_chipset_svwks()
205 				pci_read_config_dword(findev, 0x4C, &reg4c);  in init_chipset_svwks()
206 				reg4c &= ~0x000007FF;  in init_chipset_svwks()
207 				reg4c |=  0x00000040;  in init_chipset_svwks()
208 				reg4c |=  0x00000020;  in init_chipset_svwks()
209 				pci_write_config_dword(findev, 0x4C, reg4c);  in init_chipset_svwks()
212 			outb_p(0x06, 0x0c00);  in init_chipset_svwks()
213 			dev->irq = inb_p(0x0c01);  in init_chipset_svwks()
216 			u8 reg41 = 0;  in init_chipset_svwks()
221 				pci_read_config_byte(findev, 0x41, &reg41);  in init_chipset_svwks()
222 				reg41 &= ~0x40;  in init_chipset_svwks()
223 				pci_write_config_byte(findev, 0x41, reg41);  in init_chipset_svwks()
234 				dev->irq = 0;  in init_chipset_svwks()
236 //		pci_read_config_dword(dev, 0x40, &pioreg)  in init_chipset_svwks()
237 //		pci_write_config_dword(dev, 0x40, 0x99999999);  in init_chipset_svwks()
238 //		pci_read_config_dword(dev, 0x44, &dmareg);  in init_chipset_svwks()
239 //		pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);  in init_chipset_svwks()
243 		 * 2. enable DMA modes with bits 0-1  in init_chipset_svwks()
249 		pci_read_config_byte(dev, 0x5A, &btr);  in init_chipset_svwks()
250 		btr &= ~0x40;  in init_chipset_svwks()
252 			btr |= 0x2;  in init_chipset_svwks()
254 			btr |= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;  in init_chipset_svwks()
255 		pci_write_config_byte(dev, 0x5A, btr);  in init_chipset_svwks()
259 		pci_read_config_byte(dev, 0x5A, &btr);  in init_chipset_svwks()
260 		btr &= ~0x40;  in init_chipset_svwks()
261 		btr |= 0x3;  in init_chipset_svwks()
262 		pci_write_config_byte(dev, 0x5A, btr);  in init_chipset_svwks()
265 	return 0;  in init_chipset_svwks()
348 	{	/* 0: OSB4 */
354 		.udma_mask	= 0x00, /* UDMA is problematic on OSB4 */
411 		if ((PCI_FUNC(dev->devfn) & 1) == 0) {  in svwks_init_one()
412 			if (pci_resource_start(dev, 0) != 0x01f1)  in svwks_init_one()
423 	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE),   0 },
428 	{ 0, },