50 	 * it cannot be configured for PIO mode 0.  This table sets these  in it8172_set_pio_mode()
53 	static const u8 timings[] = { 0x3f, 0x3c, 0x1b, 0x12, 0x0a };  in it8172_set_pio_mode()
55 	pci_read_config_word(dev, 0x40, &drive_enables);  in it8172_set_pio_mode()
56 	pci_read_config_dword(dev, 0x44, &drive_timing);  in it8172_set_pio_mode()
59 	 * Enable port 0x44. The IT8172 spec is confused; it calls  in it8172_set_pio_mode()
63 	drive_enables |= 0x4000;  in it8172_set_pio_mode()
65 	drive_enables &= drive->dn ? 0xc006 : 0xc060;  in it8172_set_pio_mode()
68 		drive_enables |= 0x0004 << (drive->dn * 4);  in it8172_set_pio_mode()
71 		drive_enables |= 0x0002 << (drive->dn * 4);  in it8172_set_pio_mode()
73 	drive_timing &= drive->dn ? 0x00003f00 : 0x000fc000;  in it8172_set_pio_mode()
76 	pci_write_config_word(dev, 0x40, drive_enables);  in it8172_set_pio_mode()
77 	pci_write_config_dword(dev, 0x44, drive_timing);  in it8172_set_pio_mode()
85 	int u_speed		= 0;  in it8172_set_dma_mode()
89 	pci_read_config_byte(dev, 0x48, &reg48);  in it8172_set_dma_mode()
90 	pci_read_config_byte(dev, 0x4a, &reg4a);  in it8172_set_dma_mode()
96 		pci_write_config_byte(dev, 0x48, reg48 | u_flag);  in it8172_set_dma_mode()
98 		pci_write_config_byte(dev, 0x4a, reg4a | u_speed);  in it8172_set_dma_mode()
100 		const u8 mwdma_to_pio[] = { 0, 3, 4 };  in it8172_set_dma_mode()
102 		pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);  in it8172_set_dma_mode()
103 		pci_write_config_byte(dev, 0x4a, reg4a & ~a_speed);  in it8172_set_dma_mode()
121 	.enablebits	= { {0x41, 0x80, 0x80}, {0x00, 0x00, 0x00} },
136 	{ PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8172), 0 },
137 	{ 0, },