71  *   the wrong PCI frequency since DPLL has already been calibrated by BIOS;
99  * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
102  *   with only the chip type and its specific base DPLL frequency, the highest
107  *   switch  to calculating  PCI clock frequency based on the chip's base DPLL
109  * - switch to using the  DPLL clock and enable UltraATA/133 mode by default on
112  * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
400 	u8 dpll_clk;		/* DPLL clock in MHz */
451 	.dpll_clk	= 0,	/* no DPLL */
793  *	Switch the DPLL clock on the HPT3xxN devices. This is a	right mess.
842  *	hpt37x_calibrate_dpll	-	calibrate the DPLL
845  *	Perform a calibration cycle on the DPLL.
850 	u32 dpll = (f_high << 16) | f_low | 0x100;  in hpt37x_calibrate_dpll()  local
854 	pci_write_config_dword(dev, 0x5c, dpll);  in hpt37x_calibrate_dpll()
866 		/* DPLL destabilized? */  in hpt37x_calibrate_dpll()
870 	/* Turn off tuning, we have the DPLL set */  in hpt37x_calibrate_dpll()
871 	pci_read_config_dword (dev, 0x5c, &dpll);  in hpt37x_calibrate_dpll()
872 	pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));  in hpt37x_calibrate_dpll()
911 	u8 pci_clk,  dpll_clk	= 0;	/* PCI and DPLL clock in MHz */  in init_chipset_hpt366()
955 		 * saves f_CNT value before  reprogramming the DPLL from its  in init_chipset_hpt366()
977 		 * that nobody has touched the DPLL yet...  in init_chipset_hpt366()
1008 		printk(KERN_INFO "%s %s: DPLL base: %d MHz, f_CNT: %d, "  in init_chipset_hpt366()
1052 	 * Only try the DPLL if we don't have a table for the PCI clock that  in init_chipset_hpt366()
1055 	 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.  in init_chipset_hpt366()
1056 	 * We also  don't like using  the DPLL because this causes glitches  in init_chipset_hpt366()
1064 		  * Select 66 MHz DPLL clock only if UltraATA/133 mode is  in init_chipset_hpt366()
1065 		  * supported/enabled, use 50 MHz DPLL clock otherwise...  in init_chipset_hpt366()
1070 		} else if (dpll_clk) {	/* HPT36x chips don't have DPLL */  in init_chipset_hpt366()
1081 		/* Select the DPLL clock. */  in init_chipset_hpt366()
1085 		 * Adjust the DPLL based upon PCI clock, enable it,  in init_chipset_hpt366()
1103 			printk(KERN_ERR "%s %s: DPLL did not stabilize!\n",  in init_chipset_hpt366()
1108 		printk(KERN_INFO "%s %s: using %d MHz DPLL clock\n",  in init_chipset_hpt366()
1111 		/* Mark the fact that we're not using the DPLL. */  in init_chipset_hpt366()