27  * Here are the standard PIO mode 0-4 timings for each "format".
28  * Format-0 uses fast data reg timings, with slower command reg timings.
29  * Format-1 uses fast timings for all registers, but won't work with all drives.
37  * After chip reset, the PIO timings are set to 0x0000e132, which is not valid.
39 #define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)  argument
50  *	will have valid default PIO timings set up before we get here.
71  *	different timings can still be chosen for each drive.  We could
106 	unsigned int reg, timings = 0;  in cs5530_set_dma_mode()  local
109 		case XFER_UDMA_0:	timings = 0x00921250; break;  in cs5530_set_dma_mode()
110 		case XFER_UDMA_1:	timings = 0x00911140; break;  in cs5530_set_dma_mode()
111 		case XFER_UDMA_2:	timings = 0x00911030; break;  in cs5530_set_dma_mode()
112 		case XFER_MW_DMA_0:	timings = 0x00077771; break;  in cs5530_set_dma_mode()
113 		case XFER_MW_DMA_1:	timings = 0x00012121; break;  in cs5530_set_dma_mode()
114 		case XFER_MW_DMA_2:	timings = 0x00002020; break;  in cs5530_set_dma_mode()
118 	timings |= reg & 0x80000000;		/* preserve PIO format bit */  in cs5530_set_dma_mode()
120 		outl(timings, basereg + 4);	/* write drive0 config register */  in cs5530_set_dma_mode()
122 		if (timings & 0x00100000)  in cs5530_set_dma_mode()
123 			reg |=  0x00100000;	/* enable UDMA timings for both drives */  in cs5530_set_dma_mode()
125 			reg &= ~0x00100000;	/* disable UDMA timings for both drives */  in cs5530_set_dma_mode()
127 		outl(timings, basereg + 12);	/* write drive1 config register */  in cs5530_set_dma_mode()