28 #define CFR		0x50
29 #define   CFR_INTR_CH0		0x04
31 #define	CMDTIM		0x52
32 #define	ARTTIM0		0x53
33 #define	DRWTIM0		0x54
34 #define ARTTIM1 	0x55
35 #define DRWTIM1		0x56
36 #define ARTTIM23	0x57
37 #define   ARTTIM23_DIS_RA2	0x04
38 #define   ARTTIM23_DIS_RA3	0x08
39 #define   ARTTIM23_INTR_CH1	0x10
40 #define DRWTIM2		0x58
41 #define BRST		0x59
42 #define DRWTIM3		0x5b
44 #define BMIDECR0	0x70
45 #define MRDMODE		0x71
46 #define   MRDMODE_INTR_CH0	0x04
47 #define   MRDMODE_INTR_CH1	0x08
48 #define UDIDETCR0	0x73
49 #define DTPR0		0x74
50 #define BMIDECR1	0x78
51 #define BMIDECSR	0x79
52 #define UDIDETCR1	0x7B
53 #define DTPR1		0x7C
62 		{15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};  in cmd64x_program_timings()
63 	static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};  in cmd64x_program_timings()
67 	u8 arttim = 0;  in cmd64x_program_timings()
72 	ide_timing_compute(drive, mode, &t, T, 0);  in cmd64x_program_timings()
89 	t.active &= 0x0f;  in cmd64x_program_timings()
107 			ide_timing_compute(pair, pair->pio_mode, &tp, T, 0);  in cmd64x_program_timings()
111 						&tp, T, 0);  in cmd64x_program_timings()
127 	arttim &= ~0xc0;  in cmd64x_program_timings()
154 	u8 unit			= drive->dn & 0x01;  in cmd64x_set_dma_mode()
155 	u8 regU = 0, pciU	= hwif->channel ? UDIDETCR1 : UDIDETCR0;  in cmd64x_set_dma_mode()
159 	regU &= ~(unit ? 0xCA : 0x35);  in cmd64x_set_dma_mode()
163 		regU |= unit ? 0x0A : 0x05;  in cmd64x_set_dma_mode()
166 		regU |= unit ? 0x4A : 0x15;  in cmd64x_set_dma_mode()
169 		regU |= unit ? 0x8A : 0x25;  in cmd64x_set_dma_mode()
172 		regU |= unit ? 0x42 : 0x11;  in cmd64x_set_dma_mode()
175 		regU |= unit ? 0x82 : 0x21;  in cmd64x_set_dma_mode()
178 		regU |= unit ? 0xC2 : 0x31;  in cmd64x_set_dma_mode()
211 	u8  irq_stat		= 0;  in cmd64x_clear_irq()
226 	pr_debug("%s: mrdmode: 0x%02x irq_mask: 0x%02x\n",  in cmd648_test_irq()
229 	return (mrdmode & irq_mask) ? 1 : 0;  in cmd648_test_irq()
238 	u8  irq_stat		= 0;  in cmd64x_test_irq()
242 	pr_debug("%s: irq_stat: 0x%02x irq_mask: 0x%02x\n",  in cmd64x_test_irq()
245 	return (irq_stat & irq_mask) ? 1 : 0;  in cmd64x_test_irq()
249  * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
256 	u8 dma_stat = 0, dma_cmd = 0;  in cmd646_1_dma_end()
272 	u8 mrdmode = 0;  in init_chipset_cmd64x()
282 	 * bits 0-1 are write only and won't be read back as  in init_chipset_cmd64x()
286 	mrdmode &= ~0x30;  in init_chipset_cmd64x()
287 	(void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02));  in init_chipset_cmd64x()
289 	return 0;  in init_chipset_cmd64x()
295 	u8 bmidecsr = 0, mask	= hwif->channel ? 0x02 : 0x01;  in cmd64x_cable_detect()
335 	{	/* 0: CMD643 */
338 		.enablebits	= {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
345 		.udma_mask	= 0x00, /* no udma */
350 		.enablebits	= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
361 		.enablebits	= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
371 		.enablebits	= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
390 		 * correspond to revisions 0x03, 0x05 and 0x07 respectively.  in cmd64x_init_one()
392 		 * tell me the details, the 0x03 revision cannot support  in cmd64x_init_one()
398 		 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.  in cmd64x_init_one()
401 			d.udma_mask = 0x00;  in cmd64x_init_one()
408 				d.enablebits[0].reg = 0;  in cmd64x_init_one()
420 	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
424 	{ 0, },