Lines Matching defs:etmv4_config
255 struct etmv4_config { struct
256 u32 mode;
257 u32 pe_sel;
258 u32 cfg;
259 u32 eventctrl0;
260 u32 eventctrl1;
261 u32 stall_ctrl;
262 u32 ts_ctrl;
263 u32 syncfreq;
264 u32 ccctlr;
265 u32 bb_ctrl;
266 u32 vinst_ctrl;
267 u32 viiectlr;
268 u32 vissctlr;
269 u32 vipcssctlr;
270 u8 seq_idx;
271 u32 seq_ctrl[ETM_MAX_SEQ_STATES];
272 u32 seq_rst;
273 u32 seq_state;
274 u8 cntr_idx;
275 u32 cntrldvr[ETMv4_MAX_CNTR];
276 u32 cntr_ctrl[ETMv4_MAX_CNTR];
277 u32 cntr_val[ETMv4_MAX_CNTR];
278 u8 res_idx;
279 u32 res_ctrl[ETM_MAX_RES_SEL];
280 u8 ss_idx;
281 u32 ss_ctrl[ETM_MAX_SS_CMP];
282 u32 ss_status[ETM_MAX_SS_CMP];
283 u32 ss_pe_cmp[ETM_MAX_SS_CMP];
284 u8 addr_idx;
285 u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP];
286 u64 addr_acc[ETM_MAX_SINGLE_ADDR_CMP];
287 u8 addr_type[ETM_MAX_SINGLE_ADDR_CMP];
288 u8 ctxid_idx;
289 u64 ctxid_pid[ETMv4_MAX_CTXID_CMP];
290 u32 ctxid_mask0;
291 u32 ctxid_mask1;
292 u8 vmid_idx;
293 u64 vmid_val[ETM_MAX_VMID_CMP];
294 u32 vmid_mask0;
295 u32 vmid_mask1;
296 u32 ext_inp;
297 u8 arch;