Lines Matching +full:preemphasis +full:- +full:width
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
242 * struct zynqmp_dp_link_config - Common link config between source and sink
252 * struct zynqmp_dp_mode - Configured mode of DisplayPort
266 * struct zynqmp_dp_config - Configuration of DisplayPort from DTS
278 * struct zynqmp_dp - Xilinx DisplayPort core
335 writel(val, dp->iomem + offset); in zynqmp_dp_write()
340 return readl(dp->iomem + offset); in zynqmp_dp_read()
353 /* -----------------------------------------------------------------------------
364 reset_control_assert(dp->reset); in zynqmp_dp_reset()
366 reset_control_deassert(dp->reset); in zynqmp_dp_reset()
371 bool status = !!reset_control_status(dp->reset); in zynqmp_dp_reset()
379 dev_err(dp->dev, "reset %s timeout\n", assert ? "assert" : "deassert"); in zynqmp_dp_reset()
380 return -ETIMEDOUT; in zynqmp_dp_reset()
384 * zynqmp_dp_phy_init - Initialize the phy
397 for (i = 0; i < dp->num_lanes; i++) { in zynqmp_dp_phy_init()
398 ret = phy_init(dp->phy[i]); in zynqmp_dp_phy_init()
400 dev_err(dp->dev, "failed to init phy lane %d\n", i); in zynqmp_dp_phy_init()
415 for (i = dp->num_lanes - 1; i >= 0; i--) { in zynqmp_dp_phy_init()
416 ret = phy_power_on(dp->phy[i]); in zynqmp_dp_phy_init()
418 dev_err(dp->dev, "failed to power on phy lane %d\n", i); in zynqmp_dp_phy_init()
427 * zynqmp_dp_phy_exit - Exit the phy
437 for (i = 0; i < dp->num_lanes; i++) { in zynqmp_dp_phy_exit()
438 ret = phy_power_off(dp->phy[i]); in zynqmp_dp_phy_exit()
440 dev_err(dp->dev, "failed to power off phy(%d) %d\n", i, in zynqmp_dp_phy_exit()
446 for (i = 0; i < dp->num_lanes; i++) { in zynqmp_dp_phy_exit()
447 ret = phy_exit(dp->phy[i]); in zynqmp_dp_phy_exit()
449 dev_err(dp->dev, "failed to exit phy(%d) %d\n", i, ret); in zynqmp_dp_phy_exit()
454 * zynqmp_dp_phy_probe - Probe the PHYs
459 * found. The caller can check dp->num_lanes to check how many PHYs were found.
462 * * 0 - Success
463 * * -ENXIO - No PHY found
464 * * -EPROBE_DEFER - Probe deferral requested
465 * * Other negative value - PHY retrieval failure
475 snprintf(phy_name, sizeof(phy_name), "dp-phy%d", i); in zynqmp_dp_phy_probe()
476 phy = devm_phy_get(dp->dev, phy_name); in zynqmp_dp_phy_probe()
480 case -ENODEV: in zynqmp_dp_phy_probe()
481 if (dp->num_lanes) in zynqmp_dp_phy_probe()
484 dev_err(dp->dev, "no PHY found\n"); in zynqmp_dp_phy_probe()
485 return -ENXIO; in zynqmp_dp_phy_probe()
487 case -EPROBE_DEFER: in zynqmp_dp_phy_probe()
488 return -EPROBE_DEFER; in zynqmp_dp_phy_probe()
491 dev_err(dp->dev, "failed to get PHY lane %u\n", in zynqmp_dp_phy_probe()
497 dp->phy[i] = phy; in zynqmp_dp_phy_probe()
498 dp->num_lanes++; in zynqmp_dp_phy_probe()
505 * zynqmp_dp_phy_ready - Check if PHY is ready
511 * Return: 0 if PHY is ready, or -ENODEV if PHY is not ready.
517 ready = (1 << dp->num_lanes) - 1; in zynqmp_dp_phy_ready()
526 dev_err(dp->dev, "PHY isn't ready\n"); in zynqmp_dp_phy_ready()
527 return -ENODEV; in zynqmp_dp_phy_ready()
536 /* -----------------------------------------------------------------------------
541 * zynqmp_dp_max_rate - Calculate and return available max pixel clock
542 * @link_rate: link rate (Kilo-bytes / sec)
554 * zynqmp_dp_mode_configure - Configure the link values
564 * Return: Current link rate code, or -EINVAL.
569 int max_rate = dp->link_config.max_rate; in zynqmp_dp_mode_configure()
571 u8 max_lanes = dp->link_config.max_lanes; in zynqmp_dp_mode_configure()
573 u8 bpp = dp->config.bpp; in zynqmp_dp_mode_configure()
585 dev_err(dp->dev, "can't downshift. already lowest link rate\n"); in zynqmp_dp_mode_configure()
586 return -EINVAL; in zynqmp_dp_mode_configure()
600 dp->mode.bw_code = bw_code; in zynqmp_dp_mode_configure()
601 dp->mode.lane_cnt = lane_cnt; in zynqmp_dp_mode_configure()
602 dp->mode.pclock = pclock; in zynqmp_dp_mode_configure()
603 return dp->mode.bw_code; in zynqmp_dp_mode_configure()
607 dev_err(dp->dev, "failed to configure link values\n"); in zynqmp_dp_mode_configure()
609 return -EINVAL; in zynqmp_dp_mode_configure()
613 * zynqmp_dp_adjust_train - Adjust train values
620 u8 *train_set = dp->train_set; in zynqmp_dp_adjust_train()
621 u8 voltage = 0, preemphasis = 0; in zynqmp_dp_adjust_train() local
624 for (i = 0; i < dp->mode.lane_cnt; i++) { in zynqmp_dp_adjust_train()
631 if (p > preemphasis) in zynqmp_dp_adjust_train()
632 preemphasis = p; in zynqmp_dp_adjust_train()
638 if (preemphasis >= DP_TRAIN_PRE_EMPH_LEVEL_2) in zynqmp_dp_adjust_train()
639 preemphasis |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; in zynqmp_dp_adjust_train()
641 for (i = 0; i < dp->mode.lane_cnt; i++) in zynqmp_dp_adjust_train()
642 train_set[i] = voltage | preemphasis; in zynqmp_dp_adjust_train()
646 * zynqmp_dp_update_vs_emph - Update the training values
660 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, dp->train_set, in zynqmp_dp_update_vs_emph()
661 dp->mode.lane_cnt); in zynqmp_dp_update_vs_emph()
665 for (i = 0; i < dp->mode.lane_cnt; i++) { in zynqmp_dp_update_vs_emph()
668 u8 train = dp->train_set[i]; in zynqmp_dp_update_vs_emph()
675 phy_configure(dp->phy[i], &opts); in zynqmp_dp_update_vs_emph()
684 * zynqmp_dp_link_train_cr - Train clock recovery
693 u8 lane_cnt = dp->mode.lane_cnt; in zynqmp_dp_link_train_cr()
701 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, in zynqmp_dp_link_train_cr()
716 drm_dp_link_train_clock_recovery_delay(dp->dpcd); in zynqmp_dp_link_train_cr()
717 ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status); in zynqmp_dp_link_train_cr()
726 if (!(dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED)) in zynqmp_dp_link_train_cr()
731 if ((dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == vs) in zynqmp_dp_link_train_cr()
739 vs = dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in zynqmp_dp_link_train_cr()
744 return -EIO; in zynqmp_dp_link_train_cr()
750 * zynqmp_dp_link_train_ce - Train channel equalization
759 u8 lane_cnt = dp->mode.lane_cnt; in zynqmp_dp_link_train_ce()
764 if (dp->dpcd[DP_DPCD_REV] >= DP_V1_2 && in zynqmp_dp_link_train_ce()
765 dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) in zynqmp_dp_link_train_ce()
771 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, in zynqmp_dp_link_train_ce()
781 drm_dp_link_train_channel_eq_delay(dp->dpcd); in zynqmp_dp_link_train_ce()
782 ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status); in zynqmp_dp_link_train_ce()
794 return -EIO; in zynqmp_dp_link_train_ce()
800 * zynqmp_dp_link_train - Train the link
808 u8 bw_code = dp->mode.bw_code; in zynqmp_dp_train()
809 u8 lane_cnt = dp->mode.lane_cnt; in zynqmp_dp_train()
815 enhanced = drm_dp_enhanced_frame_cap(dp->dpcd); in zynqmp_dp_train()
821 if (dp->dpcd[3] & 0x1) { in zynqmp_dp_train()
823 drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL, in zynqmp_dp_train()
827 drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL, 0); in zynqmp_dp_train()
830 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, aux_lane_cnt); in zynqmp_dp_train()
832 dev_err(dp->dev, "failed to set lane count\n"); in zynqmp_dp_train()
836 ret = drm_dp_dpcd_writeb(&dp->aux, DP_MAIN_LINK_CHANNEL_CODING_SET, in zynqmp_dp_train()
839 dev_err(dp->dev, "failed to set ANSI 8B/10B encoding\n"); in zynqmp_dp_train()
843 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LINK_BW_SET, bw_code); in zynqmp_dp_train()
845 dev_err(dp->dev, "failed to set DP bandwidth\n"); in zynqmp_dp_train()
869 memset(dp->train_set, 0, 4); in zynqmp_dp_train()
878 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, in zynqmp_dp_train()
881 dev_err(dp->dev, "failed to disable training pattern\n"); in zynqmp_dp_train()
893 * zynqmp_dp_train_loop - Downshift the link rate during training
900 struct zynqmp_dp_mode *mode = &dp->mode; in zynqmp_dp_train_loop()
901 u8 bw = mode->bw_code; in zynqmp_dp_train_loop()
905 if (dp->status == connector_status_disconnected || in zynqmp_dp_train_loop()
906 !dp->enabled) in zynqmp_dp_train_loop()
913 ret = zynqmp_dp_mode_configure(dp, mode->pclock, bw); in zynqmp_dp_train_loop()
921 dev_err(dp->dev, "failed to train the DP link\n"); in zynqmp_dp_train_loop()
924 /* -----------------------------------------------------------------------------
931 * zynqmp_dp_aux_cmd_submit - Submit aux command
948 * -EBUSY when there is any request already being processed
949 * -ETIMEDOUT when receiving reply is timed out
950 * -EIO when received bytes are less than requested
960 return -EBUSY; in zynqmp_dp_aux_cmd_submit()
972 reg |= (bytes - 1) << ZYNQMP_DP_AUX_COMMAND_BYTES_SHIFT; in zynqmp_dp_aux_cmd_submit()
983 return -ETIMEDOUT; in zynqmp_dp_aux_cmd_submit()
997 return -EIO; in zynqmp_dp_aux_cmd_submit()
1018 ret = zynqmp_dp_aux_cmd_submit(dp, msg->request, msg->address, in zynqmp_dp_aux_transfer()
1019 msg->buffer, msg->size, in zynqmp_dp_aux_transfer()
1020 &msg->reply); in zynqmp_dp_aux_transfer()
1022 dev_dbg(dp->dev, "aux %d retries\n", i); in zynqmp_dp_aux_transfer()
1023 return msg->size; in zynqmp_dp_aux_transfer()
1026 if (dp->status == connector_status_disconnected) { in zynqmp_dp_aux_transfer()
1027 dev_dbg(dp->dev, "no connected aux device\n"); in zynqmp_dp_aux_transfer()
1028 return -ENODEV; in zynqmp_dp_aux_transfer()
1034 dev_dbg(dp->dev, "failed to do aux transfer (%d)\n", ret); in zynqmp_dp_aux_transfer()
1040 * zynqmp_dp_aux_init - Initialize and register the DP AUX
1055 * 40 and 48. The AUX pulse width must be between 0.4µs and 0.6µs, in zynqmp_dp_aux_init()
1059 rate = clk_get_rate(dp->dpsub->apb_clk); in zynqmp_dp_aux_init()
1062 dev_err(dp->dev, "aclk frequency too high\n"); in zynqmp_dp_aux_init()
1063 return -EINVAL; in zynqmp_dp_aux_init()
1070 dp->aux.name = "ZynqMP DP AUX"; in zynqmp_dp_aux_init()
1071 dp->aux.dev = dp->dev; in zynqmp_dp_aux_init()
1072 dp->aux.transfer = zynqmp_dp_aux_transfer; in zynqmp_dp_aux_init()
1074 return drm_dp_aux_register(&dp->aux); in zynqmp_dp_aux_init()
1078 * zynqmp_dp_aux_cleanup - Cleanup the DP AUX
1085 drm_dp_aux_unregister(&dp->aux); in zynqmp_dp_aux_cleanup()
1088 /* -----------------------------------------------------------------------------
1093 * zynqmp_dp_update_misc - Write the misc registers
1101 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_MISC0, dp->config.misc0); in zynqmp_dp_update_misc()
1102 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_MISC1, dp->config.misc1); in zynqmp_dp_update_misc()
1106 * zynqmp_dp_set_format - Set the input format
1113 * Return: 0 on success, or -EINVAL.
1120 struct zynqmp_dp_config *config = &dp->config; in zynqmp_dp_set_format()
1123 config->misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_MASK; in zynqmp_dp_set_format()
1124 config->misc1 &= ~ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN; in zynqmp_dp_set_format()
1128 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_RGB; in zynqmp_dp_set_format()
1133 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_444; in zynqmp_dp_set_format()
1138 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_422; in zynqmp_dp_set_format()
1143 config->misc1 |= ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN; in zynqmp_dp_set_format()
1148 dev_err(dp->dev, "Invalid colormetry in DT\n"); in zynqmp_dp_set_format()
1149 return -EINVAL; in zynqmp_dp_set_format()
1152 display = &dp->connector.display_info; in zynqmp_dp_set_format()
1153 if (display->bpc && bpc > display->bpc) { in zynqmp_dp_set_format()
1154 dev_warn(dp->dev, in zynqmp_dp_set_format()
1156 bpc, display->bpc); in zynqmp_dp_set_format()
1157 bpc = display->bpc; in zynqmp_dp_set_format()
1160 config->misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_MASK; in zynqmp_dp_set_format()
1164 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_6; in zynqmp_dp_set_format()
1167 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8; in zynqmp_dp_set_format()
1170 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_10; in zynqmp_dp_set_format()
1173 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_12; in zynqmp_dp_set_format()
1176 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_16; in zynqmp_dp_set_format()
1179 dev_warn(dp->dev, "Not supported bpc (%u). fall back to 8bpc\n", in zynqmp_dp_set_format()
1181 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8; in zynqmp_dp_set_format()
1187 config->bpp = bpc * num_colors; in zynqmp_dp_set_format()
1193 * zynqmp_dp_encoder_mode_set_transfer_unit - Set the transfer unit values
1210 vid_kbytes = mode->clock * (dp->config.bpp / 8); in zynqmp_dp_encoder_mode_set_transfer_unit()
1211 bw = drm_dp_bw_code_to_link_rate(dp->mode.bw_code); in zynqmp_dp_encoder_mode_set_transfer_unit()
1212 avg_bytes_per_tu = vid_kbytes * tu / (dp->mode.lane_cnt * bw / 1000); in zynqmp_dp_encoder_mode_set_transfer_unit()
1224 init_wait = tu - avg_bytes_per_tu / 1000; in zynqmp_dp_encoder_mode_set_transfer_unit()
1230 * zynqmp_dp_encoder_mode_set_stream - Configure the main stream
1240 u8 lane_cnt = dp->mode.lane_cnt; in zynqmp_dp_encoder_mode_set_stream()
1244 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HTOTAL, mode->htotal); in zynqmp_dp_encoder_mode_set_stream()
1245 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VTOTAL, mode->vtotal); in zynqmp_dp_encoder_mode_set_stream()
1247 (!!(mode->flags & DRM_MODE_FLAG_PVSYNC) << in zynqmp_dp_encoder_mode_set_stream()
1249 (!!(mode->flags & DRM_MODE_FLAG_PHSYNC) << in zynqmp_dp_encoder_mode_set_stream()
1252 mode->hsync_end - mode->hsync_start); in zynqmp_dp_encoder_mode_set_stream()
1254 mode->vsync_end - mode->vsync_start); in zynqmp_dp_encoder_mode_set_stream()
1255 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HRES, mode->hdisplay); in zynqmp_dp_encoder_mode_set_stream()
1256 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VRES, mode->vdisplay); in zynqmp_dp_encoder_mode_set_stream()
1258 mode->htotal - mode->hsync_start); in zynqmp_dp_encoder_mode_set_stream()
1260 mode->vtotal - mode->vsync_start); in zynqmp_dp_encoder_mode_set_stream()
1263 if (dp->config.misc0 & ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK) { in zynqmp_dp_encoder_mode_set_stream()
1264 reg = drm_dp_bw_code_to_link_rate(dp->mode.bw_code); in zynqmp_dp_encoder_mode_set_stream()
1266 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_M_VID, mode->clock); in zynqmp_dp_encoder_mode_set_stream()
1267 rate = zynqmp_disp_get_audio_clk_rate(dp->dpsub->disp); in zynqmp_dp_encoder_mode_set_stream()
1269 dev_dbg(dp->dev, "Audio rate: %d\n", rate / 512); in zynqmp_dp_encoder_mode_set_stream()
1276 if (zynqmp_disp_audio_enabled(dp->dpsub->disp)) in zynqmp_dp_encoder_mode_set_stream()
1282 wpl = (mode->hdisplay * dp->config.bpp + 15) / 16; in zynqmp_dp_encoder_mode_set_stream()
1283 reg = wpl + wpl % lane_cnt - lane_cnt; in zynqmp_dp_encoder_mode_set_stream()
1287 /* -----------------------------------------------------------------------------
1295 struct zynqmp_dp_link_config *link_config = &dp->link_config; in zynqmp_dp_connector_detect()
1311 ret = drm_dp_dpcd_read(&dp->aux, 0x0, dp->dpcd, in zynqmp_dp_connector_detect()
1312 sizeof(dp->dpcd)); in zynqmp_dp_connector_detect()
1314 dev_dbg(dp->dev, "DPCD read failed"); in zynqmp_dp_connector_detect()
1318 link_config->max_rate = min_t(int, in zynqmp_dp_connector_detect()
1319 drm_dp_max_link_rate(dp->dpcd), in zynqmp_dp_connector_detect()
1321 link_config->max_lanes = min_t(u8, in zynqmp_dp_connector_detect()
1322 drm_dp_max_lane_count(dp->dpcd), in zynqmp_dp_connector_detect()
1323 dp->num_lanes); in zynqmp_dp_connector_detect()
1325 dp->status = connector_status_connected; in zynqmp_dp_connector_detect()
1330 dp->status = connector_status_disconnected; in zynqmp_dp_connector_detect()
1340 edid = drm_get_edid(connector, &dp->aux.ddc); in zynqmp_dp_connector_get_modes()
1356 return &dp->encoder; in zynqmp_dp_connector_best_encoder()
1363 u8 max_lanes = dp->link_config.max_lanes; in zynqmp_dp_connector_mode_valid()
1364 u8 bpp = dp->config.bpp; in zynqmp_dp_connector_mode_valid()
1365 int max_rate = dp->link_config.max_rate; in zynqmp_dp_connector_mode_valid()
1368 if (mode->clock > ZYNQMP_MAX_FREQ) { in zynqmp_dp_connector_mode_valid()
1369 dev_dbg(dp->dev, "filtered the mode, %s,for high pixel rate\n", in zynqmp_dp_connector_mode_valid()
1370 mode->name); in zynqmp_dp_connector_mode_valid()
1377 if (mode->clock > rate) { in zynqmp_dp_connector_mode_valid()
1378 dev_dbg(dp->dev, "filtered the mode, %s,for high pixel rate\n", in zynqmp_dp_connector_mode_valid()
1379 mode->name); in zynqmp_dp_connector_mode_valid()
1403 /* -----------------------------------------------------------------------------
1413 pm_runtime_get_sync(dp->dev); in zynqmp_dp_encoder_enable()
1414 dp->enabled = true; in zynqmp_dp_encoder_enable()
1416 if (zynqmp_disp_audio_enabled(dp->dpsub->disp)) in zynqmp_dp_encoder_enable()
1419 if (dp->status == connector_status_connected) { in zynqmp_dp_encoder_enable()
1421 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, in zynqmp_dp_encoder_enable()
1431 dev_dbg(dp->dev, "DP aux failed\n"); in zynqmp_dp_encoder_enable()
1443 dp->enabled = false; in zynqmp_dp_encoder_disable()
1444 cancel_delayed_work(&dp->hpd_work); in zynqmp_dp_encoder_disable()
1446 drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D3); in zynqmp_dp_encoder_disable()
1449 if (zynqmp_disp_audio_enabled(dp->dpsub->disp)) in zynqmp_dp_encoder_disable()
1451 pm_runtime_put_sync(dp->dev); in zynqmp_dp_encoder_disable()
1460 struct drm_display_mode *mode = &crtc_state->mode; in zynqmp_dp_encoder_atomic_mode_set()
1461 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; in zynqmp_dp_encoder_atomic_mode_set()
1462 u8 max_lanes = dp->link_config.max_lanes; in zynqmp_dp_encoder_atomic_mode_set()
1463 u8 bpp = dp->config.bpp; in zynqmp_dp_encoder_atomic_mode_set()
1464 int rate, max_rate = dp->link_config.max_rate; in zynqmp_dp_encoder_atomic_mode_set()
1471 if (mode->clock > rate) { in zynqmp_dp_encoder_atomic_mode_set()
1472 dev_err(dp->dev, "the mode, %s,has too high pixel rate\n", in zynqmp_dp_encoder_atomic_mode_set()
1473 mode->name); in zynqmp_dp_encoder_atomic_mode_set()
1477 ret = zynqmp_dp_mode_configure(dp, adjusted_mode->clock, 0); in zynqmp_dp_encoder_atomic_mode_set()
1492 struct drm_display_mode *mode = &crtc_state->mode; in zynqmp_dp_encoder_atomic_check()
1493 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; in zynqmp_dp_encoder_atomic_check()
1494 int diff = mode->htotal - mode->hsync_end; in zynqmp_dp_encoder_atomic_check()
1501 int vrefresh = (adjusted_mode->clock * 1000) / in zynqmp_dp_encoder_atomic_check()
1502 (adjusted_mode->vtotal * adjusted_mode->htotal); in zynqmp_dp_encoder_atomic_check()
1504 dev_dbg(encoder->dev->dev, "hbackporch adjusted: %d to %d", in zynqmp_dp_encoder_atomic_check()
1505 diff, ZYNQMP_DP_MIN_H_BACKPORCH - diff); in zynqmp_dp_encoder_atomic_check()
1506 diff = ZYNQMP_DP_MIN_H_BACKPORCH - diff; in zynqmp_dp_encoder_atomic_check()
1507 adjusted_mode->htotal += diff; in zynqmp_dp_encoder_atomic_check()
1508 adjusted_mode->clock = adjusted_mode->vtotal * in zynqmp_dp_encoder_atomic_check()
1509 adjusted_mode->htotal * vrefresh / 1000; in zynqmp_dp_encoder_atomic_check()
1522 /* -----------------------------------------------------------------------------
1527 * zynqmp_dp_enable_vblank - Enable vblank
1538 * zynqmp_dp_disable_vblank - Disable vblank
1554 if (dp->drm) in zynqmp_dp_hpd_work_func()
1555 drm_helper_hpd_irq_event(dp->drm); in zynqmp_dp_hpd_work_func()
1570 dev_dbg_ratelimited(dp->dev, "underflow interrupt\n"); in zynqmp_dp_irq_handler()
1572 dev_dbg_ratelimited(dp->dev, "overflow interrupt\n"); in zynqmp_dp_irq_handler()
1577 zynqmp_disp_handle_vblank(dp->dpsub->disp); in zynqmp_dp_irq_handler()
1580 schedule_delayed_work(&dp->hpd_work, 0); in zynqmp_dp_irq_handler()
1586 ret = drm_dp_dpcd_read(&dp->aux, DP_SINK_COUNT, status, in zynqmp_dp_irq_handler()
1592 !drm_dp_clock_recovery_ok(&status[2], dp->mode.lane_cnt) || in zynqmp_dp_irq_handler()
1593 !drm_dp_channel_eq_ok(&status[2], dp->mode.lane_cnt)) { in zynqmp_dp_irq_handler()
1602 /* -----------------------------------------------------------------------------
1608 struct zynqmp_dp *dp = dpsub->dp; in zynqmp_dp_drm_init()
1609 struct drm_encoder *encoder = &dp->encoder; in zynqmp_dp_drm_init()
1610 struct drm_connector *connector = &dp->connector; in zynqmp_dp_drm_init()
1613 dp->config.misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK; in zynqmp_dp_drm_init()
1617 encoder->possible_crtcs |= zynqmp_disp_get_crtc_mask(dpsub->disp); in zynqmp_dp_drm_init()
1618 drm_simple_encoder_init(dp->drm, encoder, DRM_MODE_ENCODER_TMDS); in zynqmp_dp_drm_init()
1621 connector->polled = DRM_CONNECTOR_POLL_HPD; in zynqmp_dp_drm_init()
1622 ret = drm_connector_init(encoder->dev, connector, in zynqmp_dp_drm_init()
1626 dev_err(dp->dev, "failed to create the DRM connector\n"); in zynqmp_dp_drm_init()
1637 dev_err(dp->dev, "failed to initialize DP aux\n"); in zynqmp_dp_drm_init()
1649 struct platform_device *pdev = to_platform_device(dpsub->dev); in zynqmp_dp_probe()
1656 return -ENOMEM; in zynqmp_dp_probe()
1658 dp->dev = &pdev->dev; in zynqmp_dp_probe()
1659 dp->dpsub = dpsub; in zynqmp_dp_probe()
1660 dp->status = connector_status_disconnected; in zynqmp_dp_probe()
1661 dp->drm = drm; in zynqmp_dp_probe()
1663 INIT_DELAYED_WORK(&dp->hpd_work, zynqmp_dp_hpd_work_func); in zynqmp_dp_probe()
1665 dpsub->dp = dp; in zynqmp_dp_probe()
1669 dp->iomem = devm_ioremap_resource(dp->dev, res); in zynqmp_dp_probe()
1670 if (IS_ERR(dp->iomem)) in zynqmp_dp_probe()
1671 return PTR_ERR(dp->iomem); in zynqmp_dp_probe()
1673 dp->irq = platform_get_irq(pdev, 0); in zynqmp_dp_probe()
1674 if (dp->irq < 0) in zynqmp_dp_probe()
1675 return dp->irq; in zynqmp_dp_probe()
1677 dp->reset = devm_reset_control_get(dp->dev, NULL); in zynqmp_dp_probe()
1678 if (IS_ERR(dp->reset)) { in zynqmp_dp_probe()
1679 if (PTR_ERR(dp->reset) != -EPROBE_DEFER) in zynqmp_dp_probe()
1680 dev_err(dp->dev, "failed to get reset: %ld\n", in zynqmp_dp_probe()
1681 PTR_ERR(dp->reset)); in zynqmp_dp_probe()
1682 return PTR_ERR(dp->reset); in zynqmp_dp_probe()
1707 ret = devm_request_threaded_irq(dp->dev, dp->irq, NULL, in zynqmp_dp_probe()
1709 dev_name(dp->dev), dp); in zynqmp_dp_probe()
1713 dev_dbg(dp->dev, "ZynqMP DisplayPort Tx probed with %u lanes\n", in zynqmp_dp_probe()
1714 dp->num_lanes); in zynqmp_dp_probe()
1725 struct zynqmp_dp *dp = dpsub->dp; in zynqmp_dp_remove()
1728 disable_irq(dp->irq); in zynqmp_dp_remove()
1730 cancel_delayed_work_sync(&dp->hpd_work); in zynqmp_dp_remove()