Lines Matching full:dp
40 MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in msec (default: 50)");
47 MODULE_PARM_DESC(power_on_delay_ms, "DP power on delay in msec (default: 4)");
267 * @misc0: misc0 configuration (per DP v1.2 spec)
268 * @misc1: misc1 configuration (per DP v1.2 spec)
289 * @phy: PHY handles for DP lanes
294 * @dpcd: DP configuration data from currently connected sink device
333 static void zynqmp_dp_write(struct zynqmp_dp *dp, int offset, u32 val) in zynqmp_dp_write() argument
335 writel(val, dp->iomem + offset); in zynqmp_dp_write()
338 static u32 zynqmp_dp_read(struct zynqmp_dp *dp, int offset) in zynqmp_dp_read() argument
340 return readl(dp->iomem + offset); in zynqmp_dp_read()
343 static void zynqmp_dp_clr(struct zynqmp_dp *dp, int offset, u32 clr) in zynqmp_dp_clr() argument
345 zynqmp_dp_write(dp, offset, zynqmp_dp_read(dp, offset) & ~clr); in zynqmp_dp_clr()
348 static void zynqmp_dp_set(struct zynqmp_dp *dp, int offset, u32 set) in zynqmp_dp_set() argument
350 zynqmp_dp_write(dp, offset, zynqmp_dp_read(dp, offset) | set); in zynqmp_dp_set()
359 static int zynqmp_dp_reset(struct zynqmp_dp *dp, bool assert) in zynqmp_dp_reset() argument
364 reset_control_assert(dp->reset); in zynqmp_dp_reset()
366 reset_control_deassert(dp->reset); in zynqmp_dp_reset()
371 bool status = !!reset_control_status(dp->reset); in zynqmp_dp_reset()
379 dev_err(dp->dev, "reset %s timeout\n", assert ? "assert" : "deassert"); in zynqmp_dp_reset()
385 * @dp: DisplayPort IP core structure
392 static int zynqmp_dp_phy_init(struct zynqmp_dp *dp) in zynqmp_dp_phy_init() argument
397 for (i = 0; i < dp->num_lanes; i++) { in zynqmp_dp_phy_init()
398 ret = phy_init(dp->phy[i]); in zynqmp_dp_phy_init()
400 dev_err(dp->dev, "failed to init phy lane %d\n", i); in zynqmp_dp_phy_init()
405 ret = zynqmp_dp_reset(dp, false); in zynqmp_dp_phy_init()
409 zynqmp_dp_clr(dp, ZYNQMP_DP_PHY_RESET, ZYNQMP_DP_PHY_RESET_ALL_RESET); in zynqmp_dp_phy_init()
415 for (i = dp->num_lanes - 1; i >= 0; i--) { in zynqmp_dp_phy_init()
416 ret = phy_power_on(dp->phy[i]); in zynqmp_dp_phy_init()
418 dev_err(dp->dev, "failed to power on phy lane %d\n", i); in zynqmp_dp_phy_init()
428 * @dp: DisplayPort IP core structure
432 static void zynqmp_dp_phy_exit(struct zynqmp_dp *dp) in zynqmp_dp_phy_exit() argument
437 for (i = 0; i < dp->num_lanes; i++) { in zynqmp_dp_phy_exit()
438 ret = phy_power_off(dp->phy[i]); in zynqmp_dp_phy_exit()
440 dev_err(dp->dev, "failed to power off phy(%d) %d\n", i, in zynqmp_dp_phy_exit()
444 zynqmp_dp_reset(dp, true); in zynqmp_dp_phy_exit()
446 for (i = 0; i < dp->num_lanes; i++) { in zynqmp_dp_phy_exit()
447 ret = phy_exit(dp->phy[i]); in zynqmp_dp_phy_exit()
449 dev_err(dp->dev, "failed to exit phy(%d) %d\n", i, ret); in zynqmp_dp_phy_exit()
455 * @dp: DisplayPort IP core structure
459 * found. The caller can check dp->num_lanes to check how many PHYs were found.
467 static int zynqmp_dp_phy_probe(struct zynqmp_dp *dp) in zynqmp_dp_phy_probe() argument
475 snprintf(phy_name, sizeof(phy_name), "dp-phy%d", i); in zynqmp_dp_phy_probe()
476 phy = devm_phy_get(dp->dev, phy_name); in zynqmp_dp_phy_probe()
481 if (dp->num_lanes) in zynqmp_dp_phy_probe()
484 dev_err(dp->dev, "no PHY found\n"); in zynqmp_dp_phy_probe()
491 dev_err(dp->dev, "failed to get PHY lane %u\n", in zynqmp_dp_phy_probe()
497 dp->phy[i] = phy; in zynqmp_dp_phy_probe()
498 dp->num_lanes++; in zynqmp_dp_phy_probe()
506 * @dp: DisplayPort IP core structure
513 static int zynqmp_dp_phy_ready(struct zynqmp_dp *dp) in zynqmp_dp_phy_ready() argument
517 ready = (1 << dp->num_lanes) - 1; in zynqmp_dp_phy_ready()
521 reg = zynqmp_dp_read(dp, ZYNQMP_DP_PHY_STATUS); in zynqmp_dp_phy_ready()
526 dev_err(dp->dev, "PHY isn't ready\n"); in zynqmp_dp_phy_ready()
555 * @dp: DisplayPort IP core structure
566 static int zynqmp_dp_mode_configure(struct zynqmp_dp *dp, int pclock, in zynqmp_dp_mode_configure() argument
569 int max_rate = dp->link_config.max_rate; in zynqmp_dp_mode_configure()
571 u8 max_lanes = dp->link_config.max_lanes; in zynqmp_dp_mode_configure()
573 u8 bpp = dp->config.bpp; in zynqmp_dp_mode_configure()
585 dev_err(dp->dev, "can't downshift. already lowest link rate\n"); in zynqmp_dp_mode_configure()
600 dp->mode.bw_code = bw_code; in zynqmp_dp_mode_configure()
601 dp->mode.lane_cnt = lane_cnt; in zynqmp_dp_mode_configure()
602 dp->mode.pclock = pclock; in zynqmp_dp_mode_configure()
603 return dp->mode.bw_code; in zynqmp_dp_mode_configure()
607 dev_err(dp->dev, "failed to configure link values\n"); in zynqmp_dp_mode_configure()
614 * @dp: DisplayPort IP core structure
617 static void zynqmp_dp_adjust_train(struct zynqmp_dp *dp, in zynqmp_dp_adjust_train() argument
620 u8 *train_set = dp->train_set; in zynqmp_dp_adjust_train()
624 for (i = 0; i < dp->mode.lane_cnt; i++) { in zynqmp_dp_adjust_train()
641 for (i = 0; i < dp->mode.lane_cnt; i++) in zynqmp_dp_adjust_train()
647 * @dp: DisplayPort IP core structure
655 static int zynqmp_dp_update_vs_emph(struct zynqmp_dp *dp) in zynqmp_dp_update_vs_emph() argument
660 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, dp->train_set, in zynqmp_dp_update_vs_emph()
661 dp->mode.lane_cnt); in zynqmp_dp_update_vs_emph()
665 for (i = 0; i < dp->mode.lane_cnt; i++) { in zynqmp_dp_update_vs_emph()
668 u8 train = dp->train_set[i]; in zynqmp_dp_update_vs_emph()
670 opts.dp.voltage[0] = (train & DP_TRAIN_VOLTAGE_SWING_MASK) in zynqmp_dp_update_vs_emph()
672 opts.dp.pre[0] = (train & DP_TRAIN_PRE_EMPHASIS_MASK) in zynqmp_dp_update_vs_emph()
675 phy_configure(dp->phy[i], &opts); in zynqmp_dp_update_vs_emph()
677 zynqmp_dp_write(dp, reg, 0x2); in zynqmp_dp_update_vs_emph()
685 * @dp: DisplayPort IP core structure
690 static int zynqmp_dp_link_train_cr(struct zynqmp_dp *dp) in zynqmp_dp_link_train_cr() argument
693 u8 lane_cnt = dp->mode.lane_cnt; in zynqmp_dp_link_train_cr()
699 zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET, in zynqmp_dp_link_train_cr()
701 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, in zynqmp_dp_link_train_cr()
712 ret = zynqmp_dp_update_vs_emph(dp); in zynqmp_dp_link_train_cr()
716 drm_dp_link_train_clock_recovery_delay(dp->dpcd); in zynqmp_dp_link_train_cr()
717 ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status); in zynqmp_dp_link_train_cr()
726 if (!(dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED)) in zynqmp_dp_link_train_cr()
731 if ((dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == vs) in zynqmp_dp_link_train_cr()
739 vs = dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in zynqmp_dp_link_train_cr()
740 zynqmp_dp_adjust_train(dp, link_status); in zynqmp_dp_link_train_cr()
751 * @dp: DisplayPort IP core structure
756 static int zynqmp_dp_link_train_ce(struct zynqmp_dp *dp) in zynqmp_dp_link_train_ce() argument
759 u8 lane_cnt = dp->mode.lane_cnt; in zynqmp_dp_link_train_ce()
764 if (dp->dpcd[DP_DPCD_REV] >= DP_V1_2 && in zynqmp_dp_link_train_ce()
765 dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) in zynqmp_dp_link_train_ce()
770 zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET, pat); in zynqmp_dp_link_train_ce()
771 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, in zynqmp_dp_link_train_ce()
777 ret = zynqmp_dp_update_vs_emph(dp); in zynqmp_dp_link_train_ce()
781 drm_dp_link_train_channel_eq_delay(dp->dpcd); in zynqmp_dp_link_train_ce()
782 ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status); in zynqmp_dp_link_train_ce()
790 zynqmp_dp_adjust_train(dp, link_status); in zynqmp_dp_link_train_ce()
801 * @dp: DisplayPort IP core structure
805 static int zynqmp_dp_train(struct zynqmp_dp *dp) in zynqmp_dp_train() argument
808 u8 bw_code = dp->mode.bw_code; in zynqmp_dp_train()
809 u8 lane_cnt = dp->mode.lane_cnt; in zynqmp_dp_train()
814 zynqmp_dp_write(dp, ZYNQMP_DP_LANE_COUNT_SET, lane_cnt); in zynqmp_dp_train()
815 enhanced = drm_dp_enhanced_frame_cap(dp->dpcd); in zynqmp_dp_train()
817 zynqmp_dp_write(dp, ZYNQMP_DP_ENHANCED_FRAME_EN, 1); in zynqmp_dp_train()
821 if (dp->dpcd[3] & 0x1) { in zynqmp_dp_train()
822 zynqmp_dp_write(dp, ZYNQMP_DP_DOWNSPREAD_CTL, 1); in zynqmp_dp_train()
823 drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL, in zynqmp_dp_train()
826 zynqmp_dp_write(dp, ZYNQMP_DP_DOWNSPREAD_CTL, 0); in zynqmp_dp_train()
827 drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL, 0); in zynqmp_dp_train()
830 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, aux_lane_cnt); in zynqmp_dp_train()
832 dev_err(dp->dev, "failed to set lane count\n"); in zynqmp_dp_train()
836 ret = drm_dp_dpcd_writeb(&dp->aux, DP_MAIN_LINK_CHANNEL_CODING_SET, in zynqmp_dp_train()
839 dev_err(dp->dev, "failed to set ANSI 8B/10B encoding\n"); in zynqmp_dp_train()
843 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LINK_BW_SET, bw_code); in zynqmp_dp_train()
845 dev_err(dp->dev, "failed to set DP bandwidth\n"); in zynqmp_dp_train()
849 zynqmp_dp_write(dp, ZYNQMP_DP_LINK_BW_SET, bw_code); in zynqmp_dp_train()
863 zynqmp_dp_write(dp, ZYNQMP_DP_PHY_CLOCK_SELECT, reg); in zynqmp_dp_train()
864 ret = zynqmp_dp_phy_ready(dp); in zynqmp_dp_train()
868 zynqmp_dp_write(dp, ZYNQMP_DP_SCRAMBLING_DISABLE, 1); in zynqmp_dp_train()
869 memset(dp->train_set, 0, 4); in zynqmp_dp_train()
870 ret = zynqmp_dp_link_train_cr(dp); in zynqmp_dp_train()
874 ret = zynqmp_dp_link_train_ce(dp); in zynqmp_dp_train()
878 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, in zynqmp_dp_train()
881 dev_err(dp->dev, "failed to disable training pattern\n"); in zynqmp_dp_train()
884 zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET, in zynqmp_dp_train()
887 zynqmp_dp_write(dp, ZYNQMP_DP_SCRAMBLING_DISABLE, 0); in zynqmp_dp_train()
894 * @dp: DisplayPort IP core structure
898 static void zynqmp_dp_train_loop(struct zynqmp_dp *dp) in zynqmp_dp_train_loop() argument
900 struct zynqmp_dp_mode *mode = &dp->mode; in zynqmp_dp_train_loop()
905 if (dp->status == connector_status_disconnected || in zynqmp_dp_train_loop()
906 !dp->enabled) in zynqmp_dp_train_loop()
909 ret = zynqmp_dp_train(dp); in zynqmp_dp_train_loop()
913 ret = zynqmp_dp_mode_configure(dp, mode->pclock, bw); in zynqmp_dp_train_loop()
921 dev_err(dp->dev, "failed to train the DP link\n"); in zynqmp_dp_train_loop()
932 * @dp: DisplayPort IP core structure
952 static int zynqmp_dp_aux_cmd_submit(struct zynqmp_dp *dp, u32 cmd, u16 addr, in zynqmp_dp_aux_cmd_submit() argument
958 reg = zynqmp_dp_read(dp, ZYNQMP_DP_INTERRUPT_SIGNAL_STATE); in zynqmp_dp_aux_cmd_submit()
962 zynqmp_dp_write(dp, ZYNQMP_DP_AUX_ADDRESS, addr); in zynqmp_dp_aux_cmd_submit()
965 zynqmp_dp_write(dp, ZYNQMP_DP_AUX_WRITE_FIFO, in zynqmp_dp_aux_cmd_submit()
973 zynqmp_dp_write(dp, ZYNQMP_DP_AUX_COMMAND, reg); in zynqmp_dp_aux_cmd_submit()
977 reg = zynqmp_dp_read(dp, ZYNQMP_DP_INTERRUPT_SIGNAL_STATE); in zynqmp_dp_aux_cmd_submit()
988 reg = zynqmp_dp_read(dp, ZYNQMP_DP_AUX_REPLY_CODE); in zynqmp_dp_aux_cmd_submit()
995 reg = zynqmp_dp_read(dp, ZYNQMP_DP_REPLY_DATA_COUNT); in zynqmp_dp_aux_cmd_submit()
1000 buf[i] = zynqmp_dp_read(dp, ZYNQMP_DP_AUX_REPLY_DATA); in zynqmp_dp_aux_cmd_submit()
1009 struct zynqmp_dp *dp = container_of(aux, struct zynqmp_dp, aux); in zynqmp_dp_aux_transfer() local
1018 ret = zynqmp_dp_aux_cmd_submit(dp, msg->request, msg->address, in zynqmp_dp_aux_transfer()
1022 dev_dbg(dp->dev, "aux %d retries\n", i); in zynqmp_dp_aux_transfer()
1026 if (dp->status == connector_status_disconnected) { in zynqmp_dp_aux_transfer()
1027 dev_dbg(dp->dev, "no connected aux device\n"); in zynqmp_dp_aux_transfer()
1034 dev_dbg(dp->dev, "failed to do aux transfer (%d)\n", ret); in zynqmp_dp_aux_transfer()
1040 * zynqmp_dp_aux_init - Initialize and register the DP AUX
1041 * @dp: DisplayPort IP core structure
1043 * Program the AUX clock divider and filter and register the DP AUX adapter.
1047 static int zynqmp_dp_aux_init(struct zynqmp_dp *dp) in zynqmp_dp_aux_init() argument
1059 rate = clk_get_rate(dp->dpsub->apb_clk); in zynqmp_dp_aux_init()
1062 dev_err(dp->dev, "aclk frequency too high\n"); in zynqmp_dp_aux_init()
1066 zynqmp_dp_write(dp, ZYNQMP_DP_AUX_CLK_DIVIDER, in zynqmp_dp_aux_init()
1070 dp->aux.name = "ZynqMP DP AUX"; in zynqmp_dp_aux_init()
1071 dp->aux.dev = dp->dev; in zynqmp_dp_aux_init()
1072 dp->aux.transfer = zynqmp_dp_aux_transfer; in zynqmp_dp_aux_init()
1074 return drm_dp_aux_register(&dp->aux); in zynqmp_dp_aux_init()
1078 * zynqmp_dp_aux_cleanup - Cleanup the DP AUX
1079 * @dp: DisplayPort IP core structure
1081 * Unregister the DP AUX adapter.
1083 static void zynqmp_dp_aux_cleanup(struct zynqmp_dp *dp) in zynqmp_dp_aux_cleanup() argument
1085 drm_dp_aux_unregister(&dp->aux); in zynqmp_dp_aux_cleanup()
1094 * @dp: DisplayPort IP core structure
1099 static void zynqmp_dp_update_misc(struct zynqmp_dp *dp) in zynqmp_dp_update_misc() argument
1101 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_MISC0, dp->config.misc0); in zynqmp_dp_update_misc()
1102 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_MISC1, dp->config.misc1); in zynqmp_dp_update_misc()
1107 * @dp: DisplayPort IP core structure
1115 static int zynqmp_dp_set_format(struct zynqmp_dp *dp, in zynqmp_dp_set_format() argument
1120 struct zynqmp_dp_config *config = &dp->config; in zynqmp_dp_set_format()
1148 dev_err(dp->dev, "Invalid colormetry in DT\n"); in zynqmp_dp_set_format()
1152 display = &dp->connector.display_info; in zynqmp_dp_set_format()
1154 dev_warn(dp->dev, in zynqmp_dp_set_format()
1179 dev_warn(dp->dev, "Not supported bpc (%u). fall back to 8bpc\n", in zynqmp_dp_set_format()
1194 * @dp: DisplayPort IP core structure
1198 * Calculation is based on DP and IP core specification.
1201 zynqmp_dp_encoder_mode_set_transfer_unit(struct zynqmp_dp *dp, in zynqmp_dp_encoder_mode_set_transfer_unit() argument
1208 zynqmp_dp_write(dp, ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE, tu); in zynqmp_dp_encoder_mode_set_transfer_unit()
1210 vid_kbytes = mode->clock * (dp->config.bpp / 8); in zynqmp_dp_encoder_mode_set_transfer_unit()
1211 bw = drm_dp_bw_code_to_link_rate(dp->mode.bw_code); in zynqmp_dp_encoder_mode_set_transfer_unit()
1212 avg_bytes_per_tu = vid_kbytes * tu / (dp->mode.lane_cnt * bw / 1000); in zynqmp_dp_encoder_mode_set_transfer_unit()
1213 zynqmp_dp_write(dp, ZYNQMP_DP_MIN_BYTES_PER_TU, in zynqmp_dp_encoder_mode_set_transfer_unit()
1215 zynqmp_dp_write(dp, ZYNQMP_DP_FRAC_BYTES_PER_TU, in zynqmp_dp_encoder_mode_set_transfer_unit()
1226 zynqmp_dp_write(dp, ZYNQMP_DP_INIT_WAIT, init_wait); in zynqmp_dp_encoder_mode_set_transfer_unit()
1231 * @dp: DisplayPort IP core structure
1237 static void zynqmp_dp_encoder_mode_set_stream(struct zynqmp_dp *dp, in zynqmp_dp_encoder_mode_set_stream() argument
1240 u8 lane_cnt = dp->mode.lane_cnt; in zynqmp_dp_encoder_mode_set_stream()
1244 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HTOTAL, mode->htotal); in zynqmp_dp_encoder_mode_set_stream()
1245 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VTOTAL, mode->vtotal); in zynqmp_dp_encoder_mode_set_stream()
1246 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_POLARITY, in zynqmp_dp_encoder_mode_set_stream()
1251 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HSWIDTH, in zynqmp_dp_encoder_mode_set_stream()
1253 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VSWIDTH, in zynqmp_dp_encoder_mode_set_stream()
1255 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HRES, mode->hdisplay); in zynqmp_dp_encoder_mode_set_stream()
1256 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VRES, mode->vdisplay); in zynqmp_dp_encoder_mode_set_stream()
1257 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HSTART, in zynqmp_dp_encoder_mode_set_stream()
1259 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VSTART, in zynqmp_dp_encoder_mode_set_stream()
1263 if (dp->config.misc0 & ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK) { in zynqmp_dp_encoder_mode_set_stream()
1264 reg = drm_dp_bw_code_to_link_rate(dp->mode.bw_code); in zynqmp_dp_encoder_mode_set_stream()
1265 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_N_VID, reg); in zynqmp_dp_encoder_mode_set_stream()
1266 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_M_VID, mode->clock); in zynqmp_dp_encoder_mode_set_stream()
1267 rate = zynqmp_disp_get_audio_clk_rate(dp->dpsub->disp); in zynqmp_dp_encoder_mode_set_stream()
1269 dev_dbg(dp->dev, "Audio rate: %d\n", rate / 512); in zynqmp_dp_encoder_mode_set_stream()
1270 zynqmp_dp_write(dp, ZYNQMP_DP_TX_N_AUD, reg); in zynqmp_dp_encoder_mode_set_stream()
1271 zynqmp_dp_write(dp, ZYNQMP_DP_TX_M_AUD, rate / 1000); in zynqmp_dp_encoder_mode_set_stream()
1276 if (zynqmp_disp_audio_enabled(dp->dpsub->disp)) in zynqmp_dp_encoder_mode_set_stream()
1277 zynqmp_dp_write(dp, ZYNQMP_DP_TX_AUDIO_CHANNELS, 1); in zynqmp_dp_encoder_mode_set_stream()
1279 zynqmp_dp_write(dp, ZYNQMP_DP_USER_PIX_WIDTH, 1); in zynqmp_dp_encoder_mode_set_stream()
1282 wpl = (mode->hdisplay * dp->config.bpp + 15) / 16; in zynqmp_dp_encoder_mode_set_stream()
1284 zynqmp_dp_write(dp, ZYNQMP_DP_USER_DATA_COUNT_PER_LANE, reg); in zynqmp_dp_encoder_mode_set_stream()
1294 struct zynqmp_dp *dp = connector_to_dp(connector); in zynqmp_dp_connector_detect() local
1295 struct zynqmp_dp_link_config *link_config = &dp->link_config; in zynqmp_dp_connector_detect()
1304 state = zynqmp_dp_read(dp, ZYNQMP_DP_INTERRUPT_SIGNAL_STATE); in zynqmp_dp_connector_detect()
1311 ret = drm_dp_dpcd_read(&dp->aux, 0x0, dp->dpcd, in zynqmp_dp_connector_detect()
1312 sizeof(dp->dpcd)); in zynqmp_dp_connector_detect()
1314 dev_dbg(dp->dev, "DPCD read failed"); in zynqmp_dp_connector_detect()
1319 drm_dp_max_link_rate(dp->dpcd), in zynqmp_dp_connector_detect()
1322 drm_dp_max_lane_count(dp->dpcd), in zynqmp_dp_connector_detect()
1323 dp->num_lanes); in zynqmp_dp_connector_detect()
1325 dp->status = connector_status_connected; in zynqmp_dp_connector_detect()
1330 dp->status = connector_status_disconnected; in zynqmp_dp_connector_detect()
1336 struct zynqmp_dp *dp = connector_to_dp(connector); in zynqmp_dp_connector_get_modes() local
1340 edid = drm_get_edid(connector, &dp->aux.ddc); in zynqmp_dp_connector_get_modes()
1354 struct zynqmp_dp *dp = connector_to_dp(connector); in zynqmp_dp_connector_best_encoder() local
1356 return &dp->encoder; in zynqmp_dp_connector_best_encoder()
1362 struct zynqmp_dp *dp = connector_to_dp(connector); in zynqmp_dp_connector_mode_valid() local
1363 u8 max_lanes = dp->link_config.max_lanes; in zynqmp_dp_connector_mode_valid()
1364 u8 bpp = dp->config.bpp; in zynqmp_dp_connector_mode_valid()
1365 int max_rate = dp->link_config.max_rate; in zynqmp_dp_connector_mode_valid()
1369 dev_dbg(dp->dev, "filtered the mode, %s,for high pixel rate\n", in zynqmp_dp_connector_mode_valid()
1378 dev_dbg(dp->dev, "filtered the mode, %s,for high pixel rate\n", in zynqmp_dp_connector_mode_valid()
1409 struct zynqmp_dp *dp = encoder_to_dp(encoder); in zynqmp_dp_encoder_enable() local
1413 pm_runtime_get_sync(dp->dev); in zynqmp_dp_encoder_enable()
1414 dp->enabled = true; in zynqmp_dp_encoder_enable()
1415 zynqmp_dp_update_misc(dp); in zynqmp_dp_encoder_enable()
1416 if (zynqmp_disp_audio_enabled(dp->dpsub->disp)) in zynqmp_dp_encoder_enable()
1417 zynqmp_dp_write(dp, ZYNQMP_DP_TX_AUDIO_CONTROL, 1); in zynqmp_dp_encoder_enable()
1418 zynqmp_dp_write(dp, ZYNQMP_DP_TX_PHY_POWER_DOWN, 0); in zynqmp_dp_encoder_enable()
1419 if (dp->status == connector_status_connected) { in zynqmp_dp_encoder_enable()
1421 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, in zynqmp_dp_encoder_enable()
1431 dev_dbg(dp->dev, "DP aux failed\n"); in zynqmp_dp_encoder_enable()
1433 zynqmp_dp_train_loop(dp); in zynqmp_dp_encoder_enable()
1434 zynqmp_dp_write(dp, ZYNQMP_DP_SOFTWARE_RESET, in zynqmp_dp_encoder_enable()
1436 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_ENABLE, 1); in zynqmp_dp_encoder_enable()
1441 struct zynqmp_dp *dp = encoder_to_dp(encoder); in zynqmp_dp_encoder_disable() local
1443 dp->enabled = false; in zynqmp_dp_encoder_disable()
1444 cancel_delayed_work(&dp->hpd_work); in zynqmp_dp_encoder_disable()
1445 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_ENABLE, 0); in zynqmp_dp_encoder_disable()
1446 drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D3); in zynqmp_dp_encoder_disable()
1447 zynqmp_dp_write(dp, ZYNQMP_DP_TX_PHY_POWER_DOWN, in zynqmp_dp_encoder_disable()
1449 if (zynqmp_disp_audio_enabled(dp->dpsub->disp)) in zynqmp_dp_encoder_disable()
1450 zynqmp_dp_write(dp, ZYNQMP_DP_TX_AUDIO_CONTROL, 0); in zynqmp_dp_encoder_disable()
1451 pm_runtime_put_sync(dp->dev); in zynqmp_dp_encoder_disable()
1459 struct zynqmp_dp *dp = encoder_to_dp(encoder); in zynqmp_dp_encoder_atomic_mode_set() local
1462 u8 max_lanes = dp->link_config.max_lanes; in zynqmp_dp_encoder_atomic_mode_set()
1463 u8 bpp = dp->config.bpp; in zynqmp_dp_encoder_atomic_mode_set()
1464 int rate, max_rate = dp->link_config.max_rate; in zynqmp_dp_encoder_atomic_mode_set()
1467 zynqmp_dp_set_format(dp, ZYNQMP_DPSUB_FORMAT_RGB, 8); in zynqmp_dp_encoder_atomic_mode_set()
1472 dev_err(dp->dev, "the mode, %s,has too high pixel rate\n", in zynqmp_dp_encoder_atomic_mode_set()
1477 ret = zynqmp_dp_mode_configure(dp, adjusted_mode->clock, 0); in zynqmp_dp_encoder_atomic_mode_set()
1481 zynqmp_dp_encoder_mode_set_transfer_unit(dp, adjusted_mode); in zynqmp_dp_encoder_atomic_mode_set()
1482 zynqmp_dp_encoder_mode_set_stream(dp, adjusted_mode); in zynqmp_dp_encoder_atomic_mode_set()
1497 * ZynqMP DP requires horizontal backporch to be greater than 12. in zynqmp_dp_encoder_atomic_check()
1528 * @dp: DisplayPort IP core structure
1532 void zynqmp_dp_enable_vblank(struct zynqmp_dp *dp) in zynqmp_dp_enable_vblank() argument
1534 zynqmp_dp_write(dp, ZYNQMP_DP_INT_EN, ZYNQMP_DP_INT_VBLANK_START); in zynqmp_dp_enable_vblank()
1539 * @dp: DisplayPort IP core structure
1543 void zynqmp_dp_disable_vblank(struct zynqmp_dp *dp) in zynqmp_dp_disable_vblank() argument
1545 zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, ZYNQMP_DP_INT_VBLANK_START); in zynqmp_dp_disable_vblank()
1550 struct zynqmp_dp *dp; in zynqmp_dp_hpd_work_func() local
1552 dp = container_of(work, struct zynqmp_dp, hpd_work.work); in zynqmp_dp_hpd_work_func()
1554 if (dp->drm) in zynqmp_dp_hpd_work_func()
1555 drm_helper_hpd_irq_event(dp->drm); in zynqmp_dp_hpd_work_func()
1560 struct zynqmp_dp *dp = (struct zynqmp_dp *)data; in zynqmp_dp_irq_handler() local
1563 status = zynqmp_dp_read(dp, ZYNQMP_DP_INT_STATUS); in zynqmp_dp_irq_handler()
1564 mask = zynqmp_dp_read(dp, ZYNQMP_DP_INT_MASK); in zynqmp_dp_irq_handler()
1570 dev_dbg_ratelimited(dp->dev, "underflow interrupt\n"); in zynqmp_dp_irq_handler()
1572 dev_dbg_ratelimited(dp->dev, "overflow interrupt\n"); in zynqmp_dp_irq_handler()
1574 zynqmp_dp_write(dp, ZYNQMP_DP_INT_STATUS, status); in zynqmp_dp_irq_handler()
1577 zynqmp_disp_handle_vblank(dp->dpsub->disp); in zynqmp_dp_irq_handler()
1580 schedule_delayed_work(&dp->hpd_work, 0); in zynqmp_dp_irq_handler()
1586 ret = drm_dp_dpcd_read(&dp->aux, DP_SINK_COUNT, status, in zynqmp_dp_irq_handler()
1592 !drm_dp_clock_recovery_ok(&status[2], dp->mode.lane_cnt) || in zynqmp_dp_irq_handler()
1593 !drm_dp_channel_eq_ok(&status[2], dp->mode.lane_cnt)) { in zynqmp_dp_irq_handler()
1594 zynqmp_dp_train_loop(dp); in zynqmp_dp_irq_handler()
1608 struct zynqmp_dp *dp = dpsub->dp; in zynqmp_dp_drm_init() local
1609 struct drm_encoder *encoder = &dp->encoder; in zynqmp_dp_drm_init()
1610 struct drm_connector *connector = &dp->connector; in zynqmp_dp_drm_init()
1613 dp->config.misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK; in zynqmp_dp_drm_init()
1614 zynqmp_dp_set_format(dp, ZYNQMP_DPSUB_FORMAT_RGB, 8); in zynqmp_dp_drm_init()
1618 drm_simple_encoder_init(dp->drm, encoder, DRM_MODE_ENCODER_TMDS); in zynqmp_dp_drm_init()
1626 dev_err(dp->dev, "failed to create the DRM connector\n"); in zynqmp_dp_drm_init()
1635 ret = zynqmp_dp_aux_init(dp); in zynqmp_dp_drm_init()
1637 dev_err(dp->dev, "failed to initialize DP aux\n"); in zynqmp_dp_drm_init()
1642 zynqmp_dp_write(dp, ZYNQMP_DP_INT_EN, ZYNQMP_DP_INT_ALL); in zynqmp_dp_drm_init()
1650 struct zynqmp_dp *dp; in zynqmp_dp_probe() local
1654 dp = drmm_kzalloc(drm, sizeof(*dp), GFP_KERNEL); in zynqmp_dp_probe()
1655 if (!dp) in zynqmp_dp_probe()
1658 dp->dev = &pdev->dev; in zynqmp_dp_probe()
1659 dp->dpsub = dpsub; in zynqmp_dp_probe()
1660 dp->status = connector_status_disconnected; in zynqmp_dp_probe()
1661 dp->drm = drm; in zynqmp_dp_probe()
1663 INIT_DELAYED_WORK(&dp->hpd_work, zynqmp_dp_hpd_work_func); in zynqmp_dp_probe()
1665 dpsub->dp = dp; in zynqmp_dp_probe()
1668 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dp"); in zynqmp_dp_probe()
1669 dp->iomem = devm_ioremap_resource(dp->dev, res); in zynqmp_dp_probe()
1670 if (IS_ERR(dp->iomem)) in zynqmp_dp_probe()
1671 return PTR_ERR(dp->iomem); in zynqmp_dp_probe()
1673 dp->irq = platform_get_irq(pdev, 0); in zynqmp_dp_probe()
1674 if (dp->irq < 0) in zynqmp_dp_probe()
1675 return dp->irq; in zynqmp_dp_probe()
1677 dp->reset = devm_reset_control_get(dp->dev, NULL); in zynqmp_dp_probe()
1678 if (IS_ERR(dp->reset)) { in zynqmp_dp_probe()
1679 if (PTR_ERR(dp->reset) != -EPROBE_DEFER) in zynqmp_dp_probe()
1680 dev_err(dp->dev, "failed to get reset: %ld\n", in zynqmp_dp_probe()
1681 PTR_ERR(dp->reset)); in zynqmp_dp_probe()
1682 return PTR_ERR(dp->reset); in zynqmp_dp_probe()
1685 ret = zynqmp_dp_phy_probe(dp); in zynqmp_dp_probe()
1690 zynqmp_dp_write(dp, ZYNQMP_DP_TX_PHY_POWER_DOWN, in zynqmp_dp_probe()
1692 zynqmp_dp_set(dp, ZYNQMP_DP_PHY_RESET, ZYNQMP_DP_PHY_RESET_ALL_RESET); in zynqmp_dp_probe()
1693 zynqmp_dp_write(dp, ZYNQMP_DP_FORCE_SCRAMBLER_RESET, 1); in zynqmp_dp_probe()
1694 zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMITTER_ENABLE, 0); in zynqmp_dp_probe()
1695 zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, 0xffffffff); in zynqmp_dp_probe()
1697 ret = zynqmp_dp_phy_init(dp); in zynqmp_dp_probe()
1701 zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMITTER_ENABLE, 1); in zynqmp_dp_probe()
1707 ret = devm_request_threaded_irq(dp->dev, dp->irq, NULL, in zynqmp_dp_probe()
1709 dev_name(dp->dev), dp); in zynqmp_dp_probe()
1713 dev_dbg(dp->dev, "ZynqMP DisplayPort Tx probed with %u lanes\n", in zynqmp_dp_probe()
1714 dp->num_lanes); in zynqmp_dp_probe()
1719 zynqmp_dp_phy_exit(dp); in zynqmp_dp_probe()
1725 struct zynqmp_dp *dp = dpsub->dp; in zynqmp_dp_remove() local
1727 zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, ZYNQMP_DP_INT_ALL); in zynqmp_dp_remove()
1728 disable_irq(dp->irq); in zynqmp_dp_remove()
1730 cancel_delayed_work_sync(&dp->hpd_work); in zynqmp_dp_remove()
1731 zynqmp_dp_aux_cleanup(dp); in zynqmp_dp_remove()
1733 zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMITTER_ENABLE, 0); in zynqmp_dp_remove()
1734 zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, 0xffffffff); in zynqmp_dp_remove()
1736 zynqmp_dp_phy_exit(dp); in zynqmp_dp_remove()