Lines Matching +full:matrix +full:- +full:connected
1 // SPDX-License-Identifier: GPL-2.0-only
66 struct drm_device *dev = state->dev; in vc4_get_ctm_state()
71 ret = drm_modeset_lock(&vc4->ctm_state_lock, state->acquire_ctx); in vc4_get_ctm_state()
87 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); in vc4_ctm_duplicate_state()
91 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); in vc4_ctm_duplicate_state()
93 return &state->base; in vc4_ctm_duplicate_state()
113 drm_atomic_private_obj_fini(&vc4->ctm_manager); in vc4_ctm_obj_fini()
120 drm_modeset_lock_init(&vc4->ctm_state_lock); in vc4_ctm_obj_init()
124 return -ENOMEM; in vc4_ctm_obj_init()
126 drm_atomic_private_obj_init(&vc4->base, &vc4->ctm_manager, &ctm_state->base, in vc4_ctm_obj_init()
129 return drmm_add_action_or_reset(&vc4->base, vc4_ctm_obj_fini, NULL); in vc4_ctm_obj_init()
154 struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(vc4->ctm_manager.state); in vc4_ctm_commit()
155 struct drm_color_ctm *ctm = ctm_state->ctm; in vc4_ctm_commit()
157 if (ctm_state->fifo) { in vc4_ctm_commit()
159 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]), in vc4_ctm_commit()
161 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[3]), in vc4_ctm_commit()
163 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[6]), in vc4_ctm_commit()
166 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[1]), in vc4_ctm_commit()
168 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[4]), in vc4_ctm_commit()
170 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[7]), in vc4_ctm_commit()
173 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[2]), in vc4_ctm_commit()
175 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[5]), in vc4_ctm_commit()
177 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[8]), in vc4_ctm_commit()
182 VC4_SET_FIELD(ctm_state->fifo, SCALER_OLEDOFFS_DISPFIFO)); in vc4_ctm_commit()
188 struct vc4_dev *vc4 = to_vc4_dev(state->dev); in vc4_hvs_get_global_state()
191 priv_state = drm_atomic_get_private_obj_state(state, &vc4->hvs_channels); in vc4_hvs_get_global_state()
210 if (!crtc_state->active) in vc4_hvs_pv_muxing_commit()
213 if (vc4_state->assigned_channel != 2) in vc4_hvs_pv_muxing_commit()
221 * DSP3 is connected to FIFO2 unless the transposer is in vc4_hvs_pv_muxing_commit()
223 * TXP IP, and we need to disable the FIFO2 -> pixelvalve1 in vc4_hvs_pv_muxing_commit()
226 if (vc4_state->feed_txp) in vc4_hvs_pv_muxing_commit()
250 if (!vc4_state->update_muxing) in vc5_hvs_pv_muxing_commit()
253 switch (vc4_crtc->data->hvs_output) { in vc5_hvs_pv_muxing_commit()
255 mux = (vc4_state->assigned_channel == 2) ? 0 : 1; in vc5_hvs_pv_muxing_commit()
263 if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED) in vc5_hvs_pv_muxing_commit()
266 mux = vc4_state->assigned_channel; in vc5_hvs_pv_muxing_commit()
275 if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED) in vc5_hvs_pv_muxing_commit()
278 mux = vc4_state->assigned_channel; in vc5_hvs_pv_muxing_commit()
288 if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED) in vc5_hvs_pv_muxing_commit()
291 mux = vc4_state->assigned_channel; in vc5_hvs_pv_muxing_commit()
308 struct drm_device *dev = state->dev; in vc4_atomic_complete_commit()
310 struct vc4_hvs *hvs = vc4->hvs; in vc4_atomic_complete_commit()
318 if (!new_crtc_state->commit) in vc4_atomic_complete_commit()
322 vc4_hvs_mask_underrun(dev, vc4_crtc_state->assigned_channel); in vc4_atomic_complete_commit()
325 if (vc4->hvs->hvs5) in vc4_atomic_complete_commit()
326 clk_set_min_rate(hvs->core_clk, 500000000); in vc4_atomic_complete_commit()
336 if (vc4->hvs->hvs5) in vc4_atomic_complete_commit()
355 if (vc4->hvs->hvs5) in vc4_atomic_complete_commit()
356 clk_set_min_rate(hvs->core_clk, 0); in vc4_atomic_complete_commit()
360 up(&vc4->async_modeset); in vc4_atomic_complete_commit()
372 * vc4_atomic_commit - commit validated state object
377 * This function commits a with drm_atomic_helper_check() pre-validated state
382 * Zero for success or -errno.
391 if (state->async_update) { in vc4_atomic_commit()
392 ret = down_interruptible(&vc4->async_modeset); in vc4_atomic_commit()
398 up(&vc4->async_modeset); in vc4_atomic_commit()
406 up(&vc4->async_modeset); in vc4_atomic_commit()
412 * state->legacy_cursor_update to false to prevent in vc4_atomic_commit()
413 * drm_atomic_helper_setup_commit() from auto-completing in vc4_atomic_commit()
414 * commit->flip_done. in vc4_atomic_commit()
416 state->legacy_cursor_update = false; in vc4_atomic_commit()
421 INIT_WORK(&state->commit_work, commit_work); in vc4_atomic_commit()
423 ret = down_interruptible(&vc4->async_modeset); in vc4_atomic_commit()
429 up(&vc4->async_modeset); in vc4_atomic_commit()
437 up(&vc4->async_modeset); in vc4_atomic_commit()
443 * This is the point of no return - everything below never fails except in vc4_atomic_commit()
468 queue_work(system_unbound_wq, &state->commit_work); in vc4_atomic_commit()
484 if (!(mode_cmd->flags & DRM_MODE_FB_MODIFIERS)) { in vc4_fb_create()
489 mode_cmd->handles[0]); in vc4_fb_create()
492 mode_cmd->handles[0]); in vc4_fb_create()
493 return ERR_PTR(-ENOENT); in vc4_fb_create()
499 if (bo->t_format) { in vc4_fb_create()
530 if (!new_crtc_state->ctm && old_crtc_state->ctm) { in vc4_ctm_atomic_check()
531 ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager); in vc4_ctm_atomic_check()
534 ctm_state->fifo = 0; in vc4_ctm_atomic_check()
539 if (new_crtc_state->ctm == old_crtc_state->ctm) in vc4_ctm_atomic_check()
543 ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager); in vc4_ctm_atomic_check()
548 /* CTM is being enabled or the matrix changed. */ in vc4_ctm_atomic_check()
549 if (new_crtc_state->ctm) { in vc4_ctm_atomic_check()
553 /* fifo is 1-based since 0 disables CTM. */ in vc4_ctm_atomic_check()
554 int fifo = vc4_crtc_state->assigned_channel + 1; in vc4_ctm_atomic_check()
559 if (ctm_state->fifo && ctm_state->fifo != fifo) { in vc4_ctm_atomic_check()
561 return -EINVAL; in vc4_ctm_atomic_check()
568 ctm = new_crtc_state->ctm->data; in vc4_ctm_atomic_check()
569 for (i = 0; i < ARRAY_SIZE(ctm->matrix); i++) { in vc4_ctm_atomic_check()
570 u64 val = ctm->matrix[i]; in vc4_ctm_atomic_check()
574 return -EINVAL; in vc4_ctm_atomic_check()
577 ctm_state->fifo = fifo; in vc4_ctm_atomic_check()
578 ctm_state->ctm = ctm; in vc4_ctm_atomic_check()
588 struct vc4_dev *vc4 = to_vc4_dev(state->dev); in vc4_load_tracker_atomic_check()
594 if (!vc4->load_tracker_available) in vc4_load_tracker_atomic_check()
598 &vc4->load_tracker); in vc4_load_tracker_atomic_check()
607 if (old_plane_state->fb && old_plane_state->crtc) { in vc4_load_tracker_atomic_check()
609 load_state->membus_load -= vc4_plane_state->membus_load; in vc4_load_tracker_atomic_check()
610 load_state->hvs_load -= vc4_plane_state->hvs_load; in vc4_load_tracker_atomic_check()
613 if (new_plane_state->fb && new_plane_state->crtc) { in vc4_load_tracker_atomic_check()
615 load_state->membus_load += vc4_plane_state->membus_load; in vc4_load_tracker_atomic_check()
616 load_state->hvs_load += vc4_plane_state->hvs_load; in vc4_load_tracker_atomic_check()
621 if (!vc4->load_tracker_enabled) in vc4_load_tracker_atomic_check()
627 if (load_state->membus_load > SZ_1G + SZ_512M) in vc4_load_tracker_atomic_check()
628 return -ENOSPC; in vc4_load_tracker_atomic_check()
633 if (load_state->hvs_load > 240000000ULL) in vc4_load_tracker_atomic_check()
634 return -ENOSPC; in vc4_load_tracker_atomic_check()
644 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); in vc4_load_tracker_duplicate_state()
648 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); in vc4_load_tracker_duplicate_state()
650 return &state->base; in vc4_load_tracker_duplicate_state()
671 if (!vc4->load_tracker_available) in vc4_load_tracker_obj_fini()
674 drm_atomic_private_obj_fini(&vc4->load_tracker); in vc4_load_tracker_obj_fini()
681 if (!vc4->load_tracker_available) in vc4_load_tracker_obj_init()
686 return -ENOMEM; in vc4_load_tracker_obj_init()
688 drm_atomic_private_obj_init(&vc4->base, &vc4->load_tracker, in vc4_load_tracker_obj_init()
689 &load_state->base, in vc4_load_tracker_obj_init()
692 return drmm_add_action_or_reset(&vc4->base, vc4_load_tracker_obj_fini, NULL); in vc4_load_tracker_obj_init()
698 struct vc4_hvs_state *old_state = to_vc4_hvs_state(obj->state); in vc4_hvs_channels_duplicate_state()
705 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); in vc4_hvs_channels_duplicate_state()
707 state->unassigned_channels = old_state->unassigned_channels; in vc4_hvs_channels_duplicate_state()
709 return &state->base; in vc4_hvs_channels_duplicate_state()
729 drm_atomic_private_obj_fini(&vc4->hvs_channels); in vc4_hvs_channels_obj_fini()
738 return -ENOMEM; in vc4_hvs_channels_obj_init()
740 state->unassigned_channels = GENMASK(HVS_NUM_CHANNELS - 1, 0); in vc4_hvs_channels_obj_init()
741 drm_atomic_private_obj_init(&vc4->base, &vc4->hvs_channels, in vc4_hvs_channels_obj_init()
742 &state->base, in vc4_hvs_channels_obj_init()
745 return drmm_add_action_or_reset(&vc4->base, vc4_hvs_channels_obj_fini, NULL); in vc4_hvs_channels_obj_init()
749 * The BCM2711 HVS has up to 7 outputs connected to the pixelvalves and
757 * - When running in a dual-display setup (so with two CRTCs involved),
764 * - To fix the above, we can't use drm_atomic_get_crtc_state on all
770 * doing a modetest -v first on HDMI1 and then on HDMI0.
772 * - Since we need the pixelvalve to be disabled and enabled back when
788 return -EINVAL; in vc4_pv_muxing_atomic_check()
799 if (old_crtc_state->enable == new_crtc_state->enable) in vc4_pv_muxing_atomic_check()
803 new_vc4_crtc_state->update_muxing = true; in vc4_pv_muxing_atomic_check()
806 if (!new_crtc_state->enable) { in vc4_pv_muxing_atomic_check()
807 hvs_new_state->unassigned_channels |= BIT(old_vc4_crtc_state->assigned_channel); in vc4_pv_muxing_atomic_check()
808 new_vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED; in vc4_pv_muxing_atomic_check()
814 * up to 7 encoders, connected to up to 6 CRTCs. in vc4_pv_muxing_atomic_check()
836 matching_channels = hvs_new_state->unassigned_channels & vc4_crtc->data->hvs_available_channels; in vc4_pv_muxing_atomic_check()
838 unsigned int channel = ffs(matching_channels) - 1; in vc4_pv_muxing_atomic_check()
840 new_vc4_crtc_state->assigned_channel = channel; in vc4_pv_muxing_atomic_check()
841 hvs_new_state->unassigned_channels &= ~BIT(channel); in vc4_pv_muxing_atomic_check()
843 return -EINVAL; in vc4_pv_muxing_atomic_check()
879 bool is_vc5 = of_device_is_compatible(dev->dev->of_node, in vc4_kms_load()
880 "brcm,bcm2711-vc5"); in vc4_kms_load()
884 vc4->load_tracker_available = true; in vc4_kms_load()
889 vc4->load_tracker_enabled = true; in vc4_kms_load()
892 sema_init(&vc4->async_modeset, 1); in vc4_kms_load()
895 dev->vblank_disable_immediate = true; in vc4_kms_load()
897 dev->irq_enabled = true; in vc4_kms_load()
898 ret = drm_vblank_init(dev, dev->mode_config.num_crtc); in vc4_kms_load()
900 dev_err(dev->dev, "failed to initialize vblank\n"); in vc4_kms_load()
905 dev->mode_config.max_width = 7680; in vc4_kms_load()
906 dev->mode_config.max_height = 7680; in vc4_kms_load()
908 dev->mode_config.max_width = 2048; in vc4_kms_load()
909 dev->mode_config.max_height = 2048; in vc4_kms_load()
912 dev->mode_config.funcs = &vc4_mode_funcs; in vc4_kms_load()
913 dev->mode_config.preferred_depth = 24; in vc4_kms_load()
914 dev->mode_config.async_page_flip = true; in vc4_kms_load()
915 dev->mode_config.allow_fb_modifiers = true; in vc4_kms_load()