Lines Matching full:value
486 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl() local
488 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
490 return value; in tegra_sor_readl()
493 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, in tegra_sor_writel() argument
496 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
497 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
544 u32 value; in tegra_clk_sor_pad_set_parent() local
546 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
547 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_clk_sor_pad_set_parent()
551 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; in tegra_clk_sor_pad_set_parent()
555 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; in tegra_clk_sor_pad_set_parent()
559 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
569 u32 value; in tegra_clk_sor_pad_get_parent() local
571 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_get_parent()
573 switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) { in tegra_clk_sor_pad_get_parent()
646 u32 value; in tegra_sor_power_up_lanes() local
652 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_power_up_lanes()
655 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | in tegra_sor_power_up_lanes()
658 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | in tegra_sor_power_up_lanes()
662 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); in tegra_sor_power_up_lanes()
664 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); in tegra_sor_power_up_lanes()
667 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); in tegra_sor_power_up_lanes()
669 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); in tegra_sor_power_up_lanes()
671 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_up_lanes()
674 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | in tegra_sor_power_up_lanes()
676 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_up_lanes()
681 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_power_up_lanes()
682 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_power_up_lanes()
688 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) in tegra_sor_power_up_lanes()
697 u32 value; in tegra_sor_power_down_lanes() local
700 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_power_down_lanes()
701 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | in tegra_sor_power_down_lanes()
703 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_down_lanes()
706 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | in tegra_sor_power_down_lanes()
708 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_down_lanes()
713 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_power_down_lanes()
714 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_power_down_lanes()
720 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) in tegra_sor_power_down_lanes()
728 u32 value; in tegra_sor_dp_precharge() local
731 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
734 value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | in tegra_sor_dp_precharge()
737 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | in tegra_sor_dp_precharge()
741 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); in tegra_sor_dp_precharge()
743 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); in tegra_sor_dp_precharge()
746 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); in tegra_sor_dp_precharge()
748 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); in tegra_sor_dp_precharge()
750 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
754 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
755 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | in tegra_sor_dp_precharge()
757 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
762 u32 mask = 0x08, adj = 0, value; in tegra_sor_dp_term_calibrate() local
765 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
766 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_dp_term_calibrate()
767 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
769 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
770 value |= SOR_PLL1_TMDS_TERM; in tegra_sor_dp_term_calibrate()
771 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
776 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
777 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; in tegra_sor_dp_term_calibrate()
778 value |= SOR_PLL1_TMDS_TERMADJ(adj); in tegra_sor_dp_term_calibrate()
779 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
783 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
784 if (value & SOR_PLL1_TERM_COMPOUT) in tegra_sor_dp_term_calibrate()
790 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
791 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; in tegra_sor_dp_term_calibrate()
792 value |= SOR_PLL1_TMDS_TERMADJ(adj); in tegra_sor_dp_term_calibrate()
793 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
796 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
797 value |= SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_dp_term_calibrate()
798 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
806 u32 pattern = 0, tx_pu = 0, value; in tegra_sor_dp_link_apply_training() local
809 for (value = 0, i = 0; i < link->lanes; i++) { in tegra_sor_dp_link_apply_training()
824 value = SOR_DP_TPG_SCRAMBLER_GALIOS | in tegra_sor_dp_link_apply_training()
829 value = SOR_DP_TPG_SCRAMBLER_NONE | in tegra_sor_dp_link_apply_training()
834 value = SOR_DP_TPG_SCRAMBLER_NONE | in tegra_sor_dp_link_apply_training()
839 value = SOR_DP_TPG_SCRAMBLER_NONE | in tegra_sor_dp_link_apply_training()
848 value |= SOR_DP_TPG_CHANNEL_CODING; in tegra_sor_dp_link_apply_training()
850 pattern = pattern << 8 | value; in tegra_sor_dp_link_apply_training()
861 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_link_apply_training()
862 value &= ~SOR_DP_PADCTL_TX_PU_MASK; in tegra_sor_dp_link_apply_training()
863 value |= SOR_DP_PADCTL_TX_PU_ENABLE; in tegra_sor_dp_link_apply_training()
864 value |= SOR_DP_PADCTL_TX_PU(tx_pu); in tegra_sor_dp_link_apply_training()
865 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_link_apply_training()
876 u32 value; in tegra_sor_dp_link_configure() local
883 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_dp_link_configure()
884 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; in tegra_sor_dp_link_configure()
885 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); in tegra_sor_dp_link_configure()
886 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_dp_link_configure()
888 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_dp_link_configure()
889 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; in tegra_sor_dp_link_configure()
890 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); in tegra_sor_dp_link_configure()
893 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; in tegra_sor_dp_link_configure()
895 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_dp_link_configure()
900 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
901 value &= ~SOR_PLL1_LOADADJ_MASK; in tegra_sor_dp_link_configure()
905 value |= SOR_PLL1_LOADADJ(0x3); in tegra_sor_dp_link_configure()
909 value |= SOR_PLL1_LOADADJ(0x4); in tegra_sor_dp_link_configure()
913 value |= SOR_PLL1_LOADADJ(0x6); in tegra_sor_dp_link_configure()
917 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
920 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_dp_link_configure()
923 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_dp_link_configure()
925 value |= SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_dp_link_configure()
927 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_dp_link_configure()
969 u32 value; in tegra_sor_setup_pwm() local
971 value = tegra_sor_readl(sor, SOR_PWM_DIV); in tegra_sor_setup_pwm()
972 value &= ~SOR_PWM_DIV_MASK; in tegra_sor_setup_pwm()
973 value |= 0x400; /* period */ in tegra_sor_setup_pwm()
974 tegra_sor_writel(sor, value, SOR_PWM_DIV); in tegra_sor_setup_pwm()
976 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
977 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK; in tegra_sor_setup_pwm()
978 value |= 0x400; /* duty cycle */ in tegra_sor_setup_pwm()
979 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ in tegra_sor_setup_pwm()
980 value |= SOR_PWM_CTL_TRIGGER; in tegra_sor_setup_pwm()
981 tegra_sor_writel(sor, value, SOR_PWM_CTL); in tegra_sor_setup_pwm()
986 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
987 if ((value & SOR_PWM_CTL_TRIGGER) == 0) in tegra_sor_setup_pwm()
998 unsigned long value, timeout; in tegra_sor_attach() local
1001 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
1002 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE; in tegra_sor_attach()
1003 value |= SOR_SUPER_STATE_MODE_NORMAL; in tegra_sor_attach()
1004 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
1008 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
1009 value |= SOR_SUPER_STATE_ATTACHED; in tegra_sor_attach()
1010 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
1016 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_attach()
1017 if ((value & SOR_TEST_ATTACHED) != 0) in tegra_sor_attach()
1028 unsigned long value, timeout; in tegra_sor_wakeup() local
1034 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_wakeup()
1035 value &= SOR_TEST_HEAD_MODE_MASK; in tegra_sor_wakeup()
1037 if (value == SOR_TEST_HEAD_MODE_AWAKE) in tegra_sor_wakeup()
1048 u32 value; in tegra_sor_power_up() local
1050 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
1051 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU; in tegra_sor_power_up()
1052 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_up()
1057 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
1058 if ((value & SOR_PWR_TRIGGER) == 0) in tegra_sor_power_up()
1245 u32 value; in tegra_sor_apply_config() local
1247 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_apply_config()
1248 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; in tegra_sor_apply_config()
1249 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size); in tegra_sor_apply_config()
1250 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_apply_config()
1252 value = tegra_sor_readl(sor, SOR_DP_CONFIG0); in tegra_sor_apply_config()
1253 value &= ~SOR_DP_CONFIG_WATERMARK_MASK; in tegra_sor_apply_config()
1254 value |= SOR_DP_CONFIG_WATERMARK(config->watermark); in tegra_sor_apply_config()
1256 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK; in tegra_sor_apply_config()
1257 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count); in tegra_sor_apply_config()
1259 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK; in tegra_sor_apply_config()
1260 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac); in tegra_sor_apply_config()
1263 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; in tegra_sor_apply_config()
1265 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; in tegra_sor_apply_config()
1267 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; in tegra_sor_apply_config()
1268 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; in tegra_sor_apply_config()
1269 tegra_sor_writel(sor, value, SOR_DP_CONFIG0); in tegra_sor_apply_config()
1271 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_apply_config()
1272 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; in tegra_sor_apply_config()
1273 value |= config->hblank_symbols & 0xffff; in tegra_sor_apply_config()
1274 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_apply_config()
1276 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_apply_config()
1277 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK; in tegra_sor_apply_config()
1278 value |= config->vblank_symbols & 0xffff; in tegra_sor_apply_config()
1279 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_apply_config()
1288 u32 value; in tegra_sor_mode_set() local
1290 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_mode_set()
1291 value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK; in tegra_sor_mode_set()
1292 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; in tegra_sor_mode_set()
1293 value &= ~SOR_STATE_ASY_OWNER_MASK; in tegra_sor_mode_set()
1295 value |= SOR_STATE_ASY_CRC_MODE_COMPLETE | in tegra_sor_mode_set()
1299 value &= ~SOR_STATE_ASY_HSYNCPOL; in tegra_sor_mode_set()
1302 value |= SOR_STATE_ASY_HSYNCPOL; in tegra_sor_mode_set()
1305 value &= ~SOR_STATE_ASY_VSYNCPOL; in tegra_sor_mode_set()
1308 value |= SOR_STATE_ASY_VSYNCPOL; in tegra_sor_mode_set()
1312 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444; in tegra_sor_mode_set()
1316 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444; in tegra_sor_mode_set()
1320 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444; in tegra_sor_mode_set()
1324 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; in tegra_sor_mode_set()
1328 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444; in tegra_sor_mode_set()
1332 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; in tegra_sor_mode_set()
1336 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_mode_set()
1343 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); in tegra_sor_mode_set()
1344 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe); in tegra_sor_mode_set()
1350 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); in tegra_sor_mode_set()
1351 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe); in tegra_sor_mode_set()
1357 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); in tegra_sor_mode_set()
1358 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe); in tegra_sor_mode_set()
1364 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); in tegra_sor_mode_set()
1365 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe); in tegra_sor_mode_set()
1373 unsigned long value, timeout; in tegra_sor_detach() local
1376 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1377 value &= ~SOR_SUPER_STATE_MODE_NORMAL; in tegra_sor_detach()
1378 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1384 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_detach()
1385 if (value & SOR_PWR_MODE_SAFE) in tegra_sor_detach()
1389 if ((value & SOR_PWR_MODE_SAFE) == 0) in tegra_sor_detach()
1393 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1394 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK; in tegra_sor_detach()
1395 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1399 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1400 value &= ~SOR_SUPER_STATE_ATTACHED; in tegra_sor_detach()
1401 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1407 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_detach()
1408 if ((value & SOR_TEST_ATTACHED) == 0) in tegra_sor_detach()
1414 if ((value & SOR_TEST_ATTACHED) != 0) in tegra_sor_detach()
1422 unsigned long value, timeout; in tegra_sor_power_down() local
1425 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
1426 value &= ~SOR_PWR_NORMAL_STATE_PU; in tegra_sor_power_down()
1427 value |= SOR_PWR_TRIGGER; in tegra_sor_power_down()
1428 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_down()
1433 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
1434 if ((value & SOR_PWR_TRIGGER) == 0) in tegra_sor_power_down()
1440 if ((value & SOR_PWR_TRIGGER) != 0) in tegra_sor_power_down()
1450 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1451 value |= SOR_PLL2_PORT_POWERDOWN; in tegra_sor_power_down()
1452 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1456 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_power_down()
1457 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; in tegra_sor_power_down()
1458 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_power_down()
1460 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1461 value |= SOR_PLL2_SEQ_PLLCAPPD; in tegra_sor_power_down()
1462 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_power_down()
1463 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1472 u32 value; in tegra_sor_crc_wait() local
1477 value = tegra_sor_readl(sor, SOR_CRCA); in tegra_sor_crc_wait()
1478 if (value & SOR_CRCA_VALID) in tegra_sor_crc_wait()
1494 u32 value; in tegra_sor_show_crc() local
1503 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_show_crc()
1504 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; in tegra_sor_show_crc()
1505 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_show_crc()
1507 value = tegra_sor_readl(sor, SOR_CRC_CNTRL); in tegra_sor_show_crc()
1508 value |= SOR_CRC_CNTRL_ENABLE; in tegra_sor_show_crc()
1509 tegra_sor_writel(sor, value, SOR_CRC_CNTRL); in tegra_sor_show_crc()
1511 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_show_crc()
1512 value &= ~SOR_TEST_CRC_POST_SERIALIZE; in tegra_sor_show_crc()
1513 tegra_sor_writel(sor, value, SOR_TEST); in tegra_sor_show_crc()
1520 value = tegra_sor_readl(sor, SOR_CRCB); in tegra_sor_show_crc()
1522 seq_printf(s, "%08x\n", value); in tegra_sor_show_crc()
1849 u32 value = 0; in tegra_sor_hdmi_subpack() local
1853 value = (value << 8) | ptr[i - 1]; in tegra_sor_hdmi_subpack()
1855 return value; in tegra_sor_hdmi_subpack()
1864 u32 value; in tegra_sor_hdmi_write_infopack() local
1885 value = INFOFRAME_HEADER_TYPE(ptr[0]) | in tegra_sor_hdmi_write_infopack()
1888 tegra_sor_writel(sor, value, offset); in tegra_sor_hdmi_write_infopack()
1899 value = tegra_sor_hdmi_subpack(&ptr[i], num); in tegra_sor_hdmi_write_infopack()
1900 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
1904 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num); in tegra_sor_hdmi_write_infopack()
1905 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
1915 u32 value; in tegra_sor_hdmi_setup_avi_infoframe() local
1919 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1920 value &= ~INFOFRAME_CTRL_SINGLE; in tegra_sor_hdmi_setup_avi_infoframe()
1921 value &= ~INFOFRAME_CTRL_OTHER; in tegra_sor_hdmi_setup_avi_infoframe()
1922 value &= ~INFOFRAME_CTRL_ENABLE; in tegra_sor_hdmi_setup_avi_infoframe()
1923 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1941 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1942 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; in tegra_sor_hdmi_setup_avi_infoframe()
1943 value |= INFOFRAME_CTRL_ENABLE; in tegra_sor_hdmi_setup_avi_infoframe()
1944 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1969 u32 value; in tegra_sor_audio_prepare() local
1976 value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0; in tegra_sor_audio_prepare()
1977 tegra_sor_writel(sor, value, SOR_INT_ENABLE); in tegra_sor_audio_prepare()
1978 tegra_sor_writel(sor, value, SOR_INT_MASK); in tegra_sor_audio_prepare()
1982 value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD; in tegra_sor_audio_prepare()
1983 tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE); in tegra_sor_audio_prepare()
1995 u32 value; in tegra_sor_audio_enable() local
1997 value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL); in tegra_sor_audio_enable()
2000 value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK); in tegra_sor_audio_enable()
2001 value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA); in tegra_sor_audio_enable()
2005 value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL; in tegra_sor_audio_enable()
2007 value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL; in tegra_sor_audio_enable()
2009 value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH; in tegra_sor_audio_enable()
2011 tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL); in tegra_sor_audio_enable()
2021 u32 value; in tegra_sor_hdmi_enable_audio_infoframe() local
2040 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_enable_audio_infoframe()
2041 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; in tegra_sor_hdmi_enable_audio_infoframe()
2042 value |= INFOFRAME_CTRL_ENABLE; in tegra_sor_hdmi_enable_audio_infoframe()
2043 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_enable_audio_infoframe()
2050 u32 value; in tegra_sor_hdmi_audio_enable() local
2056 value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH | in tegra_sor_hdmi_audio_enable()
2059 tegra_sor_writel(sor, value, SOR_HDMI_SPARE); in tegra_sor_hdmi_audio_enable()
2062 value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0); in tegra_sor_hdmi_audio_enable()
2063 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW); in tegra_sor_hdmi_audio_enable()
2066 value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE; in tegra_sor_hdmi_audio_enable()
2067 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH); in tegra_sor_hdmi_audio_enable()
2070 value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP; in tegra_sor_hdmi_audio_enable()
2071 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2073 value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2074 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320); in tegra_sor_hdmi_audio_enable()
2086 value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2087 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480); in tegra_sor_hdmi_audio_enable()
2090 value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2091 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960); in tegra_sor_hdmi_audio_enable()
2094 value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2095 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920); in tegra_sor_hdmi_audio_enable()
2098 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2099 value &= ~SOR_HDMI_AUDIO_N_RESET; in tegra_sor_hdmi_audio_enable()
2100 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2107 u32 value; in tegra_sor_hdmi_disable_audio_infoframe() local
2109 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
2110 value &= ~INFOFRAME_CTRL_ENABLE; in tegra_sor_hdmi_disable_audio_infoframe()
2111 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
2133 u32 value; in tegra_sor_hdmi_disable_scrambling() local
2135 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); in tegra_sor_hdmi_disable_scrambling()
2136 value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4; in tegra_sor_hdmi_disable_scrambling()
2137 value &= ~SOR_HDMI2_CTRL_SCRAMBLE; in tegra_sor_hdmi_disable_scrambling()
2138 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); in tegra_sor_hdmi_disable_scrambling()
2161 u32 value; in tegra_sor_hdmi_enable_scrambling() local
2163 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); in tegra_sor_hdmi_enable_scrambling()
2164 value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4; in tegra_sor_hdmi_enable_scrambling()
2165 value |= SOR_HDMI2_CTRL_SCRAMBLE; in tegra_sor_hdmi_enable_scrambling()
2166 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); in tegra_sor_hdmi_enable_scrambling()
2211 u32 value; in tegra_sor_hdmi_disable() local
2225 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_disable()
2228 value &= ~SOR1_TIMING_CYA; in tegra_sor_hdmi_disable()
2230 value &= ~SOR_ENABLE(sor->index); in tegra_sor_hdmi_disable()
2232 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_disable()
2258 u32 value; in tegra_sor_hdmi_enable() local
2286 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2287 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; in tegra_sor_hdmi_enable()
2288 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2292 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2293 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3; in tegra_sor_hdmi_enable()
2294 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2296 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2297 value &= ~SOR_PLL0_VCOPD; in tegra_sor_hdmi_enable()
2298 value &= ~SOR_PLL0_PWR; in tegra_sor_hdmi_enable()
2299 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2301 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2302 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_hdmi_enable()
2303 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2307 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2308 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; in tegra_sor_hdmi_enable()
2309 value &= ~SOR_PLL2_PORT_POWERDOWN; in tegra_sor_hdmi_enable()
2310 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2314 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2315 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | in tegra_sor_hdmi_enable()
2317 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2320 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2321 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0) in tegra_sor_hdmi_enable()
2327 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | in tegra_sor_hdmi_enable()
2329 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2332 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2333 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_hdmi_enable()
2339 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2340 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; in tegra_sor_hdmi_enable()
2341 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_sor_hdmi_enable()
2345 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70; in tegra_sor_hdmi_enable()
2348 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40; in tegra_sor_hdmi_enable()
2351 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; in tegra_sor_hdmi_enable()
2352 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2357 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_hdmi_enable()
2358 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; in tegra_sor_hdmi_enable()
2359 value |= SOR_DP_LINKCTL_LANE_COUNT(4); in tegra_sor_hdmi_enable()
2360 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_hdmi_enable()
2362 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2363 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; in tegra_sor_hdmi_enable()
2364 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_hdmi_enable()
2365 value &= ~SOR_DP_SPARE_SEQ_ENABLE; in tegra_sor_hdmi_enable()
2366 value &= ~SOR_DP_SPARE_MACRO_SOR_CLK; in tegra_sor_hdmi_enable()
2367 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2369 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) | in tegra_sor_hdmi_enable()
2371 tegra_sor_writel(sor, value, SOR_SEQ_CTL); in tegra_sor_hdmi_enable()
2373 value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT | in tegra_sor_hdmi_enable()
2375 tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); in tegra_sor_hdmi_enable()
2376 tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); in tegra_sor_hdmi_enable()
2380 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div); in tegra_sor_hdmi_enable()
2381 tegra_sor_writel(sor, value, SOR_REFCLK); in tegra_sor_hdmi_enable()
2385 for (value = 0, i = 0; i < 5; i++) in tegra_sor_hdmi_enable()
2386 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | in tegra_sor_hdmi_enable()
2390 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_hdmi_enable()
2434 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe); in tegra_sor_hdmi_enable()
2438 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED; in tegra_sor_hdmi_enable()
2440 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); in tegra_sor_hdmi_enable()
2445 value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) | in tegra_sor_hdmi_enable()
2447 tegra_sor_writel(sor, value, SOR_HDMI_CTRL); in tegra_sor_hdmi_enable()
2455 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE | in tegra_sor_hdmi_enable()
2457 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); in tegra_sor_hdmi_enable()
2459 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start); in tegra_sor_hdmi_enable()
2460 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); in tegra_sor_hdmi_enable()
2462 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_sor_hdmi_enable()
2463 value |= H_PULSE2_ENABLE; in tegra_sor_hdmi_enable()
2464 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_sor_hdmi_enable()
2476 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
2477 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; in tegra_sor_hdmi_enable()
2478 value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A; in tegra_sor_hdmi_enable()
2479 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2482 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2483 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_hdmi_enable()
2484 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2494 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2495 value &= ~SOR_PLL0_ICHPMP_MASK; in tegra_sor_hdmi_enable()
2496 value &= ~SOR_PLL0_FILTER_MASK; in tegra_sor_hdmi_enable()
2497 value &= ~SOR_PLL0_VCOCAP_MASK; in tegra_sor_hdmi_enable()
2498 value |= SOR_PLL0_ICHPMP(settings->ichpmp); in tegra_sor_hdmi_enable()
2499 value |= SOR_PLL0_FILTER(settings->filter); in tegra_sor_hdmi_enable()
2500 value |= SOR_PLL0_VCOCAP(settings->vcocap); in tegra_sor_hdmi_enable()
2501 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2504 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2505 value &= ~SOR_PLL1_LOADADJ_MASK; in tegra_sor_hdmi_enable()
2506 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; in tegra_sor_hdmi_enable()
2507 value |= SOR_PLL1_LOADADJ(settings->loadadj); in tegra_sor_hdmi_enable()
2508 value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj); in tegra_sor_hdmi_enable()
2509 value |= SOR_PLL1_TMDS_TERM; in tegra_sor_hdmi_enable()
2510 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2512 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2513 value &= ~SOR_PLL3_BG_TEMP_COEF_MASK; in tegra_sor_hdmi_enable()
2514 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK; in tegra_sor_hdmi_enable()
2515 value &= ~SOR_PLL3_AVDD10_LEVEL_MASK; in tegra_sor_hdmi_enable()
2516 value &= ~SOR_PLL3_AVDD14_LEVEL_MASK; in tegra_sor_hdmi_enable()
2517 value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef); in tegra_sor_hdmi_enable()
2518 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level); in tegra_sor_hdmi_enable()
2519 value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level); in tegra_sor_hdmi_enable()
2520 value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level); in tegra_sor_hdmi_enable()
2521 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2523 value = settings->drive_current[3] << 24 | in tegra_sor_hdmi_enable()
2527 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_hdmi_enable()
2529 value = settings->preemphasis[3] << 24 | in tegra_sor_hdmi_enable()
2533 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); in tegra_sor_hdmi_enable()
2535 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2536 value &= ~SOR_DP_PADCTL_TX_PU_MASK; in tegra_sor_hdmi_enable()
2537 value |= SOR_DP_PADCTL_TX_PU_ENABLE; in tegra_sor_hdmi_enable()
2538 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value); in tegra_sor_hdmi_enable()
2539 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2541 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2542 value &= ~SOR_DP_PADCTL_SPAREPLL_MASK; in tegra_sor_hdmi_enable()
2543 value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll); in tegra_sor_hdmi_enable()
2544 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2547 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2548 value |= SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_hdmi_enable()
2549 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2553 value = VSYNC_H_POSITION(1); in tegra_sor_hdmi_enable()
2554 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS); in tegra_sor_hdmi_enable()
2557 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL); in tegra_sor_hdmi_enable()
2558 value &= ~DITHER_CONTROL_MASK; in tegra_sor_hdmi_enable()
2559 value &= ~BASE_COLOR_SIZE_MASK; in tegra_sor_hdmi_enable()
2563 value |= BASE_COLOR_SIZE_666; in tegra_sor_hdmi_enable()
2567 value |= BASE_COLOR_SIZE_888; in tegra_sor_hdmi_enable()
2571 value |= BASE_COLOR_SIZE_101010; in tegra_sor_hdmi_enable()
2575 value |= BASE_COLOR_SIZE_121212; in tegra_sor_hdmi_enable()
2580 value |= BASE_COLOR_SIZE_888; in tegra_sor_hdmi_enable()
2584 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL); in tegra_sor_hdmi_enable()
2587 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
2588 value &= ~SOR_STATE_ASY_OWNER_MASK; in tegra_sor_hdmi_enable()
2589 value |= SOR_STATE_ASY_OWNER(1 + dc->pipe); in tegra_sor_hdmi_enable()
2590 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2597 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2598 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK; in tegra_sor_hdmi_enable()
2599 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK; in tegra_sor_hdmi_enable()
2600 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2603 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2604 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK; in tegra_sor_hdmi_enable()
2605 value |= SOR_HEAD_STATE_COLORSPACE_RGB; in tegra_sor_hdmi_enable()
2606 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2613 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2614 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; in tegra_sor_hdmi_enable()
2615 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2622 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_enable()
2625 value |= SOR1_TIMING_CYA; in tegra_sor_hdmi_enable()
2627 value |= SOR_ENABLE(sor->index); in tegra_sor_hdmi_enable()
2629 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_enable()
2632 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2633 value &= ~PROTOCOL_MASK; in tegra_sor_hdmi_enable()
2634 value |= PROTOCOL_SINGLE_TMDS_A; in tegra_sor_hdmi_enable()
2635 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2659 u32 value; in tegra_sor_dp_disable() local
2683 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_dp_disable()
2684 value &= ~SOR_ENABLE(sor->index); in tegra_sor_dp_disable()
2685 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_dp_disable()
2688 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_dp_disable()
2689 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; in tegra_sor_dp_disable()
2690 value &= ~SOR_STATE_ASY_SUBOWNER_MASK; in tegra_sor_dp_disable()
2691 value &= ~SOR_STATE_ASY_OWNER_MASK; in tegra_sor_dp_disable()
2692 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_dp_disable()
2728 u32 value; in tegra_sor_dp_enable() local
2769 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2770 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; in tegra_sor_dp_enable()
2771 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2775 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_dp_enable()
2776 value |= SOR_PLL3_PLL_VDD_MODE_3V3; in tegra_sor_dp_enable()
2777 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_dp_enable()
2779 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2780 value &= ~(SOR_PLL0_VCOPD | SOR_PLL0_PWR); in tegra_sor_dp_enable()
2781 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2783 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2784 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_dp_enable()
2785 value |= SOR_PLL2_SEQ_PLLCAPPD; in tegra_sor_dp_enable()
2786 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2790 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2791 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; in tegra_sor_dp_enable()
2792 value &= ~SOR_PLL2_PORT_POWERDOWN; in tegra_sor_dp_enable()
2793 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2795 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_dp_enable()
2796 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_sor_dp_enable()
2799 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; in tegra_sor_dp_enable()
2801 value |= SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK; in tegra_sor_dp_enable()
2803 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_dp_enable()
2807 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_dp_enable()
2810 value |= SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_dp_enable()
2812 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_dp_enable()
2814 value |= SOR_DP_SPARE_SEQ_ENABLE; in tegra_sor_dp_enable()
2815 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_dp_enable()
2820 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2821 value &= ~SOR_PLL0_ICHPMP_MASK; in tegra_sor_dp_enable()
2822 value &= ~SOR_PLL0_VCOCAP_MASK; in tegra_sor_dp_enable()
2823 value |= SOR_PLL0_ICHPMP(0x1); in tegra_sor_dp_enable()
2824 value |= SOR_PLL0_VCOCAP(0x3); in tegra_sor_dp_enable()
2825 value |= SOR_PLL0_RESISTOR_EXT; in tegra_sor_dp_enable()
2826 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2829 for (value = 0, i = 0; i < 5; i++) in tegra_sor_dp_enable()
2830 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | in tegra_sor_dp_enable()
2834 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_dp_enable()
2868 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_dp_enable()
2869 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; in tegra_sor_dp_enable()
2870 value |= SOR_STATE_ASY_PROTOCOL_DP_A; in tegra_sor_dp_enable()
2871 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_dp_enable()
2874 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_dp_enable()
2875 value |= SOR_DP_LINKCTL_ENABLE; in tegra_sor_dp_enable()
2876 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_dp_enable()
2903 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | in tegra_sor_dp_enable()
2905 tegra_sor_writel(sor, value, SOR_CSTM); in tegra_sor_dp_enable()
2924 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_dp_enable()
2925 value |= SOR_ENABLE(sor->index); in tegra_sor_dp_enable()
2926 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_dp_enable()
3639 u32 value; in tegra_sor_parse_dt() local
3643 err = of_property_read_u32(np, "nvidia,interface", &value); in tegra_sor_parse_dt()
3647 sor->index = value; in tegra_sor_parse_dt()
3678 u32 value; in tegra_sor_irq() local
3680 value = tegra_sor_readl(sor, SOR_INT_STATUS); in tegra_sor_irq()
3681 tegra_sor_writel(sor, value, SOR_INT_STATUS); in tegra_sor_irq()
3683 if (value & SOR_INT_CODEC_SCRATCH0) { in tegra_sor_irq()
3684 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0); in tegra_sor_irq()
3686 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) { in tegra_sor_irq()
3689 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK; in tegra_sor_irq()