1 // SPDX-License-Identifier: GPL-2.0-only
93 	tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));  in tegra_rgb_encoder_disable()
94 	tegra_dc_commit(rgb->dc);  in tegra_rgb_encoder_disable()
103 	tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable));  in tegra_rgb_encoder_enable()
106 	tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS);  in tegra_rgb_encoder_enable()
109 	value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1));  in tegra_rgb_encoder_enable()
112 	tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));  in tegra_rgb_encoder_enable()
117 	tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL);  in tegra_rgb_encoder_enable()
121 	tegra_dc_writel(rgb->dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);  in tegra_rgb_encoder_enable()
123 	tegra_dc_commit(rgb->dc);  in tegra_rgb_encoder_enable()
132 	struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);  in tegra_rgb_encoder_atomic_check()
133 	unsigned long pclk = crtc_state->mode.clock * 1000;  in tegra_rgb_encoder_atomic_check()
152 	 * matched sufficiently close that the panel will still work).  in tegra_rgb_encoder_atomic_check()
154 	div = ((clk_get_rate(rgb->clk) * 2) / pclk) - 2;  in tegra_rgb_encoder_atomic_check()
157 	err = tegra_dc_state_setup_clock(dc, crtc_state, rgb->clk_parent,  in tegra_rgb_encoder_atomic_check()
160 		dev_err(output->dev, "failed to setup CRTC state: %d\n", err);  in tegra_rgb_encoder_atomic_check()
179 	np = of_get_child_by_name(dc->dev->of_node, "rgb");  in tegra_dc_rgb_probe()
181 		return -ENODEV;  in tegra_dc_rgb_probe()
183 	rgb = devm_kzalloc(dc->dev, sizeof(*rgb), GFP_KERNEL);  in tegra_dc_rgb_probe()
185 		return -ENOMEM;  in tegra_dc_rgb_probe()
187 	rgb->output.dev = dc->dev;  in tegra_dc_rgb_probe()
188 	rgb->output.of_node = np;  in tegra_dc_rgb_probe()
189 	rgb->dc = dc;  in tegra_dc_rgb_probe()
191 	err = tegra_output_probe(&rgb->output);  in tegra_dc_rgb_probe()
195 	rgb->clk = devm_clk_get(dc->dev, NULL);  in tegra_dc_rgb_probe()
196 	if (IS_ERR(rgb->clk)) {  in tegra_dc_rgb_probe()
197 		dev_err(dc->dev, "failed to get clock\n");  in tegra_dc_rgb_probe()
198 		return PTR_ERR(rgb->clk);  in tegra_dc_rgb_probe()
201 	rgb->clk_parent = devm_clk_get(dc->dev, "parent");  in tegra_dc_rgb_probe()
202 	if (IS_ERR(rgb->clk_parent)) {  in tegra_dc_rgb_probe()
203 		dev_err(dc->dev, "failed to get parent clock\n");  in tegra_dc_rgb_probe()
204 		return PTR_ERR(rgb->clk_parent);  in tegra_dc_rgb_probe()
207 	err = clk_set_parent(rgb->clk, rgb->clk_parent);  in tegra_dc_rgb_probe()
209 		dev_err(dc->dev, "failed to set parent clock: %d\n", err);  in tegra_dc_rgb_probe()
213 	dc->rgb = &rgb->output;  in tegra_dc_rgb_probe()
220 	if (!dc->rgb)  in tegra_dc_rgb_remove()
223 	tegra_output_remove(dc->rgb);  in tegra_dc_rgb_remove()
224 	dc->rgb = NULL;  in tegra_dc_rgb_remove()
231 	struct tegra_output *output = dc->rgb;  in tegra_dc_rgb_init()
235 	if (!dc->rgb)  in tegra_dc_rgb_init()
236 		return -ENODEV;  in tegra_dc_rgb_init()
238 	drm_simple_encoder_init(drm, &output->encoder, DRM_MODE_ENCODER_LVDS);  in tegra_dc_rgb_init()
239 	drm_encoder_helper_add(&output->encoder,  in tegra_dc_rgb_init()
243 	 * Wrap directly-connected panel into DRM bridge in order to let  in tegra_dc_rgb_init()
244 	 * DRM core to handle panel for us.  in tegra_dc_rgb_init()
246 	if (output->panel) {  in tegra_dc_rgb_init()
247 		output->bridge = devm_drm_panel_bridge_add(output->dev,  in tegra_dc_rgb_init()
248 							   output->panel);  in tegra_dc_rgb_init()
249 		if (IS_ERR(output->bridge)) {  in tegra_dc_rgb_init()
250 			dev_err(output->dev,  in tegra_dc_rgb_init()
251 				"failed to wrap panel into bridge: %pe\n",  in tegra_dc_rgb_init()
252 				output->bridge);  in tegra_dc_rgb_init()
253 			return PTR_ERR(output->bridge);  in tegra_dc_rgb_init()
256 		output->panel = NULL;  in tegra_dc_rgb_init()
260 	 * Tegra devices that have LVDS panel utilize LVDS encoder bridge  in tegra_dc_rgb_init()
261 	 * for converting up to 28 LCD LVTTL lanes into 5/4 LVDS lanes that  in tegra_dc_rgb_init()
262 	 * go to display panel's receiver.  in tegra_dc_rgb_init()
264 	 * Encoder usually have a power-down control which needs to be enabled  in tegra_dc_rgb_init()
265 	 * in order to transmit data to the panel.  Historically devices that  in tegra_dc_rgb_init()
266 	 * use an older device-tree version didn't model the bridge, assuming  in tegra_dc_rgb_init()
268 	 * to model LVDS encoder properly.  in tegra_dc_rgb_init()
270 	 * Newer device-trees utilize LVDS encoder bridge, which provides  in tegra_dc_rgb_init()
271 	 * us with a connector and handles the display panel.  in tegra_dc_rgb_init()
273 	 * For older device-trees we wrapped panel into the panel-bridge.  in tegra_dc_rgb_init()
275 	if (output->bridge) {  in tegra_dc_rgb_init()
276 		err = drm_bridge_attach(&output->encoder, output->bridge,  in tegra_dc_rgb_init()
279 			dev_err(output->dev, "failed to attach bridge: %d\n",  in tegra_dc_rgb_init()
284 		connector = drm_bridge_connector_init(drm, &output->encoder);  in tegra_dc_rgb_init()
286 			dev_err(output->dev,  in tegra_dc_rgb_init()
292 		drm_connector_attach_encoder(connector, &output->encoder);  in tegra_dc_rgb_init()
297 		dev_err(output->dev, "failed to initialize output: %d\n", err);  in tegra_dc_rgb_init()
306 	output->encoder.possible_crtcs = drm_crtc_mask(&dc->base);  in tegra_dc_rgb_init()
313 	if (dc->rgb)  in tegra_dc_rgb_exit()
314 		tegra_output_exit(dc->rgb);  in tegra_dc_rgb_exit()