Lines Matching +full:clock +full:- +full:indices
1 /* savage_state.c -- State and drawing support for Savage
20 * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
39 uint32_t scstart = dev_priv->state.s3d.new_scstart; in savage_emit_clip_rect_s3d()
40 uint32_t scend = dev_priv->state.s3d.new_scend; in savage_emit_clip_rect_s3d()
42 ((uint32_t) pbox->x1 & 0x000007ff) | in savage_emit_clip_rect_s3d()
43 (((uint32_t) pbox->y1 << 16) & 0x07ff0000); in savage_emit_clip_rect_s3d()
45 (((uint32_t) pbox->x2 - 1) & 0x000007ff) | in savage_emit_clip_rect_s3d()
46 ((((uint32_t) pbox->y2 - 1) << 16) & 0x07ff0000); in savage_emit_clip_rect_s3d()
47 if (scstart != dev_priv->state.s3d.scstart || in savage_emit_clip_rect_s3d()
48 scend != dev_priv->state.s3d.scend) { in savage_emit_clip_rect_s3d()
55 dev_priv->state.s3d.scstart = scstart; in savage_emit_clip_rect_s3d()
56 dev_priv->state.s3d.scend = scend; in savage_emit_clip_rect_s3d()
57 dev_priv->waiting = 1; in savage_emit_clip_rect_s3d()
65 uint32_t drawctrl0 = dev_priv->state.s4.new_drawctrl0; in savage_emit_clip_rect_s4()
66 uint32_t drawctrl1 = dev_priv->state.s4.new_drawctrl1; in savage_emit_clip_rect_s4()
68 ((uint32_t) pbox->x1 & 0x000007ff) | in savage_emit_clip_rect_s4()
69 (((uint32_t) pbox->y1 << 12) & 0x00fff000); in savage_emit_clip_rect_s4()
71 (((uint32_t) pbox->x2 - 1) & 0x000007ff) | in savage_emit_clip_rect_s4()
72 ((((uint32_t) pbox->y2 - 1) << 12) & 0x00fff000); in savage_emit_clip_rect_s4()
73 if (drawctrl0 != dev_priv->state.s4.drawctrl0 || in savage_emit_clip_rect_s4()
74 drawctrl1 != dev_priv->state.s4.drawctrl1) { in savage_emit_clip_rect_s4()
81 dev_priv->state.s4.drawctrl0 = drawctrl0; in savage_emit_clip_rect_s4()
82 dev_priv->state.s4.drawctrl1 = drawctrl1; in savage_emit_clip_rect_s4()
83 dev_priv->waiting = 1; in savage_emit_clip_rect_s4()
93 return -EINVAL; in savage_verify_texaddr()
97 if (addr < dev_priv->texture_offset || in savage_verify_texaddr()
98 addr >= dev_priv->texture_offset + dev_priv->texture_size) { in savage_verify_texaddr()
102 return -EINVAL; in savage_verify_texaddr()
105 if (!dev_priv->agp_textures) { in savage_verify_texaddr()
108 return -EINVAL; in savage_verify_texaddr()
111 if (addr < dev_priv->agp_textures->offset || in savage_verify_texaddr()
112 addr >= (dev_priv->agp_textures->offset + in savage_verify_texaddr()
113 dev_priv->agp_textures->size)) { in savage_verify_texaddr()
117 return -EINVAL; in savage_verify_texaddr()
125 dev_priv->state.where = regs[reg - start]
129 tmp = regs[reg - start]; \
130 dev_priv->state.where = (tmp & (mask)) | \
131 (dev_priv->state.where & ~(mask)); \
140 start + count - 1 > SAVAGE_DESTTEXRWWATERMARK_S3D) { in savage_verify_state_s3d()
141 DRM_ERROR("invalid register range (0x%04x-0x%04x)\n", in savage_verify_state_s3d()
142 start, start + count - 1); in savage_verify_state_s3d()
143 return -EINVAL; in savage_verify_state_s3d()
157 if (dev_priv->state.s3d.texctrl & SAVAGE_TEXCTRL_TEXEN_MASK) in savage_verify_state_s3d()
159 dev_priv->state.s3d.texaddr); in savage_verify_state_s3d()
172 start + count - 1 > SAVAGE_TEXBLENDCOLOR_S4) { in savage_verify_state_s4()
173 DRM_ERROR("invalid register range (0x%04x-0x%04x)\n", in savage_verify_state_s4()
174 start, start + count - 1); in savage_verify_state_s4()
175 return -EINVAL; in savage_verify_state_s4()
190 if (dev_priv->state.s4.texdescr & SAVAGE_TEXDESCR_TEX0EN_MASK) in savage_verify_state_s4()
192 dev_priv->state.s4.texaddr0); in savage_verify_state_s4()
193 if (dev_priv->state.s4.texdescr & SAVAGE_TEXDESCR_TEX1EN_MASK) in savage_verify_state_s4()
195 dev_priv->state.s4.texaddr1); in savage_verify_state_s4()
208 unsigned int count = cmd_header->state.count; in savage_dispatch_state()
209 unsigned int start = cmd_header->state.start; in savage_dispatch_state()
218 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { in savage_dispatch_state()
225 count2 = count - (SAVAGE_SCEND_S3D + 1 - start); in savage_dispatch_state()
227 count = SAVAGE_SCSTART_S3D - start; in savage_dispatch_state()
230 count -= SAVAGE_SCEND_S3D + 1 - start; in savage_dispatch_state()
242 count2 = count - in savage_dispatch_state()
243 (SAVAGE_DRAWCTRL1_S4 + 1 - start); in savage_dispatch_state()
245 count = SAVAGE_DRAWCTRL0_S4 - start; in savage_dispatch_state()
248 count -= SAVAGE_DRAWCTRL1_S4 + 1 - start; in savage_dispatch_state()
257 if (cmd_header->state.global) { in savage_dispatch_state()
260 dev_priv->waiting = 1; in savage_dispatch_state()
270 count -= n; in savage_dispatch_state()
290 unsigned int prim = cmd_header->prim.prim; in savage_dispatch_dma_prim()
291 unsigned int skip = cmd_header->prim.skip; in savage_dispatch_dma_prim()
292 unsigned int n = cmd_header->prim.count; in savage_dispatch_dma_prim()
293 unsigned int start = cmd_header->prim.start; in savage_dispatch_dma_prim()
299 return -EINVAL; in savage_dispatch_dma_prim()
314 return -EINVAL; in savage_dispatch_dma_prim()
323 return -EINVAL; in savage_dispatch_dma_prim()
328 return -EINVAL; in savage_dispatch_dma_prim()
331 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { in savage_dispatch_dma_prim()
334 return -EINVAL; in savage_dispatch_dma_prim()
337 unsigned int size = 10 - (skip & 1) - (skip >> 1 & 1) - in savage_dispatch_dma_prim()
338 (skip >> 2 & 1) - (skip >> 3 & 1) - (skip >> 4 & 1) - in savage_dispatch_dma_prim()
339 (skip >> 5 & 1) - (skip >> 6 & 1) - (skip >> 7 & 1); in savage_dispatch_dma_prim()
342 return -EINVAL; in savage_dispatch_dma_prim()
346 return -EINVAL; in savage_dispatch_dma_prim()
350 if (start + n > dmabuf->total / 32) { in savage_dispatch_dma_prim()
351 DRM_ERROR("vertex indices (%u-%u) out of range (0-%u)\n", in savage_dispatch_dma_prim()
352 start, start + n - 1, dmabuf->total / 32); in savage_dispatch_dma_prim()
353 return -EINVAL; in savage_dispatch_dma_prim()
361 if (dmabuf->bus_address != dev_priv->state.common.vbaddr) { in savage_dispatch_dma_prim()
364 BCI_WRITE(dmabuf->bus_address | dev_priv->dma_type); in savage_dispatch_dma_prim()
365 dev_priv->state.common.vbaddr = dmabuf->bus_address; in savage_dispatch_dma_prim()
367 if (S3_SAVAGE3D_SERIES(dev_priv->chipset) && dev_priv->waiting) { in savage_dispatch_dma_prim()
376 dev_priv->waiting = 0; in savage_dispatch_dma_prim()
381 /* Can emit up to 255 indices (85 triangles) at once. */ in savage_dispatch_dma_prim()
384 /* Need to reorder indices for correct flat in savage_dispatch_dma_prim()
385 * shading while preserving the clock sense in savage_dispatch_dma_prim()
387 int reorder[3] = { -1, -1, -1 }; in savage_dispatch_dma_prim()
399 } else if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { in savage_dispatch_dma_prim()
418 n -= count; in savage_dispatch_dma_prim()
432 unsigned int prim = cmd_header->prim.prim; in savage_dispatch_vb_prim()
433 unsigned int skip = cmd_header->prim.skip; in savage_dispatch_vb_prim()
434 unsigned int n = cmd_header->prim.count; in savage_dispatch_vb_prim()
435 unsigned int start = cmd_header->prim.start; in savage_dispatch_vb_prim()
452 return -EINVAL; in savage_dispatch_vb_prim()
461 return -EINVAL; in savage_dispatch_vb_prim()
466 return -EINVAL; in savage_dispatch_vb_prim()
469 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { in savage_dispatch_vb_prim()
472 return -EINVAL; in savage_dispatch_vb_prim()
478 return -EINVAL; in savage_dispatch_vb_prim()
483 vtx_size -= (skip & 1) + (skip >> 1 & 1) + in savage_dispatch_vb_prim()
490 return -EINVAL; in savage_dispatch_vb_prim()
494 DRM_ERROR("vertex indices (%u-%u) out of range (0-%u)\n", in savage_dispatch_vb_prim()
495 start, start + n - 1, vb_size / (vb_stride * 4)); in savage_dispatch_vb_prim()
496 return -EINVAL; in savage_dispatch_vb_prim()
505 * shading while preserving the clock sense in savage_dispatch_vb_prim()
507 int reorder[3] = { -1, -1, -1 }; in savage_dispatch_vb_prim()
537 n -= count; in savage_dispatch_vb_prim()
551 unsigned int prim = cmd_header->idx.prim; in savage_dispatch_dma_idx()
552 unsigned int skip = cmd_header->idx.skip; in savage_dispatch_dma_idx()
553 unsigned int n = cmd_header->idx.count; in savage_dispatch_dma_idx()
559 return -EINVAL; in savage_dispatch_dma_idx()
572 DRM_ERROR("wrong number of indices %u in TRILIST\n", n); in savage_dispatch_dma_idx()
573 return -EINVAL; in savage_dispatch_dma_idx()
580 ("wrong number of indices %u in TRIFAN/STRIP\n", n); in savage_dispatch_dma_idx()
581 return -EINVAL; in savage_dispatch_dma_idx()
586 return -EINVAL; in savage_dispatch_dma_idx()
589 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { in savage_dispatch_dma_idx()
592 return -EINVAL; in savage_dispatch_dma_idx()
595 unsigned int size = 10 - (skip & 1) - (skip >> 1 & 1) - in savage_dispatch_dma_idx()
596 (skip >> 2 & 1) - (skip >> 3 & 1) - (skip >> 4 & 1) - in savage_dispatch_dma_idx()
597 (skip >> 5 & 1) - (skip >> 6 & 1) - (skip >> 7 & 1); in savage_dispatch_dma_idx()
600 return -EINVAL; in savage_dispatch_dma_idx()
604 return -EINVAL; in savage_dispatch_dma_idx()
613 if (dmabuf->bus_address != dev_priv->state.common.vbaddr) { in savage_dispatch_dma_idx()
616 BCI_WRITE(dmabuf->bus_address | dev_priv->dma_type); in savage_dispatch_dma_idx()
617 dev_priv->state.common.vbaddr = dmabuf->bus_address; in savage_dispatch_dma_idx()
619 if (S3_SAVAGE3D_SERIES(dev_priv->chipset) && dev_priv->waiting) { in savage_dispatch_dma_idx()
628 dev_priv->waiting = 0; in savage_dispatch_dma_idx()
633 /* Can emit up to 255 indices (85 triangles) at once. */ in savage_dispatch_dma_idx()
636 /* check indices */ in savage_dispatch_dma_idx()
638 if (idx[i] > dmabuf->total / 32) { in savage_dispatch_dma_idx()
639 DRM_ERROR("idx[%u]=%u out of range (0-%u)\n", in savage_dispatch_dma_idx()
640 i, idx[i], dmabuf->total / 32); in savage_dispatch_dma_idx()
641 return -EINVAL; in savage_dispatch_dma_idx()
646 /* Need to reorder indices for correct flat in savage_dispatch_dma_idx()
647 * shading while preserving the clock sense in savage_dispatch_dma_idx()
649 int reorder[3] = { 2, -1, -1 }; in savage_dispatch_dma_idx()
660 } else if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { in savage_dispatch_dma_idx()
679 n -= count; in savage_dispatch_dma_idx()
694 unsigned int prim = cmd_header->idx.prim; in savage_dispatch_vb_idx()
695 unsigned int skip = cmd_header->idx.skip; in savage_dispatch_vb_idx()
696 unsigned int n = cmd_header->idx.count; in savage_dispatch_vb_idx()
711 DRM_ERROR("wrong number of indices %u in TRILIST\n", n); in savage_dispatch_vb_idx()
712 return -EINVAL; in savage_dispatch_vb_idx()
719 ("wrong number of indices %u in TRIFAN/STRIP\n", n); in savage_dispatch_vb_idx()
720 return -EINVAL; in savage_dispatch_vb_idx()
725 return -EINVAL; in savage_dispatch_vb_idx()
728 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { in savage_dispatch_vb_idx()
731 return -EINVAL; in savage_dispatch_vb_idx()
737 return -EINVAL; in savage_dispatch_vb_idx()
742 vtx_size -= (skip & 1) + (skip >> 1 & 1) + in savage_dispatch_vb_idx()
749 return -EINVAL; in savage_dispatch_vb_idx()
757 /* Check indices */ in savage_dispatch_vb_idx()
760 DRM_ERROR("idx[%u]=%u out of range (0-%u)\n", in savage_dispatch_vb_idx()
762 return -EINVAL; in savage_dispatch_vb_idx()
768 * shading while preserving the clock sense in savage_dispatch_vb_idx()
770 int reorder[3] = { 2, -1, -1 }; in savage_dispatch_vb_idx()
794 n -= count; in savage_dispatch_vb_idx()
808 unsigned int flags = cmd_header->clear0.flags; in savage_dispatch_clear()
825 if (data->clear1.mask != 0xffffffff) { in savage_dispatch_clear()
829 DMA_WRITE(data->clear1.mask); in savage_dispatch_clear()
836 w = boxes[i].x2 - boxes[i].x1; in savage_dispatch_clear()
837 h = boxes[i].y2 - boxes[i].y1; in savage_dispatch_clear()
845 DMA_WRITE(dev_priv->front_offset); in savage_dispatch_clear()
846 DMA_WRITE(dev_priv->front_bd); in savage_dispatch_clear()
849 DMA_WRITE(dev_priv->back_offset); in savage_dispatch_clear()
850 DMA_WRITE(dev_priv->back_bd); in savage_dispatch_clear()
853 DMA_WRITE(dev_priv->depth_offset); in savage_dispatch_clear()
854 DMA_WRITE(dev_priv->depth_bd); in savage_dispatch_clear()
857 DMA_WRITE(data->clear1.value); in savage_dispatch_clear()
863 if (data->clear1.mask != 0xffffffff) { in savage_dispatch_clear()
891 DMA_WRITE(dev_priv->back_offset); in savage_dispatch_swap()
892 DMA_WRITE(dev_priv->back_bd); in savage_dispatch_swap()
895 DMA_WRITE(BCI_W_H(boxes[i].x2 - boxes[i].x1, in savage_dispatch_swap()
896 boxes[i].y2 - boxes[i].y1)); in savage_dispatch_swap()
917 dev_priv->emit_clip_rect(dev_priv, &boxes[i]); in savage_dispatch_draw()
954 "non-drawing-command %d\n", in savage_dispatch_draw()
956 return -EINVAL; in savage_dispatch_draw()
969 drm_savage_private_t *dev_priv = dev->dev_private; in savage_bci_cmdbuf()
970 struct drm_device_dma *dma = dev->dma; in savage_bci_cmdbuf()
984 if (dma && dma->buflist) { in savage_bci_cmdbuf()
985 if (cmdbuf->dma_idx >= dma->buf_count) { in savage_bci_cmdbuf()
987 ("vertex buffer index %u out of range (0-%u)\n", in savage_bci_cmdbuf()
988 cmdbuf->dma_idx, dma->buf_count - 1); in savage_bci_cmdbuf()
989 return -EINVAL; in savage_bci_cmdbuf()
991 dmabuf = dma->buflist[cmdbuf->dma_idx]; in savage_bci_cmdbuf()
1001 if (cmdbuf->size) { in savage_bci_cmdbuf()
1002 kcmd_addr = kmalloc_array(cmdbuf->size, 8, GFP_KERNEL); in savage_bci_cmdbuf()
1004 return -ENOMEM; in savage_bci_cmdbuf()
1006 if (copy_from_user(kcmd_addr, cmdbuf->cmd_addr, in savage_bci_cmdbuf()
1007 cmdbuf->size * 8)) in savage_bci_cmdbuf()
1010 return -EFAULT; in savage_bci_cmdbuf()
1012 cmdbuf->cmd_addr = kcmd_addr; in savage_bci_cmdbuf()
1014 if (cmdbuf->vb_size) { in savage_bci_cmdbuf()
1015 kvb_addr = memdup_user(cmdbuf->vb_addr, cmdbuf->vb_size); in savage_bci_cmdbuf()
1021 cmdbuf->vb_addr = kvb_addr; in savage_bci_cmdbuf()
1023 if (cmdbuf->nbox) { in savage_bci_cmdbuf()
1024 kbox_addr = kmalloc_array(cmdbuf->nbox, sizeof(struct drm_clip_rect), in savage_bci_cmdbuf()
1027 ret = -ENOMEM; in savage_bci_cmdbuf()
1031 if (copy_from_user(kbox_addr, cmdbuf->box_addr, in savage_bci_cmdbuf()
1032 cmdbuf->nbox * sizeof(struct drm_clip_rect))) { in savage_bci_cmdbuf()
1033 ret = -EFAULT; in savage_bci_cmdbuf()
1036 cmdbuf->box_addr = kbox_addr; in savage_bci_cmdbuf()
1045 dev_priv->waiting = 1; in savage_bci_cmdbuf()
1049 while (i < cmdbuf->size) { in savage_bci_cmdbuf()
1051 cmd_header = *(drm_savage_cmd_header_t *)cmdbuf->cmd_addr; in savage_bci_cmdbuf()
1052 cmdbuf->cmd_addr++; in savage_bci_cmdbuf()
1062 if (i + j > cmdbuf->size) { in savage_bci_cmdbuf()
1066 ret = -EINVAL; in savage_bci_cmdbuf()
1073 first_draw_cmd = cmdbuf->cmd_addr - 1; in savage_bci_cmdbuf()
1074 cmdbuf->cmd_addr += j; in savage_bci_cmdbuf()
1081 cmdbuf->cmd_addr - 1, in savage_bci_cmdbuf()
1082 dmabuf, cmdbuf->vb_addr, cmdbuf->vb_size, in savage_bci_cmdbuf()
1083 cmdbuf->vb_stride, in savage_bci_cmdbuf()
1084 cmdbuf->nbox, cmdbuf->box_addr); in savage_bci_cmdbuf()
1096 if (i + j > cmdbuf->size) { in savage_bci_cmdbuf()
1100 ret = -EINVAL; in savage_bci_cmdbuf()
1104 (const uint32_t *)cmdbuf->cmd_addr); in savage_bci_cmdbuf()
1105 cmdbuf->cmd_addr += j; in savage_bci_cmdbuf()
1109 if (i + 1 > cmdbuf->size) { in savage_bci_cmdbuf()
1113 ret = -EINVAL; in savage_bci_cmdbuf()
1117 cmdbuf->cmd_addr, in savage_bci_cmdbuf()
1118 cmdbuf->nbox, in savage_bci_cmdbuf()
1119 cmdbuf->box_addr); in savage_bci_cmdbuf()
1120 cmdbuf->cmd_addr++; in savage_bci_cmdbuf()
1124 ret = savage_dispatch_swap(dev_priv, cmdbuf->nbox, in savage_bci_cmdbuf()
1125 cmdbuf->box_addr); in savage_bci_cmdbuf()
1131 ret = -EINVAL; in savage_bci_cmdbuf()
1143 dev_priv, first_draw_cmd, cmdbuf->cmd_addr, dmabuf, in savage_bci_cmdbuf()
1144 cmdbuf->vb_addr, cmdbuf->vb_size, cmdbuf->vb_stride, in savage_bci_cmdbuf()
1145 cmdbuf->nbox, cmdbuf->box_addr); in savage_bci_cmdbuf()
1154 if (dmabuf && cmdbuf->discard) { in savage_bci_cmdbuf()
1155 drm_savage_buf_priv_t *buf_priv = dmabuf->dev_private; in savage_bci_cmdbuf()
1158 SET_AGE(&buf_priv->age, event, dev_priv->event_wrap); in savage_bci_cmdbuf()