Lines Matching +full:no +full:- +full:hpd
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
39 #include <linux/io-64-nonatomic-lo-hi.h>
58 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
83 * avivo_wait_for_vblank - vblank wait asic callback.
88 * Wait for vblank on the requested crtc (r5xx-r7xx).
94 if (crtc >= rdev->num_crtc) in avivo_wait_for_vblank()
120 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rs600_page_flip()
121 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rs600_page_flip()
126 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip()
129 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, in rs600_page_flip()
131 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rs600_page_flip()
133 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rs600_page_flip()
137 for (i = 0; i < rdev->usec_timeout; i++) { in rs600_page_flip()
138 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rs600_page_flip()
144 /* Unlock the lock, so double-buffering can take place inside vblank */ in rs600_page_flip()
146 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip()
151 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rs600_page_flip_pending()
154 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & in rs600_page_flip_pending()
160 struct drm_device *dev = encoder->dev; in avivo_program_fmt()
161 struct radeon_device *rdev = dev->dev_private; in avivo_program_fmt()
171 dither = radeon_connector->dither; in avivo_program_fmt()
175 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) in avivo_program_fmt()
204 switch (radeon_encoder->encoder_id) { in avivo_program_fmt()
224 int requested_index = rdev->pm.requested_power_state_index; in rs600_pm_misc()
225 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; in rs600_pm_misc()
226 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; in rs600_pm_misc()
230 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { in rs600_pm_misc()
231 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { in rs600_pm_misc()
232 tmp = RREG32(voltage->gpio.reg); in rs600_pm_misc()
233 if (voltage->active_high) in rs600_pm_misc()
234 tmp |= voltage->gpio.mask; in rs600_pm_misc()
236 tmp &= ~(voltage->gpio.mask); in rs600_pm_misc()
237 WREG32(voltage->gpio.reg, tmp); in rs600_pm_misc()
238 if (voltage->delay) in rs600_pm_misc()
239 udelay(voltage->delay); in rs600_pm_misc()
241 tmp = RREG32(voltage->gpio.reg); in rs600_pm_misc()
242 if (voltage->active_high) in rs600_pm_misc()
243 tmp &= ~voltage->gpio.mask; in rs600_pm_misc()
245 tmp |= voltage->gpio.mask; in rs600_pm_misc()
246 WREG32(voltage->gpio.reg, tmp); in rs600_pm_misc()
247 if (voltage->delay) in rs600_pm_misc()
248 udelay(voltage->delay); in rs600_pm_misc()
250 } else if (voltage->type == VOLTAGE_VDDC) in rs600_pm_misc()
251 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC); in rs600_pm_misc()
256 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { in rs600_pm_misc()
257 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) { in rs600_pm_misc()
260 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) { in rs600_pm_misc()
271 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { in rs600_pm_misc()
273 if (voltage->delay) { in rs600_pm_misc()
275 dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay); in rs600_pm_misc()
283 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) in rs600_pm_misc()
291 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN) in rs600_pm_misc()
298 if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN) in rs600_pm_misc()
305 if ((rdev->flags & RADEON_IS_PCIE) && in rs600_pm_misc()
306 !(rdev->flags & RADEON_IS_IGP) && in rs600_pm_misc()
307 rdev->asic->pm.set_pcie_lanes && in rs600_pm_misc()
308 (ps->pcie_lanes != in rs600_pm_misc()
309 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { in rs600_pm_misc()
311 ps->pcie_lanes); in rs600_pm_misc()
312 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes); in rs600_pm_misc()
318 struct drm_device *ddev = rdev->ddev; in rs600_pm_prepare()
324 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { in rs600_pm_prepare()
326 if (radeon_crtc->enabled) { in rs600_pm_prepare()
327 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); in rs600_pm_prepare()
329 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in rs600_pm_prepare()
336 struct drm_device *ddev = rdev->ddev; in rs600_pm_finish()
342 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { in rs600_pm_finish()
344 if (radeon_crtc->enabled) { in rs600_pm_finish()
345 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); in rs600_pm_finish()
347 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in rs600_pm_finish()
352 /* hpd for digital panel detect/disconnect */
353 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) in rs600_hpd_sense() argument
358 switch (hpd) { in rs600_hpd_sense()
376 enum radeon_hpd_id hpd) in rs600_hpd_set_polarity() argument
379 bool connected = rs600_hpd_sense(rdev, hpd); in rs600_hpd_set_polarity()
381 switch (hpd) { in rs600_hpd_set_polarity()
405 struct drm_device *dev = rdev->ddev; in rs600_hpd_init()
409 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { in rs600_hpd_init()
411 switch (radeon_connector->hpd.hpd) { in rs600_hpd_init()
423 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) in rs600_hpd_init()
424 enable |= 1 << radeon_connector->hpd.hpd; in rs600_hpd_init()
425 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); in rs600_hpd_init()
432 struct drm_device *dev = rdev->ddev; in rs600_hpd_fini()
436 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { in rs600_hpd_fini()
438 switch (radeon_connector->hpd.hpd) { in rs600_hpd_fini()
450 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) in rs600_hpd_fini()
451 disable |= 1 << radeon_connector->hpd.hpd; in rs600_hpd_fini()
469 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in rs600_asic_reset()
477 pci_save_state(rdev->pdev); in rs600_asic_reset()
479 pci_clear_master(rdev->pdev); in rs600_asic_reset()
489 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in rs600_asic_reset()
497 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in rs600_asic_reset()
505 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in rs600_asic_reset()
507 pci_restore_state(rdev->pdev); in rs600_asic_reset()
510 dev_err(rdev->dev, "failed to reset GPU\n"); in rs600_asic_reset()
511 ret = -1; in rs600_asic_reset()
513 dev_info(rdev->dev, "GPU reset succeed\n"); in rs600_asic_reset()
543 if (rdev->gart.robj) { in rs600_gart_init()
552 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; in rs600_gart_init()
561 if (rdev->gart.robj == NULL) { in rs600_gart_enable()
562 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); in rs600_gart_enable()
563 return -EINVAL; in rs600_gart_enable()
598 rdev->gart.table_addr); in rs600_gart_enable()
599 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); in rs600_gart_enable()
600 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); in rs600_gart_enable()
604 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); in rs600_gart_enable()
605 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); in rs600_gart_enable()
614 (unsigned)(rdev->mc.gtt_size >> 20), in rs600_gart_enable()
615 (unsigned long long)rdev->gart.table_addr); in rs600_gart_enable()
616 rdev->gart.ready = true; in rs600_gart_enable()
656 void __iomem *ptr = (void *)rdev->gart.ptr; in rs600_gart_set_page()
675 if (!rdev->irq.installed) { in rs600_irq_set()
676 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); in rs600_irq_set()
678 return -EINVAL; in rs600_irq_set()
680 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { in rs600_irq_set()
683 if (rdev->irq.crtc_vblank_int[0] || in rs600_irq_set()
684 atomic_read(&rdev->irq.pflip[0])) { in rs600_irq_set()
687 if (rdev->irq.crtc_vblank_int[1] || in rs600_irq_set()
688 atomic_read(&rdev->irq.pflip[1])) { in rs600_irq_set()
691 if (rdev->irq.hpd[0]) { in rs600_irq_set()
694 if (rdev->irq.hpd[1]) { in rs600_irq_set()
697 if (rdev->irq.afmt[0]) { in rs600_irq_set()
720 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); in rs600_irq_ack()
721 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
725 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
729 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
734 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
740 rdev->irq.stat_regs.r500.disp_int = 0; in rs600_irq_ack()
744 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) & in rs600_irq_ack()
746 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { in rs600_irq_ack()
752 rdev->irq.stat_regs.r500.hdmi0_status = 0; in rs600_irq_ack()
780 !rdev->irq.stat_regs.r500.disp_int && in rs600_irq_process()
781 !rdev->irq.stat_regs.r500.hdmi0_status) { in rs600_irq_process()
785 rdev->irq.stat_regs.r500.disp_int || in rs600_irq_process()
786 rdev->irq.stat_regs.r500.hdmi0_status) { in rs600_irq_process()
792 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_process()
793 if (rdev->irq.crtc_vblank_int[0]) { in rs600_irq_process()
794 drm_handle_vblank(rdev->ddev, 0); in rs600_irq_process()
795 rdev->pm.vblank_sync = true; in rs600_irq_process()
796 wake_up(&rdev->irq.vblank_queue); in rs600_irq_process()
798 if (atomic_read(&rdev->irq.pflip[0])) in rs600_irq_process()
801 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_process()
802 if (rdev->irq.crtc_vblank_int[1]) { in rs600_irq_process()
803 drm_handle_vblank(rdev->ddev, 1); in rs600_irq_process()
804 rdev->pm.vblank_sync = true; in rs600_irq_process()
805 wake_up(&rdev->irq.vblank_queue); in rs600_irq_process()
807 if (atomic_read(&rdev->irq.pflip[1])) in rs600_irq_process()
810 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_process()
814 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_process()
818 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { in rs600_irq_process()
825 schedule_delayed_work(&rdev->hotplug_work, 0); in rs600_irq_process()
827 schedule_work(&rdev->audio_work); in rs600_irq_process()
828 if (rdev->msi_enabled) { in rs600_irq_process()
829 switch (rdev->family) { in rs600_irq_process()
857 for (i = 0; i < rdev->usec_timeout; i++) { in rs600_mc_wait_for_idle()
862 return -1; in rs600_mc_wait_for_idle()
870 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); in rs600_gpu_init()
877 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); in rs600_mc_init()
878 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); in rs600_mc_init()
879 rdev->mc.vram_is_ddr = true; in rs600_mc_init()
880 rdev->mc.vram_width = 128; in rs600_mc_init()
881 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); in rs600_mc_init()
882 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; in rs600_mc_init()
883 rdev->mc.visible_vram_size = rdev->mc.aper_size; in rs600_mc_init()
884 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); in rs600_mc_init()
887 radeon_vram_location(rdev, &rdev->mc, base); in rs600_mc_init()
888 rdev->mc.gtt_base_align = 0; in rs600_mc_init()
889 radeon_gtt_location(rdev, &rdev->mc); in rs600_mc_init()
900 if (!rdev->mode_info.mode_config_initialized) in rs600_bandwidth_update()
905 if (rdev->mode_info.crtcs[0]->base.enabled) in rs600_bandwidth_update()
906 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rs600_bandwidth_update()
907 if (rdev->mode_info.crtcs[1]->base.enabled) in rs600_bandwidth_update()
908 mode1 = &rdev->mode_info.crtcs[1]->base.mode; in rs600_bandwidth_update()
912 if (rdev->disp_priority == 2) { in rs600_bandwidth_update()
929 spin_lock_irqsave(&rdev->mc_idx_lock, flags); in rs600_mc_rreg()
933 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); in rs600_mc_rreg()
941 spin_lock_irqsave(&rdev->mc_idx_lock, flags); in rs600_mc_wreg()
945 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); in rs600_mc_wreg()
956 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; in rs600_set_safe_registers()
957 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); in rs600_set_safe_registers()
969 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); in rs600_mc_program()
977 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | in rs600_mc_program()
978 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); in rs600_mc_program()
980 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); in rs600_mc_program()
1007 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in rs600_startup()
1012 if (!rdev->irq.installed) { in rs600_startup()
1019 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); in rs600_startup()
1023 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); in rs600_startup()
1029 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in rs600_startup()
1035 dev_err(rdev->dev, "failed initializing audio\n"); in rs600_startup()
1052 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in rs600_resume()
1057 atom_asic_init(rdev->mode_info.atom_context); in rs600_resume()
1063 rdev->accel_working = true; in rs600_resume()
1066 rdev->accel_working = false; in rs600_resume()
1095 kfree(rdev->bios); in rs600_fini()
1096 rdev->bios = NULL; in rs600_fini()
1114 return -EINVAL; in rs600_init()
1116 if (rdev->is_atom_bios) { in rs600_init()
1121 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); in rs600_init()
1122 return -EINVAL; in rs600_init()
1126 dev_warn(rdev->dev, in rs600_init()
1133 return -EINVAL; in rs600_init()
1136 radeon_get_clock_info(rdev->ddev); in rs600_init()
1156 rdev->accel_working = true; in rs600_init()
1160 dev_err(rdev->dev, "Disabling GPU acceleration\n"); in rs600_init()
1166 rdev->accel_working = false; in rs600_init()