Lines Matching full:tv
9 * Integrated TV out support based on the GATOS code by
21 * Unit for hPos (in TV clock periods)
36 /* tv standard constants */
49 /* tv pll setting for 27 mhz ref clk */
58 /* tv pll setting for 14 mhz ref clk */
169 * Table of all allowed modes for tv output
396 WREG32(RADEON_TV_UV_ADR, tv_dac->tv.tv_uv_adr); in radeon_restore_tv_timing_tables()
397 h_table = radeon_get_htiming_tables_addr(tv_dac->tv.tv_uv_adr); in radeon_restore_tv_timing_tables()
398 v_table = radeon_get_vtiming_tables_addr(tv_dac->tv.tv_uv_adr); in radeon_restore_tv_timing_tables()
401 tmp = ((uint32_t)tv_dac->tv.h_code_timing[i] << 14) | ((uint32_t)tv_dac->tv.h_code_timing[i+1]); in radeon_restore_tv_timing_tables()
403 if (tv_dac->tv.h_code_timing[i] == 0 || tv_dac->tv.h_code_timing[i + 1] == 0) in radeon_restore_tv_timing_tables()
407 tmp = ((uint32_t)tv_dac->tv.v_code_timing[i+1] << 14) | ((uint32_t)tv_dac->tv.v_code_timing[i]); in radeon_restore_tv_timing_tables()
409 if (tv_dac->tv.v_code_timing[i] == 0 || tv_dac->tv.v_code_timing[i + 1] == 0) in radeon_restore_tv_timing_tables()
419 WREG32(RADEON_TV_FRESTART, tv_dac->tv.frestart); in radeon_legacy_write_tv_restarts()
420 WREG32(RADEON_TV_HRESTART, tv_dac->tv.hrestart); in radeon_legacy_write_tv_restarts()
421 WREG32(RADEON_TV_VRESTART, tv_dac->tv.vrestart); in radeon_legacy_write_tv_restarts()
467 h_changed = (p1 != tv_dac->tv.h_code_timing[H_TABLE_POS1] || in radeon_legacy_tv_init_restarts()
468 p2 != tv_dac->tv.h_code_timing[H_TABLE_POS2]); in radeon_legacy_tv_init_restarts()
470 tv_dac->tv.h_code_timing[H_TABLE_POS1] = p1; in radeon_legacy_tv_init_restarts()
471 tv_dac->tv.h_code_timing[H_TABLE_POS2] = p2; in radeon_legacy_tv_init_restarts()
473 /* Convert hOffset from n. of TV clock periods to n. of CRTC clock periods (CRTC pixels) */ in radeon_legacy_tv_init_restarts()
480 * convert v_pos TV lines to n. of CRTC pixels in radeon_legacy_tv_init_restarts()
495 tv_dac->tv.hrestart = restart % h_total; in radeon_legacy_tv_init_restarts()
497 tv_dac->tv.vrestart = restart % v_total; in radeon_legacy_tv_init_restarts()
499 tv_dac->tv.frestart = restart % f_total; in radeon_legacy_tv_init_restarts()
502 (unsigned)tv_dac->tv.frestart, in radeon_legacy_tv_init_restarts()
503 (unsigned)tv_dac->tv.vrestart, in radeon_legacy_tv_init_restarts()
504 (unsigned)tv_dac->tv.hrestart); in radeon_legacy_tv_init_restarts()
516 tv_dac->tv.timing_cntl = (tv_dac->tv.timing_cntl & ~RADEON_H_INC_MASK) | in radeon_legacy_tv_init_restarts()
665 tv_dac->tv.timing_cntl = tmp; in radeon_legacy_tv_mode_set()
712 tv_dac->tv.tv_uv_adr = 0xc8; in radeon_legacy_tv_mode_set()
728 if ((tv_dac->tv.h_code_timing[i] = hor_timing[i]) == 0) in radeon_legacy_tv_mode_set()
733 if ((tv_dac->tv.v_code_timing[i] = vert_timing[i]) == 0) in radeon_legacy_tv_mode_set()
744 /* program the TV registers */ in radeon_legacy_tv_mode_set()
756 /* TV PLL */ in radeon_legacy_tv_mode_set()
774 /* TV HV */ in radeon_legacy_tv_mode_set()
793 /* TV restarts */ in radeon_legacy_tv_mode_set()
796 /* tv timings */ in radeon_legacy_tv_mode_set()
801 /* tv std */ in radeon_legacy_tv_mode_set()
803 WREG32(RADEON_TV_TIMING_CNTL, tv_dac->tv.timing_cntl); in radeon_legacy_tv_mode_set()