Lines Matching +full:reg +full:- +full:names
53 /* Firmware Names */
110 * r100_wait_for_vblank - vblank wait asic callback.
115 * Wait for vblank on the requested crtc (r1xx-r4xx).
121 if (crtc >= rdev->num_crtc) in r100_wait_for_vblank()
151 * r100_page_flip - pageflip callback.
157 * Does the actual pageflip (r1xx-r4xx).
164 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in r100_page_flip()
170 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); in r100_page_flip()
173 for (i = 0; i < rdev->usec_timeout; i++) { in r100_page_flip()
174 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) in r100_page_flip()
180 /* Unlock the lock, so double-buffering can take place inside vblank */ in r100_page_flip()
182 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); in r100_page_flip()
187 * r100_page_flip_pending - check if page flip is still pending
192 * Check if the last pagefilp is still pending (r1xx-r4xx).
197 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in r100_page_flip_pending()
200 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & in r100_page_flip_pending()
205 * r100_pm_get_dynpm_state - look up dynpm power state callback.
210 * current state of the GPU (r1xx-r5xx).
216 rdev->pm.dynpm_can_upclock = true; in r100_pm_get_dynpm_state()
217 rdev->pm.dynpm_can_downclock = true; in r100_pm_get_dynpm_state()
219 switch (rdev->pm.dynpm_planned_action) { in r100_pm_get_dynpm_state()
221 rdev->pm.requested_power_state_index = 0; in r100_pm_get_dynpm_state()
222 rdev->pm.dynpm_can_downclock = false; in r100_pm_get_dynpm_state()
225 if (rdev->pm.current_power_state_index == 0) { in r100_pm_get_dynpm_state()
226 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; in r100_pm_get_dynpm_state()
227 rdev->pm.dynpm_can_downclock = false; in r100_pm_get_dynpm_state()
229 if (rdev->pm.active_crtc_count > 1) { in r100_pm_get_dynpm_state()
230 for (i = 0; i < rdev->pm.num_power_states; i++) { in r100_pm_get_dynpm_state()
231 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r100_pm_get_dynpm_state()
233 else if (i >= rdev->pm.current_power_state_index) { in r100_pm_get_dynpm_state()
234 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; in r100_pm_get_dynpm_state()
237 rdev->pm.requested_power_state_index = i; in r100_pm_get_dynpm_state()
242 rdev->pm.requested_power_state_index = in r100_pm_get_dynpm_state()
243 rdev->pm.current_power_state_index - 1; in r100_pm_get_dynpm_state()
246 if ((rdev->pm.active_crtc_count > 0) && in r100_pm_get_dynpm_state()
247 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags & in r100_pm_get_dynpm_state()
249 rdev->pm.requested_power_state_index++; in r100_pm_get_dynpm_state()
253 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { in r100_pm_get_dynpm_state()
254 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; in r100_pm_get_dynpm_state()
255 rdev->pm.dynpm_can_upclock = false; in r100_pm_get_dynpm_state()
257 if (rdev->pm.active_crtc_count > 1) { in r100_pm_get_dynpm_state()
258 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { in r100_pm_get_dynpm_state()
259 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r100_pm_get_dynpm_state()
261 else if (i <= rdev->pm.current_power_state_index) { in r100_pm_get_dynpm_state()
262 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; in r100_pm_get_dynpm_state()
265 rdev->pm.requested_power_state_index = i; in r100_pm_get_dynpm_state()
270 rdev->pm.requested_power_state_index = in r100_pm_get_dynpm_state()
271 rdev->pm.current_power_state_index + 1; in r100_pm_get_dynpm_state()
275 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; in r100_pm_get_dynpm_state()
276 rdev->pm.dynpm_can_upclock = false; in r100_pm_get_dynpm_state()
284 rdev->pm.requested_clock_mode_index = 0; in r100_pm_get_dynpm_state()
287 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r100_pm_get_dynpm_state()
288 clock_info[rdev->pm.requested_clock_mode_index].sclk, in r100_pm_get_dynpm_state()
289 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r100_pm_get_dynpm_state()
290 clock_info[rdev->pm.requested_clock_mode_index].mclk, in r100_pm_get_dynpm_state()
291 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r100_pm_get_dynpm_state()
296 * r100_pm_init_profile - Initialize power profiles callback.
301 * (r1xx-r3xx).
307 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r100_pm_init_profile()
308 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r100_pm_init_profile()
309 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in r100_pm_init_profile()
310 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in r100_pm_init_profile()
312 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; in r100_pm_init_profile()
313 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; in r100_pm_init_profile()
314 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in r100_pm_init_profile()
315 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in r100_pm_init_profile()
317 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; in r100_pm_init_profile()
318 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; in r100_pm_init_profile()
319 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in r100_pm_init_profile()
320 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in r100_pm_init_profile()
322 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; in r100_pm_init_profile()
323 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r100_pm_init_profile()
324 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in r100_pm_init_profile()
325 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in r100_pm_init_profile()
327 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; in r100_pm_init_profile()
328 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r100_pm_init_profile()
329 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in r100_pm_init_profile()
330 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in r100_pm_init_profile()
332 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; in r100_pm_init_profile()
333 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r100_pm_init_profile()
334 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in r100_pm_init_profile()
335 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in r100_pm_init_profile()
337 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; in r100_pm_init_profile()
338 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r100_pm_init_profile()
339 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in r100_pm_init_profile()
340 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in r100_pm_init_profile()
344 * r100_pm_misc - set additional pm hw parameters callback.
348 * Set non-clock parameters associated with a power state
349 * (voltage, pcie lanes, etc.) (r1xx-r4xx).
353 int requested_index = rdev->pm.requested_power_state_index; in r100_pm_misc()
354 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; in r100_pm_misc()
355 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; in r100_pm_misc()
358 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { in r100_pm_misc()
359 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { in r100_pm_misc()
360 tmp = RREG32(voltage->gpio.reg); in r100_pm_misc()
361 if (voltage->active_high) in r100_pm_misc()
362 tmp |= voltage->gpio.mask; in r100_pm_misc()
364 tmp &= ~(voltage->gpio.mask); in r100_pm_misc()
365 WREG32(voltage->gpio.reg, tmp); in r100_pm_misc()
366 if (voltage->delay) in r100_pm_misc()
367 udelay(voltage->delay); in r100_pm_misc()
369 tmp = RREG32(voltage->gpio.reg); in r100_pm_misc()
370 if (voltage->active_high) in r100_pm_misc()
371 tmp &= ~voltage->gpio.mask; in r100_pm_misc()
373 tmp |= voltage->gpio.mask; in r100_pm_misc()
374 WREG32(voltage->gpio.reg, tmp); in r100_pm_misc()
375 if (voltage->delay) in r100_pm_misc()
376 udelay(voltage->delay); in r100_pm_misc()
385 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { in r100_pm_misc()
387 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE) in r100_pm_misc()
391 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) in r100_pm_misc()
393 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) in r100_pm_misc()
398 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { in r100_pm_misc()
400 if (voltage->delay) { in r100_pm_misc()
402 switch (voltage->delay) { in r100_pm_misc()
421 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) in r100_pm_misc()
431 if ((rdev->flags & RADEON_IS_PCIE) && in r100_pm_misc()
432 !(rdev->flags & RADEON_IS_IGP) && in r100_pm_misc()
433 rdev->asic->pm.set_pcie_lanes && in r100_pm_misc()
434 (ps->pcie_lanes != in r100_pm_misc()
435 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { in r100_pm_misc()
437 ps->pcie_lanes); in r100_pm_misc()
438 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes); in r100_pm_misc()
443 * r100_pm_prepare - pre-power state change callback.
447 * Prepare for a power state change (r1xx-r4xx).
451 struct drm_device *ddev = rdev->ddev; in r100_pm_prepare()
457 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { in r100_pm_prepare()
459 if (radeon_crtc->enabled) { in r100_pm_prepare()
460 if (radeon_crtc->crtc_id) { in r100_pm_prepare()
474 * r100_pm_finish - post-power state change callback.
478 * Clean up after a power state change (r1xx-r4xx).
482 struct drm_device *ddev = rdev->ddev; in r100_pm_finish()
488 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { in r100_pm_finish()
490 if (radeon_crtc->enabled) { in r100_pm_finish()
491 if (radeon_crtc->crtc_id) { in r100_pm_finish()
505 * r100_gui_idle - gui idle callback.
509 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
522 * r100_hpd_sense - hpd sense callback.
527 * Checks if a digital monitor is connected (r1xx-r4xx).
550 * r100_hpd_set_polarity - hpd set polarity callback.
555 * Set the polarity of the hpd pin (r1xx-r4xx).
586 * r100_hpd_init - hpd setup callback.
590 * Setup the hpd pins used by the card (r1xx-r4xx).
595 struct drm_device *dev = rdev->ddev; in r100_hpd_init()
599 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { in r100_hpd_init()
601 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) in r100_hpd_init()
602 enable |= 1 << radeon_connector->hpd.hpd; in r100_hpd_init()
603 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); in r100_hpd_init()
609 * r100_hpd_fini - hpd tear down callback.
613 * Tear down the hpd pins used by the card (r1xx-r4xx).
618 struct drm_device *dev = rdev->ddev; in r100_hpd_fini()
622 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { in r100_hpd_fini()
624 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) in r100_hpd_fini()
625 disable |= 1 << radeon_connector->hpd.hpd; in r100_hpd_fini()
645 if (rdev->gart.ptr) { in r100_pci_gart_init()
653 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; in r100_pci_gart_init()
654 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; in r100_pci_gart_init()
655 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; in r100_pci_gart_init()
656 rdev->asic->gart.set_page = &r100_pci_gart_set_page; in r100_pci_gart_init()
668 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); in r100_pci_gart_enable()
669 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); in r100_pci_gart_enable()
670 /* set PCI GART page-table base address */ in r100_pci_gart_enable()
671 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); in r100_pci_gart_enable()
676 (unsigned)(rdev->mc.gtt_size >> 20), in r100_pci_gart_enable()
677 (unsigned long long)rdev->gart.table_addr); in r100_pci_gart_enable()
678 rdev->gart.ready = true; in r100_pci_gart_enable()
701 u32 *gtt = rdev->gart.ptr; in r100_pci_gart_set_page()
716 if (!rdev->irq.installed) { in r100_irq_set()
719 return -EINVAL; in r100_irq_set()
721 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { in r100_irq_set()
724 if (rdev->irq.crtc_vblank_int[0] || in r100_irq_set()
725 atomic_read(&rdev->irq.pflip[0])) { in r100_irq_set()
728 if (rdev->irq.crtc_vblank_int[1] || in r100_irq_set()
729 atomic_read(&rdev->irq.pflip[1])) { in r100_irq_set()
732 if (rdev->irq.hpd[0]) { in r100_irq_set()
735 if (rdev->irq.hpd[1]) { in r100_irq_set()
779 if (rdev->shutdown) { in r100_irq_process()
789 if (rdev->irq.crtc_vblank_int[0]) { in r100_irq_process()
790 drm_handle_vblank(rdev->ddev, 0); in r100_irq_process()
791 rdev->pm.vblank_sync = true; in r100_irq_process()
792 wake_up(&rdev->irq.vblank_queue); in r100_irq_process()
794 if (atomic_read(&rdev->irq.pflip[0])) in r100_irq_process()
798 if (rdev->irq.crtc_vblank_int[1]) { in r100_irq_process()
799 drm_handle_vblank(rdev->ddev, 1); in r100_irq_process()
800 rdev->pm.vblank_sync = true; in r100_irq_process()
801 wake_up(&rdev->irq.vblank_queue); in r100_irq_process()
803 if (atomic_read(&rdev->irq.pflip[1])) in r100_irq_process()
817 schedule_delayed_work(&rdev->hotplug_work, 0); in r100_irq_process()
818 if (rdev->msi_enabled) { in r100_irq_process()
819 switch (rdev->family) { in r100_irq_process()
843 * r100_ring_hdp_flush - flush Host Data Path via the ring buffer
850 radeon_ring_write(ring, rdev->config.r100.hdp_cntl | in r100_ring_hdp_flush()
853 radeon_ring_write(ring, rdev->config.r100.hdp_cntl); in r100_ring_hdp_flush()
861 struct radeon_ring *ring = &rdev->ring[fence->ring]; in r100_fence_ring_emit()
874 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); in r100_fence_ring_emit()
875 radeon_ring_write(ring, fence->seq); in r100_fence_ring_emit()
896 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r100_copy_blit()
918 return ERR_PTR(-EINVAL); in r100_copy_blit()
925 num_gpu_pages -= cur_pages; in r100_copy_blit()
927 /* pages are in Y direction - height in r100_copy_blit()
928 page width in X direction - width */ in r100_copy_blit()
972 for (i = 0; i < rdev->usec_timeout; i++) { in r100_cp_wait_for_idle()
979 return -1; in r100_cp_wait_for_idle()
1008 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || in r100_cp_init_microcode()
1009 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || in r100_cp_init_microcode()
1010 (rdev->family == CHIP_RS200)) { in r100_cp_init_microcode()
1013 } else if ((rdev->family == CHIP_R200) || in r100_cp_init_microcode()
1014 (rdev->family == CHIP_RV250) || in r100_cp_init_microcode()
1015 (rdev->family == CHIP_RV280) || in r100_cp_init_microcode()
1016 (rdev->family == CHIP_RS300)) { in r100_cp_init_microcode()
1019 } else if ((rdev->family == CHIP_R300) || in r100_cp_init_microcode()
1020 (rdev->family == CHIP_R350) || in r100_cp_init_microcode()
1021 (rdev->family == CHIP_RV350) || in r100_cp_init_microcode()
1022 (rdev->family == CHIP_RV380) || in r100_cp_init_microcode()
1023 (rdev->family == CHIP_RS400) || in r100_cp_init_microcode()
1024 (rdev->family == CHIP_RS480)) { in r100_cp_init_microcode()
1027 } else if ((rdev->family == CHIP_R420) || in r100_cp_init_microcode()
1028 (rdev->family == CHIP_R423) || in r100_cp_init_microcode()
1029 (rdev->family == CHIP_RV410)) { in r100_cp_init_microcode()
1032 } else if ((rdev->family == CHIP_RS690) || in r100_cp_init_microcode()
1033 (rdev->family == CHIP_RS740)) { in r100_cp_init_microcode()
1036 } else if (rdev->family == CHIP_RS600) { in r100_cp_init_microcode()
1039 } else if ((rdev->family == CHIP_RV515) || in r100_cp_init_microcode()
1040 (rdev->family == CHIP_R520) || in r100_cp_init_microcode()
1041 (rdev->family == CHIP_RV530) || in r100_cp_init_microcode()
1042 (rdev->family == CHIP_R580) || in r100_cp_init_microcode()
1043 (rdev->family == CHIP_RV560) || in r100_cp_init_microcode()
1044 (rdev->family == CHIP_RV570)) { in r100_cp_init_microcode()
1049 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); in r100_cp_init_microcode()
1052 } else if (rdev->me_fw->size % 8) { in r100_cp_init_microcode()
1054 rdev->me_fw->size, fw_name); in r100_cp_init_microcode()
1055 err = -EINVAL; in r100_cp_init_microcode()
1056 release_firmware(rdev->me_fw); in r100_cp_init_microcode()
1057 rdev->me_fw = NULL; in r100_cp_init_microcode()
1067 if (rdev->wb.enabled) in r100_gfx_get_rptr()
1068 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); in r100_gfx_get_rptr()
1084 WREG32(RADEON_CP_RB_WPTR, ring->wptr); in r100_gfx_set_wptr()
1097 if (rdev->me_fw) { in r100_cp_load_microcode()
1098 size = rdev->me_fw->size / 4; in r100_cp_load_microcode()
1099 fw_data = (const __be32 *)&rdev->me_fw->data[0]; in r100_cp_load_microcode()
1112 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r100_cp_init()
1126 if (!rdev->me_fw) { in r100_cp_init()
1148 ring->align_mask = 16 - 1; in r100_cp_init()
1178 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr); in r100_cp_init()
1179 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr); in r100_cp_init()
1183 ring->wptr = 0; in r100_cp_init()
1184 WREG32(RADEON_CP_RB_WPTR, ring->wptr); in r100_cp_init()
1188 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2)); in r100_cp_init()
1189 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET); in r100_cp_init()
1191 if (rdev->wb.enabled) in r100_cp_init()
1209 pci_set_master(rdev->pdev); in r100_cp_init()
1211 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); in r100_cp_init()
1217 ring->ready = true; in r100_cp_init()
1218 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); in r100_cp_init()
1220 if (!ring->rptr_save_reg /* not resuming from suspend */ in r100_cp_init()
1222 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); in r100_cp_init()
1224 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); in r100_cp_init()
1225 ring->rptr_save_reg = 0; in r100_cp_init()
1238 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg); in r100_cp_fini()
1239 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); in r100_cp_fini()
1246 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); in r100_cp_disable()
1247 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in r100_cp_disable()
1262 unsigned reg) in r100_reloc_pitch_offset() argument
1273 idx, reg); in r100_reloc_pitch_offset()
1280 tmp += (((u32)reloc->gpu_offset) >> 10); in r100_reloc_pitch_offset()
1282 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { in r100_reloc_pitch_offset()
1283 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_reloc_pitch_offset()
1285 if (reloc->tiling_flags & RADEON_TILING_MICRO) { in r100_reloc_pitch_offset()
1286 if (reg == RADEON_SRC_PITCH_OFFSET) { in r100_reloc_pitch_offset()
1289 return -EINVAL; in r100_reloc_pitch_offset()
1295 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp; in r100_reloc_pitch_offset()
1297 p->ib.ptr[idx] = (value & 0xffc00000) | tmp; in r100_reloc_pitch_offset()
1312 ib = p->ib.ptr; in r100_packet3_load_vbpntr()
1313 track = (struct r100_cs_track *)p->track; in r100_packet3_load_vbpntr()
1317 pkt->opcode); in r100_packet3_load_vbpntr()
1319 return -EINVAL; in r100_packet3_load_vbpntr()
1321 track->num_arrays = c; in r100_packet3_load_vbpntr()
1322 for (i = 0; i < (c - 1); i+=2, idx+=3) { in r100_packet3_load_vbpntr()
1326 pkt->opcode); in r100_packet3_load_vbpntr()
1331 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()
1333 track->arrays[i + 0].esize = idx_value >> 8; in r100_packet3_load_vbpntr()
1334 track->arrays[i + 0].robj = reloc->robj; in r100_packet3_load_vbpntr()
1335 track->arrays[i + 0].esize &= 0x7F; in r100_packet3_load_vbpntr()
1339 pkt->opcode); in r100_packet3_load_vbpntr()
1343 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()
1344 track->arrays[i + 1].robj = reloc->robj; in r100_packet3_load_vbpntr()
1345 track->arrays[i + 1].esize = idx_value >> 24; in r100_packet3_load_vbpntr()
1346 track->arrays[i + 1].esize &= 0x7F; in r100_packet3_load_vbpntr()
1352 pkt->opcode); in r100_packet3_load_vbpntr()
1357 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()
1358 track->arrays[i + 0].robj = reloc->robj; in r100_packet3_load_vbpntr()
1359 track->arrays[i + 0].esize = idx_value >> 8; in r100_packet3_load_vbpntr()
1360 track->arrays[i + 0].esize &= 0x7F; in r100_packet3_load_vbpntr()
1370 unsigned reg; in r100_cs_parse_packet0() local
1375 idx = pkt->idx + 1; in r100_cs_parse_packet0()
1376 reg = pkt->reg; in r100_cs_parse_packet0()
1381 if (pkt->one_reg_wr) { in r100_cs_parse_packet0()
1382 if ((reg >> 7) > n) { in r100_cs_parse_packet0()
1383 return -EINVAL; in r100_cs_parse_packet0()
1386 if (((reg + (pkt->count << 2)) >> 7) > n) { in r100_cs_parse_packet0()
1387 return -EINVAL; in r100_cs_parse_packet0()
1390 for (i = 0; i <= pkt->count; i++, idx++) { in r100_cs_parse_packet0()
1391 j = (reg >> 7); in r100_cs_parse_packet0()
1392 m = 1 << ((reg >> 2) & 31); in r100_cs_parse_packet0()
1394 r = check(p, pkt, idx, reg); in r100_cs_parse_packet0()
1399 if (pkt->one_reg_wr) { in r100_cs_parse_packet0()
1404 reg += 4; in r100_cs_parse_packet0()
1411 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1415 * PACKET0 - VLINE_START_END + value
1416 * PACKET0 - WAIT_UNTIL +_value
1417 * RELOC (P3) - crtc_id in reloc.
1431 uint32_t header, h_idx, reg; in r100_cs_packet_parse_vline() local
1434 ib = p->ib.ptr; in r100_cs_packet_parse_vline()
1437 r = radeon_cs_packet_parse(p, &waitreloc, p->idx); in r100_cs_packet_parse_vline()
1442 if (waitreloc.reg != RADEON_WAIT_UNTIL || in r100_cs_packet_parse_vline()
1445 return -EINVAL; in r100_cs_packet_parse_vline()
1450 return -EINVAL; in r100_cs_packet_parse_vline()
1454 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); in r100_cs_packet_parse_vline()
1458 h_idx = p->idx - 2; in r100_cs_packet_parse_vline()
1459 p->idx += waitreloc.count + 2; in r100_cs_packet_parse_vline()
1460 p->idx += p3reloc.count + 2; in r100_cs_packet_parse_vline()
1464 reg = R100_CP_PACKET0_GET_REG(header); in r100_cs_packet_parse_vline()
1465 crtc = drm_crtc_find(p->rdev->ddev, p->filp, crtc_id); in r100_cs_packet_parse_vline()
1468 return -ENOENT; in r100_cs_packet_parse_vline()
1471 crtc_id = radeon_crtc->crtc_id; in r100_cs_packet_parse_vline()
1473 if (!crtc->enabled) { in r100_cs_packet_parse_vline()
1474 /* if the CRTC isn't enabled - we need to nop out the wait until */ in r100_cs_packet_parse_vline()
1478 switch (reg) { in r100_cs_packet_parse_vline()
1489 return -EINVAL; in r100_cs_packet_parse_vline()
1553 unsigned idx, unsigned reg) in r100_packet0_check() argument
1564 ib = p->ib.ptr; in r100_packet0_check()
1565 track = (struct r100_cs_track *)p->track; in r100_packet0_check()
1569 switch (reg) { in r100_packet0_check()
1574 idx, reg); in r100_packet0_check()
1583 r = r100_reloc_pitch_offset(p, pkt, idx, reg); in r100_packet0_check()
1591 idx, reg); in r100_packet0_check()
1595 track->zb.robj = reloc->robj; in r100_packet0_check()
1596 track->zb.offset = idx_value; in r100_packet0_check()
1597 track->zb_dirty = true; in r100_packet0_check()
1598 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1604 idx, reg); in r100_packet0_check()
1608 track->cb[0].robj = reloc->robj; in r100_packet0_check()
1609 track->cb[0].offset = idx_value; in r100_packet0_check()
1610 track->cb_dirty = true; in r100_packet0_check()
1611 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1616 i = (reg - RADEON_PP_TXOFFSET_0) / 24; in r100_packet0_check()
1620 idx, reg); in r100_packet0_check()
1624 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { in r100_packet0_check()
1625 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()
1627 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check()
1632 ib[idx] = tmp + ((u32)reloc->gpu_offset); in r100_packet0_check()
1634 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1635 track->textures[i].robj = reloc->robj; in r100_packet0_check()
1636 track->tex_dirty = true; in r100_packet0_check()
1643 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; in r100_packet0_check()
1647 idx, reg); in r100_packet0_check()
1651 track->textures[0].cube_info[i].offset = idx_value; in r100_packet0_check()
1652 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1653 track->textures[0].cube_info[i].robj = reloc->robj; in r100_packet0_check()
1654 track->tex_dirty = true; in r100_packet0_check()
1661 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; in r100_packet0_check()
1665 idx, reg); in r100_packet0_check()
1669 track->textures[1].cube_info[i].offset = idx_value; in r100_packet0_check()
1670 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1671 track->textures[1].cube_info[i].robj = reloc->robj; in r100_packet0_check()
1672 track->tex_dirty = true; in r100_packet0_check()
1679 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; in r100_packet0_check()
1683 idx, reg); in r100_packet0_check()
1687 track->textures[2].cube_info[i].offset = idx_value; in r100_packet0_check()
1688 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1689 track->textures[2].cube_info[i].robj = reloc->robj; in r100_packet0_check()
1690 track->tex_dirty = true; in r100_packet0_check()
1693 track->maxy = ((idx_value >> 16) & 0x7FF); in r100_packet0_check()
1694 track->cb_dirty = true; in r100_packet0_check()
1695 track->zb_dirty = true; in r100_packet0_check()
1701 idx, reg); in r100_packet0_check()
1705 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { in r100_packet0_check()
1706 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()
1708 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check()
1717 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; in r100_packet0_check()
1718 track->cb_dirty = true; in r100_packet0_check()
1721 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; in r100_packet0_check()
1722 track->zb_dirty = true; in r100_packet0_check()
1731 track->cb[0].cpp = 1; in r100_packet0_check()
1736 track->cb[0].cpp = 2; in r100_packet0_check()
1739 track->cb[0].cpp = 4; in r100_packet0_check()
1744 return -EINVAL; in r100_packet0_check()
1746 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); in r100_packet0_check()
1747 track->cb_dirty = true; in r100_packet0_check()
1748 track->zb_dirty = true; in r100_packet0_check()
1753 track->zb.cpp = 2; in r100_packet0_check()
1761 track->zb.cpp = 4; in r100_packet0_check()
1766 track->zb_dirty = true; in r100_packet0_check()
1772 idx, reg); in r100_packet0_check()
1776 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1781 for (i = 0; i < track->num_texture; i++) in r100_packet0_check()
1782 track->textures[i].enabled = !!(temp & (1 << i)); in r100_packet0_check()
1783 track->tex_dirty = true; in r100_packet0_check()
1787 track->vap_vf_cntl = idx_value; in r100_packet0_check()
1790 track->vtx_size = r100_get_vtx_size(idx_value); in r100_packet0_check()
1795 i = (reg - RADEON_PP_TEX_SIZE_0) / 8; in r100_packet0_check()
1796 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; in r100_packet0_check()
1797 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; in r100_packet0_check()
1798 track->tex_dirty = true; in r100_packet0_check()
1803 i = (reg - RADEON_PP_TEX_PITCH_0) / 8; in r100_packet0_check()
1804 track->textures[i].pitch = idx_value + 32; in r100_packet0_check()
1805 track->tex_dirty = true; in r100_packet0_check()
1810 i = (reg - RADEON_PP_TXFILTER_0) / 24; in r100_packet0_check()
1811 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) in r100_packet0_check()
1815 track->textures[i].roundup_w = false; in r100_packet0_check()
1818 track->textures[i].roundup_h = false; in r100_packet0_check()
1819 track->tex_dirty = true; in r100_packet0_check()
1824 i = (reg - RADEON_PP_TXFORMAT_0) / 24; in r100_packet0_check()
1826 track->textures[i].use_pitch = true; in r100_packet0_check()
1828 track->textures[i].use_pitch = false; in r100_packet0_check()
1829 …track->textures[i].width = 1 << ((idx_value & RADEON_TXFORMAT_WIDTH_MASK) >> RADEON_TXFORMAT_WIDTH… in r100_packet0_check()
1830 …track->textures[i].height = 1 << ((idx_value & RADEON_TXFORMAT_HEIGHT_MASK) >> RADEON_TXFORMAT_HEI… in r100_packet0_check()
1833 track->textures[i].tex_coord_type = 2; in r100_packet0_check()
1838 track->textures[i].cpp = 1; in r100_packet0_check()
1839 track->textures[i].compress_format = R100_TRACK_COMP_NONE; in r100_packet0_check()
1850 track->textures[i].cpp = 2; in r100_packet0_check()
1851 track->textures[i].compress_format = R100_TRACK_COMP_NONE; in r100_packet0_check()
1857 track->textures[i].cpp = 4; in r100_packet0_check()
1858 track->textures[i].compress_format = R100_TRACK_COMP_NONE; in r100_packet0_check()
1861 track->textures[i].cpp = 1; in r100_packet0_check()
1862 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; in r100_packet0_check()
1866 track->textures[i].cpp = 1; in r100_packet0_check()
1867 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; in r100_packet0_check()
1870 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); in r100_packet0_check()
1871 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); in r100_packet0_check()
1872 track->tex_dirty = true; in r100_packet0_check()
1878 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; in r100_packet0_check()
1880 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); in r100_packet0_check()
1881 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); in r100_packet0_check()
1883 track->tex_dirty = true; in r100_packet0_check()
1886 pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx); in r100_packet0_check()
1887 return -EINVAL; in r100_packet0_check()
1898 idx = pkt->idx + 1; in r100_cs_track_check_pkt3_indx_buffer()
1905 return -EINVAL; in r100_cs_track_check_pkt3_indx_buffer()
1919 ib = p->ib.ptr; in r100_packet3_check()
1920 idx = pkt->idx + 1; in r100_packet3_check()
1921 track = (struct r100_cs_track *)p->track; in r100_packet3_check()
1922 switch (pkt->opcode) { in r100_packet3_check()
1931 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); in r100_packet3_check()
1935 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset); in r100_packet3_check()
1936 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); in r100_packet3_check()
1945 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); in r100_packet3_check()
1949 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset); in r100_packet3_check()
1950 track->num_arrays = 1; in r100_packet3_check()
1951 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); in r100_packet3_check()
1953 track->arrays[0].robj = reloc->robj; in r100_packet3_check()
1954 track->arrays[0].esize = track->vtx_size; in r100_packet3_check()
1956 track->max_indx = radeon_get_ib_value(p, idx+1); in r100_packet3_check()
1958 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); in r100_packet3_check()
1959 track->immd_dwords = pkt->count - 1; in r100_packet3_check()
1960 r = r100_cs_track_check(p->rdev, track); in r100_packet3_check()
1967 return -EINVAL; in r100_packet3_check()
1969 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); in r100_packet3_check()
1970 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); in r100_packet3_check()
1971 track->immd_dwords = pkt->count - 1; in r100_packet3_check()
1972 r = r100_cs_track_check(p->rdev, track); in r100_packet3_check()
1976 /* triggers drawing using in-packet vertex data */ in r100_packet3_check()
1980 return -EINVAL; in r100_packet3_check()
1982 track->vap_vf_cntl = radeon_get_ib_value(p, idx); in r100_packet3_check()
1983 track->immd_dwords = pkt->count; in r100_packet3_check()
1984 r = r100_cs_track_check(p->rdev, track); in r100_packet3_check()
1988 /* triggers drawing using in-packet vertex data */ in r100_packet3_check()
1990 track->vap_vf_cntl = radeon_get_ib_value(p, idx); in r100_packet3_check()
1991 r = r100_cs_track_check(p->rdev, track); in r100_packet3_check()
1997 track->vap_vf_cntl = radeon_get_ib_value(p, idx); in r100_packet3_check()
1998 r = r100_cs_track_check(p->rdev, track); in r100_packet3_check()
2004 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); in r100_packet3_check()
2005 r = r100_cs_track_check(p->rdev, track); in r100_packet3_check()
2011 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); in r100_packet3_check()
2012 r = r100_cs_track_check(p->rdev, track); in r100_packet3_check()
2019 if (p->rdev->hyperz_filp != p->filp) in r100_packet3_check()
2020 return -EINVAL; in r100_packet3_check()
2025 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); in r100_packet3_check()
2026 return -EINVAL; in r100_packet3_check()
2039 return -ENOMEM; in r100_cs_parse()
2040 r100_cs_track_clear(p->rdev, track); in r100_cs_parse()
2041 p->track = track; in r100_cs_parse()
2043 r = radeon_cs_packet_parse(p, &pkt, p->idx); in r100_cs_parse()
2047 p->idx += pkt.count + 2; in r100_cs_parse()
2050 if (p->rdev->family >= CHIP_R200) in r100_cs_parse()
2052 p->rdev->config.r100.reg_safe_bm, in r100_cs_parse()
2053 p->rdev->config.r100.reg_safe_bm_size, in r100_cs_parse()
2057 p->rdev->config.r100.reg_safe_bm, in r100_cs_parse()
2058 p->rdev->config.r100.reg_safe_bm_size, in r100_cs_parse()
2069 return -EINVAL; in r100_cs_parse()
2073 } while (p->idx < p->chunk_ib->length_dw); in r100_cs_parse()
2079 DRM_ERROR("pitch %d\n", t->pitch); in r100_cs_track_texture_print()
2080 DRM_ERROR("use_pitch %d\n", t->use_pitch); in r100_cs_track_texture_print()
2081 DRM_ERROR("width %d\n", t->width); in r100_cs_track_texture_print()
2082 DRM_ERROR("width_11 %d\n", t->width_11); in r100_cs_track_texture_print()
2083 DRM_ERROR("height %d\n", t->height); in r100_cs_track_texture_print()
2084 DRM_ERROR("height_11 %d\n", t->height_11); in r100_cs_track_texture_print()
2085 DRM_ERROR("num levels %d\n", t->num_levels); in r100_cs_track_texture_print()
2086 DRM_ERROR("depth %d\n", t->txdepth); in r100_cs_track_texture_print()
2087 DRM_ERROR("bpp %d\n", t->cpp); in r100_cs_track_texture_print()
2088 DRM_ERROR("coordinate type %d\n", t->tex_coord_type); in r100_cs_track_texture_print()
2089 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); in r100_cs_track_texture_print()
2090 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); in r100_cs_track_texture_print()
2091 DRM_ERROR("compress format %d\n", t->compress_format); in r100_cs_track_texture_print()
2116 hblocks = (h + block_height - 1) / block_height; in r100_track_compress_size()
2117 wblocks = (w + block_width - 1) / block_width; in r100_track_compress_size()
2130 unsigned compress_format = track->textures[idx].compress_format; in r100_cs_track_cube()
2133 cube_robj = track->textures[idx].cube_info[face].robj; in r100_cs_track_cube()
2134 w = track->textures[idx].cube_info[face].width; in r100_cs_track_cube()
2135 h = track->textures[idx].cube_info[face].height; in r100_cs_track_cube()
2141 size *= track->textures[idx].cpp; in r100_cs_track_cube()
2143 size += track->textures[idx].cube_info[face].offset; in r100_cs_track_cube()
2148 r100_cs_track_texture_print(&track->textures[idx]); in r100_cs_track_cube()
2149 return -1; in r100_cs_track_cube()
2163 for (u = 0; u < track->num_texture; u++) { in r100_cs_track_texture_check()
2164 if (!track->textures[u].enabled) in r100_cs_track_texture_check()
2166 if (track->textures[u].lookup_disable) in r100_cs_track_texture_check()
2168 robj = track->textures[u].robj; in r100_cs_track_texture_check()
2171 return -EINVAL; in r100_cs_track_texture_check()
2174 for (i = 0; i <= track->textures[u].num_levels; i++) { in r100_cs_track_texture_check()
2175 if (track->textures[u].use_pitch) { in r100_cs_track_texture_check()
2176 if (rdev->family < CHIP_R300) in r100_cs_track_texture_check()
2177 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); in r100_cs_track_texture_check()
2179 w = track->textures[u].pitch / (1 << i); in r100_cs_track_texture_check()
2181 w = track->textures[u].width; in r100_cs_track_texture_check()
2182 if (rdev->family >= CHIP_RV515) in r100_cs_track_texture_check()
2183 w |= track->textures[u].width_11; in r100_cs_track_texture_check()
2185 if (track->textures[u].roundup_w) in r100_cs_track_texture_check()
2188 h = track->textures[u].height; in r100_cs_track_texture_check()
2189 if (rdev->family >= CHIP_RV515) in r100_cs_track_texture_check()
2190 h |= track->textures[u].height_11; in r100_cs_track_texture_check()
2192 if (track->textures[u].roundup_h) in r100_cs_track_texture_check()
2194 if (track->textures[u].tex_coord_type == 1) { in r100_cs_track_texture_check()
2195 d = (1 << track->textures[u].txdepth) / (1 << i); in r100_cs_track_texture_check()
2201 if (track->textures[u].compress_format) { in r100_cs_track_texture_check()
2203 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d; in r100_cs_track_texture_check()
2208 size *= track->textures[u].cpp; in r100_cs_track_texture_check()
2210 switch (track->textures[u].tex_coord_type) { in r100_cs_track_texture_check()
2215 if (track->separate_cube) { in r100_cs_track_texture_check()
2224 "%u\n", track->textures[u].tex_coord_type, u); in r100_cs_track_texture_check()
2225 return -EINVAL; in r100_cs_track_texture_check()
2230 r100_cs_track_texture_print(&track->textures[u]); in r100_cs_track_texture_check()
2231 return -EINVAL; in r100_cs_track_texture_check()
2243 unsigned num_cb = track->cb_dirty ? track->num_cb : 0; in r100_cs_track_check()
2245 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask && in r100_cs_track_check()
2246 !track->blend_read_enable) in r100_cs_track_check()
2250 if (track->cb[i].robj == NULL) { in r100_cs_track_check()
2252 return -EINVAL; in r100_cs_track_check()
2254 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; in r100_cs_track_check()
2255 size += track->cb[i].offset; in r100_cs_track_check()
2256 if (size > radeon_bo_size(track->cb[i].robj)) { in r100_cs_track_check()
2259 radeon_bo_size(track->cb[i].robj)); in r100_cs_track_check()
2261 i, track->cb[i].pitch, track->cb[i].cpp, in r100_cs_track_check()
2262 track->cb[i].offset, track->maxy); in r100_cs_track_check()
2263 return -EINVAL; in r100_cs_track_check()
2266 track->cb_dirty = false; in r100_cs_track_check()
2268 if (track->zb_dirty && track->z_enabled) { in r100_cs_track_check()
2269 if (track->zb.robj == NULL) { in r100_cs_track_check()
2271 return -EINVAL; in r100_cs_track_check()
2273 size = track->zb.pitch * track->zb.cpp * track->maxy; in r100_cs_track_check()
2274 size += track->zb.offset; in r100_cs_track_check()
2275 if (size > radeon_bo_size(track->zb.robj)) { in r100_cs_track_check()
2278 radeon_bo_size(track->zb.robj)); in r100_cs_track_check()
2280 track->zb.pitch, track->zb.cpp, in r100_cs_track_check()
2281 track->zb.offset, track->maxy); in r100_cs_track_check()
2282 return -EINVAL; in r100_cs_track_check()
2285 track->zb_dirty = false; in r100_cs_track_check()
2287 if (track->aa_dirty && track->aaresolve) { in r100_cs_track_check()
2288 if (track->aa.robj == NULL) { in r100_cs_track_check()
2290 return -EINVAL; in r100_cs_track_check()
2293 size = track->aa.pitch * track->cb[0].cpp * track->maxy; in r100_cs_track_check()
2294 size += track->aa.offset; in r100_cs_track_check()
2295 if (size > radeon_bo_size(track->aa.robj)) { in r100_cs_track_check()
2298 radeon_bo_size(track->aa.robj)); in r100_cs_track_check()
2300 i, track->aa.pitch, track->cb[0].cpp, in r100_cs_track_check()
2301 track->aa.offset, track->maxy); in r100_cs_track_check()
2302 return -EINVAL; in r100_cs_track_check()
2305 track->aa_dirty = false; in r100_cs_track_check()
2307 prim_walk = (track->vap_vf_cntl >> 4) & 0x3; in r100_cs_track_check()
2308 if (track->vap_vf_cntl & (1 << 14)) { in r100_cs_track_check()
2309 nverts = track->vap_alt_nverts; in r100_cs_track_check()
2311 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; in r100_cs_track_check()
2315 for (i = 0; i < track->num_arrays; i++) { in r100_cs_track_check()
2316 size = track->arrays[i].esize * track->max_indx * 4; in r100_cs_track_check()
2317 if (track->arrays[i].robj == NULL) { in r100_cs_track_check()
2320 return -EINVAL; in r100_cs_track_check()
2322 if (size > radeon_bo_size(track->arrays[i].robj)) { in r100_cs_track_check()
2323 dev_err(rdev->dev, "(PW %u) Vertex array %u " in r100_cs_track_check()
2326 radeon_bo_size(track->arrays[i].robj) in r100_cs_track_check()
2328 DRM_ERROR("Max indices %u\n", track->max_indx); in r100_cs_track_check()
2329 return -EINVAL; in r100_cs_track_check()
2334 for (i = 0; i < track->num_arrays; i++) { in r100_cs_track_check()
2335 size = track->arrays[i].esize * (nverts - 1) * 4; in r100_cs_track_check()
2336 if (track->arrays[i].robj == NULL) { in r100_cs_track_check()
2339 return -EINVAL; in r100_cs_track_check()
2341 if (size > radeon_bo_size(track->arrays[i].robj)) { in r100_cs_track_check()
2342 dev_err(rdev->dev, "(PW %u) Vertex array %u " in r100_cs_track_check()
2345 radeon_bo_size(track->arrays[i].robj) in r100_cs_track_check()
2347 return -EINVAL; in r100_cs_track_check()
2352 size = track->vtx_size * nverts; in r100_cs_track_check()
2353 if (size != track->immd_dwords) { in r100_cs_track_check()
2355 track->immd_dwords, size); in r100_cs_track_check()
2357 nverts, track->vtx_size); in r100_cs_track_check()
2358 return -EINVAL; in r100_cs_track_check()
2364 return -EINVAL; in r100_cs_track_check()
2367 if (track->tex_dirty) { in r100_cs_track_check()
2368 track->tex_dirty = false; in r100_cs_track_check()
2378 track->cb_dirty = true; in r100_cs_track_clear()
2379 track->zb_dirty = true; in r100_cs_track_clear()
2380 track->tex_dirty = true; in r100_cs_track_clear()
2381 track->aa_dirty = true; in r100_cs_track_clear()
2383 if (rdev->family < CHIP_R300) { in r100_cs_track_clear()
2384 track->num_cb = 1; in r100_cs_track_clear()
2385 if (rdev->family <= CHIP_RS200) in r100_cs_track_clear()
2386 track->num_texture = 3; in r100_cs_track_clear()
2388 track->num_texture = 6; in r100_cs_track_clear()
2389 track->maxy = 2048; in r100_cs_track_clear()
2390 track->separate_cube = true; in r100_cs_track_clear()
2392 track->num_cb = 4; in r100_cs_track_clear()
2393 track->num_texture = 16; in r100_cs_track_clear()
2394 track->maxy = 4096; in r100_cs_track_clear()
2395 track->separate_cube = false; in r100_cs_track_clear()
2396 track->aaresolve = false; in r100_cs_track_clear()
2397 track->aa.robj = NULL; in r100_cs_track_clear()
2400 for (i = 0; i < track->num_cb; i++) { in r100_cs_track_clear()
2401 track->cb[i].robj = NULL; in r100_cs_track_clear()
2402 track->cb[i].pitch = 8192; in r100_cs_track_clear()
2403 track->cb[i].cpp = 16; in r100_cs_track_clear()
2404 track->cb[i].offset = 0; in r100_cs_track_clear()
2406 track->z_enabled = true; in r100_cs_track_clear()
2407 track->zb.robj = NULL; in r100_cs_track_clear()
2408 track->zb.pitch = 8192; in r100_cs_track_clear()
2409 track->zb.cpp = 4; in r100_cs_track_clear()
2410 track->zb.offset = 0; in r100_cs_track_clear()
2411 track->vtx_size = 0x7F; in r100_cs_track_clear()
2412 track->immd_dwords = 0xFFFFFFFFUL; in r100_cs_track_clear()
2413 track->num_arrays = 11; in r100_cs_track_clear()
2414 track->max_indx = 0x00FFFFFFUL; in r100_cs_track_clear()
2415 for (i = 0; i < track->num_arrays; i++) { in r100_cs_track_clear()
2416 track->arrays[i].robj = NULL; in r100_cs_track_clear()
2417 track->arrays[i].esize = 0x7F; in r100_cs_track_clear()
2419 for (i = 0; i < track->num_texture; i++) { in r100_cs_track_clear()
2420 track->textures[i].compress_format = R100_TRACK_COMP_NONE; in r100_cs_track_clear()
2421 track->textures[i].pitch = 16536; in r100_cs_track_clear()
2422 track->textures[i].width = 16536; in r100_cs_track_clear()
2423 track->textures[i].height = 16536; in r100_cs_track_clear()
2424 track->textures[i].width_11 = 1 << 11; in r100_cs_track_clear()
2425 track->textures[i].height_11 = 1 << 11; in r100_cs_track_clear()
2426 track->textures[i].num_levels = 12; in r100_cs_track_clear()
2427 if (rdev->family <= CHIP_RS200) { in r100_cs_track_clear()
2428 track->textures[i].tex_coord_type = 0; in r100_cs_track_clear()
2429 track->textures[i].txdepth = 0; in r100_cs_track_clear()
2431 track->textures[i].txdepth = 16; in r100_cs_track_clear()
2432 track->textures[i].tex_coord_type = 1; in r100_cs_track_clear()
2434 track->textures[i].cpp = 64; in r100_cs_track_clear()
2435 track->textures[i].robj = NULL; in r100_cs_track_clear()
2437 track->textures[i].enabled = false; in r100_cs_track_clear()
2438 track->textures[i].lookup_disable = false; in r100_cs_track_clear()
2439 track->textures[i].roundup_w = true; in r100_cs_track_clear()
2440 track->textures[i].roundup_h = true; in r100_cs_track_clear()
2441 if (track->separate_cube) in r100_cs_track_clear()
2443 track->textures[i].cube_info[face].robj = NULL; in r100_cs_track_clear()
2444 track->textures[i].cube_info[face].width = 16536; in r100_cs_track_clear()
2445 track->textures[i].cube_info[face].height = 16536; in r100_cs_track_clear()
2446 track->textures[i].cube_info[face].offset = 0; in r100_cs_track_clear()
2456 rdev->pll_errata = 0; in r100_errata()
2458 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { in r100_errata()
2459 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; in r100_errata()
2462 if (rdev->family == CHIP_RV100 || in r100_errata()
2463 rdev->family == CHIP_RS100 || in r100_errata()
2464 rdev->family == CHIP_RS200) { in r100_errata()
2465 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; in r100_errata()
2474 for (i = 0; i < rdev->usec_timeout; i++) { in r100_rbbm_fifo_wait_for_entry()
2481 return -1; in r100_rbbm_fifo_wait_for_entry()
2492 for (i = 0; i < rdev->usec_timeout; i++) { in r100_gui_wait_for_idle()
2499 return -1; in r100_gui_wait_for_idle()
2507 for (i = 0; i < rdev->usec_timeout; i++) { in r100_mc_wait_for_idle()
2515 return -1; in r100_mc_wait_for_idle()
2552 pci_clear_master(rdev->pdev); in r100_bm_disable()
2568 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in r100_asic_reset()
2577 pci_save_state(rdev->pdev); in r100_asic_reset()
2589 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in r100_asic_reset()
2597 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in r100_asic_reset()
2599 pci_restore_state(rdev->pdev); in r100_asic_reset()
2604 dev_err(rdev->dev, "failed to reset GPU\n"); in r100_asic_reset()
2605 ret = -1; in r100_asic_reset()
2607 dev_info(rdev->dev, "GPU reset succeed\n"); in r100_asic_reset()
2614 struct drm_device *dev = rdev->ddev; in r100_set_common_regs()
2632 switch (dev->pdev->device) { in r100_set_common_regs()
2642 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) && in r100_set_common_regs()
2643 ((dev->pdev->subsystem_device == 0x016c) || in r100_set_common_regs()
2644 (dev->pdev->subsystem_device == 0x016d) || in r100_set_common_regs()
2645 (dev->pdev->subsystem_device == 0x016e) || in r100_set_common_regs()
2646 (dev->pdev->subsystem_device == 0x016f) || in r100_set_common_regs()
2647 (dev->pdev->subsystem_device == 0x0170) || in r100_set_common_regs()
2648 (dev->pdev->subsystem_device == 0x017d) || in r100_set_common_regs()
2649 (dev->pdev->subsystem_device == 0x017e) || in r100_set_common_regs()
2650 (dev->pdev->subsystem_device == 0x0183) || in r100_set_common_regs()
2651 (dev->pdev->subsystem_device == 0x018a) || in r100_set_common_regs()
2652 (dev->pdev->subsystem_device == 0x019a))) in r100_set_common_regs()
2703 rdev->mc.vram_is_ddr = false; in r100_vram_get_type()
2704 if (rdev->flags & RADEON_IS_IGP) in r100_vram_get_type()
2705 rdev->mc.vram_is_ddr = true; in r100_vram_get_type()
2707 rdev->mc.vram_is_ddr = true; in r100_vram_get_type()
2708 if ((rdev->family == CHIP_RV100) || in r100_vram_get_type()
2709 (rdev->family == CHIP_RS100) || in r100_vram_get_type()
2710 (rdev->family == CHIP_RS200)) { in r100_vram_get_type()
2713 rdev->mc.vram_width = 32; in r100_vram_get_type()
2715 rdev->mc.vram_width = 64; in r100_vram_get_type()
2717 if (rdev->flags & RADEON_SINGLE_CRTC) { in r100_vram_get_type()
2718 rdev->mc.vram_width /= 4; in r100_vram_get_type()
2719 rdev->mc.vram_is_ddr = true; in r100_vram_get_type()
2721 } else if (rdev->family <= CHIP_RV280) { in r100_vram_get_type()
2724 rdev->mc.vram_width = 128; in r100_vram_get_type()
2726 rdev->mc.vram_width = 64; in r100_vram_get_type()
2730 rdev->mc.vram_width = 128; in r100_vram_get_type()
2744 if (rdev->family == CHIP_RV280 || in r100_get_accessible_vram()
2745 rdev->family >= CHIP_RV350) { in r100_get_accessible_vram()
2756 pci_read_config_byte(rdev->pdev, 0xe, &byte); in r100_get_accessible_vram()
2777 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); in r100_vram_init_sizes()
2778 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); in r100_vram_init_sizes()
2779 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); in r100_vram_init_sizes()
2781 if (rdev->mc.visible_vram_size > rdev->mc.aper_size) in r100_vram_init_sizes()
2782 rdev->mc.visible_vram_size = rdev->mc.aper_size; in r100_vram_init_sizes()
2784 if (rdev->flags & RADEON_IS_IGP) { in r100_vram_init_sizes()
2788 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); in r100_vram_init_sizes()
2789 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); in r100_vram_init_sizes()
2790 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; in r100_vram_init_sizes()
2792 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); in r100_vram_init_sizes()
2796 if (rdev->mc.real_vram_size == 0) { in r100_vram_init_sizes()
2797 rdev->mc.real_vram_size = 8192 * 1024; in r100_vram_init_sizes()
2798 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); in r100_vram_init_sizes()
2800 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - in r100_vram_init_sizes()
2803 if (rdev->mc.aper_size > config_aper_size) in r100_vram_init_sizes()
2804 config_aper_size = rdev->mc.aper_size; in r100_vram_init_sizes()
2806 if (config_aper_size > rdev->mc.real_vram_size) in r100_vram_init_sizes()
2807 rdev->mc.mc_vram_size = config_aper_size; in r100_vram_init_sizes()
2809 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; in r100_vram_init_sizes()
2833 base = rdev->mc.aper_base; in r100_mc_init()
2834 if (rdev->flags & RADEON_IS_IGP) in r100_mc_init()
2836 radeon_vram_location(rdev, &rdev->mc, base); in r100_mc_init()
2837 rdev->mc.gtt_base_align = 0; in r100_mc_init()
2838 if (!(rdev->flags & RADEON_IS_AGP)) in r100_mc_init()
2839 radeon_gtt_location(rdev, &rdev->mc); in r100_mc_init()
2849 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) { in r100_pll_errata_after_index()
2860 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { in r100_pll_errata_after_data()
2869 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { in r100_pll_errata_after_data()
2880 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) in r100_pll_rreg() argument
2885 spin_lock_irqsave(&rdev->pll_idx_lock, flags); in r100_pll_rreg()
2886 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); in r100_pll_rreg()
2890 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags); in r100_pll_rreg()
2894 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) in r100_pll_wreg() argument
2898 spin_lock_irqsave(&rdev->pll_idx_lock, flags); in r100_pll_wreg()
2899 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); in r100_pll_wreg()
2903 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags); in r100_pll_wreg()
2909 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; in r100_set_safe_registers()
2910 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); in r100_set_safe_registers()
2911 } else if (rdev->family < CHIP_R200) { in r100_set_safe_registers()
2912 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; in r100_set_safe_registers()
2913 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); in r100_set_safe_registers()
2925 struct drm_info_node *node = (struct drm_info_node *) m->private; in r100_debugfs_rbbm_info()
2926 struct drm_device *dev = node->minor->dev; in r100_debugfs_rbbm_info()
2927 struct radeon_device *rdev = dev->dev_private; in r100_debugfs_rbbm_info()
2928 uint32_t reg, value; in r100_debugfs_rbbm_info() local
2936 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; in r100_debugfs_rbbm_info()
2939 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value); in r100_debugfs_rbbm_info()
2946 struct drm_info_node *node = (struct drm_info_node *) m->private; in r100_debugfs_cp_ring_info()
2947 struct drm_device *dev = node->minor->dev; in r100_debugfs_cp_ring_info()
2948 struct radeon_device *rdev = dev->dev_private; in r100_debugfs_cp_ring_info()
2949 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r100_debugfs_cp_ring_info()
2956 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask; in r100_debugfs_cp_ring_info()
2960 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); in r100_debugfs_cp_ring_info()
2962 if (ring->ready) { in r100_debugfs_cp_ring_info()
2964 i = (rdp + j) & ring->ptr_mask; in r100_debugfs_cp_ring_info()
2965 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]); in r100_debugfs_cp_ring_info()
2974 struct drm_info_node *node = (struct drm_info_node *) m->private; in r100_debugfs_cp_csq_fifo()
2975 struct drm_device *dev = node->minor->dev; in r100_debugfs_cp_csq_fifo()
2976 struct radeon_device *rdev = dev->dev_private; in r100_debugfs_cp_csq_fifo()
3024 struct drm_info_node *node = (struct drm_info_node *) m->private; in r100_debugfs_mc_info()
3025 struct drm_device *dev = node->minor->dev; in r100_debugfs_mc_info()
3026 struct radeon_device *rdev = dev->dev_private; in r100_debugfs_mc_info()
3093 int r100_set_surface_reg(struct radeon_device *rdev, int reg, in r100_set_surface_reg() argument
3097 int surf_index = reg * 16; in r100_set_surface_reg()
3100 if (rdev->family <= CHIP_RS200) { in r100_set_surface_reg()
3110 } else if (rdev->family <= CHIP_RV280) { in r100_set_surface_reg()
3128 if (rdev->family < CHIP_R300) in r100_set_surface_reg()
3134 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); in r100_set_surface_reg()
3137 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); in r100_set_surface_reg()
3141 void r100_clear_surface_reg(struct radeon_device *rdev, int reg) in r100_clear_surface_reg() argument
3143 int surf_index = reg * 16; in r100_clear_surface_reg()
3222 if (!rdev->mode_info.mode_config_initialized) in r100_bandwidth_update()
3227 if (rdev->mode_info.crtcs[0]->base.enabled) { in r100_bandwidth_update()
3229 rdev->mode_info.crtcs[0]->base.primary->fb; in r100_bandwidth_update()
3231 mode1 = &rdev->mode_info.crtcs[0]->base.mode; in r100_bandwidth_update()
3232 pixel_bytes1 = fb->format->cpp[0]; in r100_bandwidth_update()
3234 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { in r100_bandwidth_update()
3235 if (rdev->mode_info.crtcs[1]->base.enabled) { in r100_bandwidth_update()
3237 rdev->mode_info.crtcs[1]->base.primary->fb; in r100_bandwidth_update()
3239 mode2 = &rdev->mode_info.crtcs[1]->base.mode; in r100_bandwidth_update()
3240 pixel_bytes2 = fb->format->cpp[0]; in r100_bandwidth_update()
3246 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { in r100_bandwidth_update()
3261 sclk_ff = rdev->pm.sclk; in r100_bandwidth_update()
3262 mclk_ff = rdev->pm.mclk; in r100_bandwidth_update()
3264 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); in r100_bandwidth_update()
3273 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ in r100_bandwidth_update()
3280 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ in r100_bandwidth_update()
3294 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ in r100_bandwidth_update()
3298 } else if (rdev->family == CHIP_R300 || in r100_bandwidth_update()
3299 rdev->family == CHIP_R350) { /* r300, r350 */ in r100_bandwidth_update()
3303 } else if (rdev->family == CHIP_RV350 || in r100_bandwidth_update()
3304 rdev->family == CHIP_RV380) { in r100_bandwidth_update()
3309 } else if (rdev->family == CHIP_R420 || in r100_bandwidth_update()
3310 rdev->family == CHIP_R423 || in r100_bandwidth_update()
3311 rdev->family == CHIP_RV410) { in r100_bandwidth_update()
3335 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { in r100_bandwidth_update()
3336 if (rdev->family == CHIP_RS480) /* don't think rs400 */ in r100_bandwidth_update()
3343 if (rdev->family == CHIP_RS400 || in r100_bandwidth_update()
3344 rdev->family == CHIP_RS480) { in r100_bandwidth_update()
3345 /* extra cas latency stored in bits 23-25 0-4 clocks */ in r100_bandwidth_update()
3351 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { in r100_bandwidth_update()
3372 if (rdev->family == CHIP_RV410 || in r100_bandwidth_update()
3373 rdev->family == CHIP_R420 || in r100_bandwidth_update()
3374 rdev->family == CHIP_R423) in r100_bandwidth_update()
3383 if (rdev->flags & RADEON_IS_AGP) { in r100_bandwidth_update()
3387 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff); in r100_bandwidth_update()
3389 /* TODO PCIE lanes may affect this - agpmode == 16?? */ in r100_bandwidth_update()
3394 if ((rdev->family == CHIP_RV100) || in r100_bandwidth_update()
3395 rdev->flags & RADEON_IS_IGP) { in r100_bandwidth_update()
3396 if (rdev->mc.vram_is_ddr) in r100_bandwidth_update()
3401 if (rdev->mc.vram_width == 128) in r100_bandwidth_update()
3410 if (rdev->mc.vram_is_ddr) { in r100_bandwidth_update()
3411 if (rdev->mc.vram_width == 32) { in r100_bandwidth_update()
3438 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); in r100_bandwidth_update()
3470 stop_req = mode1->hdisplay * pixel_bytes1 / 16; in r100_bandwidth_update()
3489 if (rdev->disp_priority == 2) { in r100_bandwidth_update()
3494 The critical point should never be above max_stop_req-4. Setting in r100_bandwidth_update()
3497 if (max_stop_req - critical_point < 4) in r100_bandwidth_update()
3500 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { in r100_bandwidth_update()
3509 if ((rdev->family == CHIP_R350) && in r100_bandwidth_update()
3511 stop_req -= 0x10; in r100_bandwidth_update()
3525 if ((rdev->family == CHIP_RS400) || in r100_bandwidth_update()
3526 (rdev->family == CHIP_RS480)) { in r100_bandwidth_update()
3544 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ in r100_bandwidth_update()
3550 stop_req = mode2->hdisplay * pixel_bytes2 / 16; in r100_bandwidth_update()
3565 if ((rdev->family == CHIP_R350) && in r100_bandwidth_update()
3567 stop_req -= 0x10; in r100_bandwidth_update()
3575 if ((rdev->family == CHIP_RS100) || in r100_bandwidth_update()
3576 (rdev->family == CHIP_RS200)) in r100_bandwidth_update()
3579 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; in r100_bandwidth_update()
3588 temp_ff.full = read_return_rate.full - disp_drain_rate.full; in r100_bandwidth_update()
3599 if (rdev->disp_priority == 2) { in r100_bandwidth_update()
3603 if (max_stop_req - critical_point2 < 4) in r100_bandwidth_update()
3608 if (critical_point2 == 0 && rdev->family == CHIP_R300) { in r100_bandwidth_update()
3616 if ((rdev->family == CHIP_RS400) || in r100_bandwidth_update()
3617 (rdev->family == CHIP_RS480)) { in r100_bandwidth_update()
3645 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay); in r100_bandwidth_update()
3648 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay); in r100_bandwidth_update()
3660 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); in r100_ring_test()
3673 for (i = 0; i < rdev->usec_timeout; i++) { in r100_ring_test()
3680 if (i < rdev->usec_timeout) { in r100_ring_test()
3685 r = -EINVAL; in r100_ring_test()
3693 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r100_ring_ib_execute()
3695 if (ring->rptr_save_reg) { in r100_ring_ib_execute()
3696 u32 next_rptr = ring->wptr + 2 + 3; in r100_ring_ib_execute()
3697 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0)); in r100_ring_ib_execute()
3702 radeon_ring_write(ring, ib->gpu_addr); in r100_ring_ib_execute()
3703 radeon_ring_write(ring, ib->length_dw); in r100_ring_ib_execute()
3716 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); in r100_ib_test()
3746 r = -ETIMEDOUT; in r100_ib_test()
3750 for (i = 0; i < rdev->usec_timeout; i++) { in r100_ib_test()
3757 if (i < rdev->usec_timeout) { in r100_ib_test()
3762 r = -EINVAL; in r100_ib_test()
3776 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in r100_mc_stop()
3780 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); in r100_mc_stop()
3781 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); in r100_mc_stop()
3782 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); in r100_mc_stop()
3783 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); in r100_mc_stop()
3784 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { in r100_mc_stop()
3785 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); in r100_mc_stop()
3786 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); in r100_mc_stop()
3790 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); in r100_mc_stop()
3792 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); in r100_mc_stop()
3793 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | in r100_mc_stop()
3796 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | in r100_mc_stop()
3800 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); in r100_mc_stop()
3801 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { in r100_mc_stop()
3802 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | in r100_mc_stop()
3805 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | in r100_mc_stop()
3809 C_000360_CUR2_LOCK & save->CUR2_OFFSET); in r100_mc_stop()
3816 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); in r100_mc_resume()
3817 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { in r100_mc_resume()
3818 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); in r100_mc_resume()
3821 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); in r100_mc_resume()
3822 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); in r100_mc_resume()
3823 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); in r100_mc_resume()
3824 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { in r100_mc_resume()
3825 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); in r100_mc_resume()
3843 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n"); in r100_debugfs()
3852 if (rdev->flags & RADEON_IS_AGP) { in r100_mc_program()
3854 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | in r100_mc_program()
3855 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); in r100_mc_program()
3856 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); in r100_mc_program()
3857 if (rdev->family > CHIP_RV200) in r100_mc_program()
3859 upper_32_bits(rdev->mc.agp_base) & 0xff); in r100_mc_program()
3863 if (rdev->family > CHIP_RV200) in r100_mc_program()
3868 dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); in r100_mc_program()
3871 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | in r100_mc_program()
3872 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); in r100_mc_program()
3880 if (radeon_dynclks != -1 && radeon_dynclks) in r100_clock_startup()
3885 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) in r100_clock_startup()
3903 if (rdev->flags & RADEON_IS_PCI) { in r100_startup()
3916 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in r100_startup()
3921 if (!rdev->irq.installed) { in r100_startup()
3928 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); in r100_startup()
3932 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); in r100_startup()
3938 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in r100_startup()
3950 if (rdev->flags & RADEON_IS_PCI) in r100_resume()
3956 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in r100_resume()
3961 radeon_combios_asic_init(rdev->ddev); in r100_resume()
3967 rdev->accel_working = true; in r100_resume()
3970 rdev->accel_working = false; in r100_resume()
3981 if (rdev->flags & RADEON_IS_PCI) in r100_suspend()
3993 if (rdev->flags & RADEON_IS_PCI) in r100_fini()
4000 kfree(rdev->bios); in r100_fini()
4001 rdev->bios = NULL; in r100_fini()
4047 return -EINVAL; in r100_init()
4049 if (rdev->is_atom_bios) { in r100_init()
4050 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); in r100_init()
4051 return -EINVAL; in r100_init()
4059 dev_warn(rdev->dev, in r100_init()
4066 return -EINVAL; in r100_init()
4070 radeon_get_clock_info(rdev->ddev); in r100_init()
4072 if (rdev->flags & RADEON_IS_AGP) { in r100_init()
4088 if (rdev->flags & RADEON_IS_PCI) { in r100_init()
4098 rdev->accel_working = true; in r100_init()
4102 dev_err(rdev->dev, "Disabling GPU acceleration\n"); in r100_init()
4107 if (rdev->flags & RADEON_IS_PCI) in r100_init()
4109 rdev->accel_working = false; in r100_init()
4114 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg) in r100_mm_rreg_slow() argument
4119 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); in r100_mm_rreg_slow()
4120 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); in r100_mm_rreg_slow()
4121 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); in r100_mm_rreg_slow()
4122 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); in r100_mm_rreg_slow()
4126 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v) in r100_mm_wreg_slow() argument
4130 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); in r100_mm_wreg_slow()
4131 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); in r100_mm_wreg_slow()
4132 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); in r100_mm_wreg_slow()
4133 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); in r100_mm_wreg_slow()
4136 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) in r100_io_rreg() argument
4138 if (reg < rdev->rio_mem_size) in r100_io_rreg()
4139 return ioread32(rdev->rio_mem + reg); in r100_io_rreg()
4141 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); in r100_io_rreg()
4142 return ioread32(rdev->rio_mem + RADEON_MM_DATA); in r100_io_rreg()
4146 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) in r100_io_wreg() argument
4148 if (reg < rdev->rio_mem_size) in r100_io_wreg()
4149 iowrite32(v, rdev->rio_mem + reg); in r100_io_wreg()
4151 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); in r100_io_wreg()
4152 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA); in r100_io_wreg()