Lines Matching full:track
47 /* value we track */
118 static void evergreen_cs_track_init(struct evergreen_cs_track *track) in evergreen_cs_track_init() argument
123 track->cb_color_fmask_bo[i] = NULL; in evergreen_cs_track_init()
124 track->cb_color_cmask_bo[i] = NULL; in evergreen_cs_track_init()
125 track->cb_color_cmask_slice[i] = 0; in evergreen_cs_track_init()
126 track->cb_color_fmask_slice[i] = 0; in evergreen_cs_track_init()
130 track->cb_color_bo[i] = NULL; in evergreen_cs_track_init()
131 track->cb_color_bo_offset[i] = 0xFFFFFFFF; in evergreen_cs_track_init()
132 track->cb_color_info[i] = 0; in evergreen_cs_track_init()
133 track->cb_color_view[i] = 0xFFFFFFFF; in evergreen_cs_track_init()
134 track->cb_color_pitch[i] = 0; in evergreen_cs_track_init()
135 track->cb_color_slice[i] = 0xfffffff; in evergreen_cs_track_init()
136 track->cb_color_slice_idx[i] = 0; in evergreen_cs_track_init()
138 track->cb_target_mask = 0xFFFFFFFF; in evergreen_cs_track_init()
139 track->cb_shader_mask = 0xFFFFFFFF; in evergreen_cs_track_init()
140 track->cb_dirty = true; in evergreen_cs_track_init()
142 track->db_depth_slice = 0xffffffff; in evergreen_cs_track_init()
143 track->db_depth_view = 0xFFFFC000; in evergreen_cs_track_init()
144 track->db_depth_size = 0xFFFFFFFF; in evergreen_cs_track_init()
145 track->db_depth_control = 0xFFFFFFFF; in evergreen_cs_track_init()
146 track->db_z_info = 0xFFFFFFFF; in evergreen_cs_track_init()
147 track->db_z_read_offset = 0xFFFFFFFF; in evergreen_cs_track_init()
148 track->db_z_write_offset = 0xFFFFFFFF; in evergreen_cs_track_init()
149 track->db_z_read_bo = NULL; in evergreen_cs_track_init()
150 track->db_z_write_bo = NULL; in evergreen_cs_track_init()
151 track->db_s_info = 0xFFFFFFFF; in evergreen_cs_track_init()
152 track->db_s_read_offset = 0xFFFFFFFF; in evergreen_cs_track_init()
153 track->db_s_write_offset = 0xFFFFFFFF; in evergreen_cs_track_init()
154 track->db_s_read_bo = NULL; in evergreen_cs_track_init()
155 track->db_s_write_bo = NULL; in evergreen_cs_track_init()
156 track->db_dirty = true; in evergreen_cs_track_init()
157 track->htile_bo = NULL; in evergreen_cs_track_init()
158 track->htile_offset = 0xFFFFFFFF; in evergreen_cs_track_init()
159 track->htile_surface = 0; in evergreen_cs_track_init()
162 track->vgt_strmout_size[i] = 0; in evergreen_cs_track_init()
163 track->vgt_strmout_bo[i] = NULL; in evergreen_cs_track_init()
164 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF; in evergreen_cs_track_init()
166 track->streamout_dirty = true; in evergreen_cs_track_init()
167 track->sx_misc_kill_all_prims = false; in evergreen_cs_track_init()
205 struct evergreen_cs_track *track = p->track; in evergreen_surface_check_linear_aligned() local
208 palign = MAX(64, track->group_size / surf->bpe); in evergreen_surface_check_linear_aligned()
210 surf->base_align = track->group_size; in evergreen_surface_check_linear_aligned()
227 struct evergreen_cs_track *track = p->track; in evergreen_surface_check_1d() local
230 palign = track->group_size / (8 * surf->bpe * surf->nsamples); in evergreen_surface_check_1d()
233 surf->base_align = track->group_size; in evergreen_surface_check_1d()
240 track->group_size, surf->bpe, surf->nsamples); in evergreen_surface_check_1d()
258 struct evergreen_cs_track *track = p->track; in evergreen_surface_check_2d() local
269 palign = (8 * surf->bankw * track->npipes) * surf->mtilea; in evergreen_surface_check_2d()
396 struct evergreen_cs_track *track = p->track; in evergreen_cs_track_validate_cb() local
402 mslice = G_028C6C_SLICE_MAX(track->cb_color_view[id]) + 1; in evergreen_cs_track_validate_cb()
403 pitch = track->cb_color_pitch[id]; in evergreen_cs_track_validate_cb()
404 slice = track->cb_color_slice[id]; in evergreen_cs_track_validate_cb()
407 surf.mode = G_028C70_ARRAY_MODE(track->cb_color_info[id]); in evergreen_cs_track_validate_cb()
408 surf.format = G_028C70_FORMAT(track->cb_color_info[id]); in evergreen_cs_track_validate_cb()
409 surf.tsplit = G_028C74_TILE_SPLIT(track->cb_color_attrib[id]); in evergreen_cs_track_validate_cb()
410 surf.nbanks = G_028C74_NUM_BANKS(track->cb_color_attrib[id]); in evergreen_cs_track_validate_cb()
411 surf.bankw = G_028C74_BANK_WIDTH(track->cb_color_attrib[id]); in evergreen_cs_track_validate_cb()
412 surf.bankh = G_028C74_BANK_HEIGHT(track->cb_color_attrib[id]); in evergreen_cs_track_validate_cb()
413 surf.mtilea = G_028C74_MACRO_TILE_ASPECT(track->cb_color_attrib[id]); in evergreen_cs_track_validate_cb()
419 id, track->cb_color_info[id]); in evergreen_cs_track_validate_cb()
431 __func__, __LINE__, id, track->cb_color_pitch[id], in evergreen_cs_track_validate_cb()
432 track->cb_color_slice[id], track->cb_color_attrib[id], in evergreen_cs_track_validate_cb()
433 track->cb_color_info[id]); in evergreen_cs_track_validate_cb()
437 offset = track->cb_color_bo_offset[id] << 8; in evergreen_cs_track_validate_cb()
445 if (offset > radeon_bo_size(track->cb_color_bo[id])) { in evergreen_cs_track_validate_cb()
458 bsize = radeon_bo_size(track->cb_color_bo[id]); in evergreen_cs_track_validate_cb()
459 tmp = track->cb_color_bo_offset[id] << 8; in evergreen_cs_track_validate_cb()
473 ib[track->cb_color_slice_idx[id]] = slice; in evergreen_cs_track_validate_cb()
482 track->cb_color_bo_offset[id] << 8, mslice, in evergreen_cs_track_validate_cb()
483 radeon_bo_size(track->cb_color_bo[id]), slice); in evergreen_cs_track_validate_cb()
499 struct evergreen_cs_track *track = p->track; in evergreen_cs_track_validate_htile() local
502 if (track->htile_bo == NULL) { in evergreen_cs_track_validate_htile()
504 __func__, __LINE__, track->db_z_info); in evergreen_cs_track_validate_htile()
508 if (G_028ABC_LINEAR(track->htile_surface)) { in evergreen_cs_track_validate_htile()
512 nby = round_up(nby, track->npipes * 8); in evergreen_cs_track_validate_htile()
518 switch (track->npipes) { in evergreen_cs_track_validate_htile()
541 __func__, __LINE__, track->npipes); in evergreen_cs_track_validate_htile()
549 size = roundup(nbx * nby * 4, track->npipes * (2 << 10)); in evergreen_cs_track_validate_htile()
550 size += track->htile_offset; in evergreen_cs_track_validate_htile()
552 if (size > radeon_bo_size(track->htile_bo)) { in evergreen_cs_track_validate_htile()
554 __func__, __LINE__, radeon_bo_size(track->htile_bo), in evergreen_cs_track_validate_htile()
563 struct evergreen_cs_track *track = p->track; in evergreen_cs_track_validate_stencil() local
569 mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1; in evergreen_cs_track_validate_stencil()
570 pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size); in evergreen_cs_track_validate_stencil()
571 slice = track->db_depth_slice; in evergreen_cs_track_validate_stencil()
574 surf.mode = G_028040_ARRAY_MODE(track->db_z_info); in evergreen_cs_track_validate_stencil()
575 surf.format = G_028044_FORMAT(track->db_s_info); in evergreen_cs_track_validate_stencil()
576 surf.tsplit = G_028044_TILE_SPLIT(track->db_s_info); in evergreen_cs_track_validate_stencil()
577 surf.nbanks = G_028040_NUM_BANKS(track->db_z_info); in evergreen_cs_track_validate_stencil()
578 surf.bankw = G_028040_BANK_WIDTH(track->db_z_info); in evergreen_cs_track_validate_stencil()
579 surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info); in evergreen_cs_track_validate_stencil()
580 surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info); in evergreen_cs_track_validate_stencil()
606 __func__, __LINE__, track->db_depth_size, in evergreen_cs_track_validate_stencil()
607 track->db_depth_slice, track->db_s_info, track->db_z_info); in evergreen_cs_track_validate_stencil()
612 offset = track->db_s_read_offset << 8; in evergreen_cs_track_validate_stencil()
619 if (offset > radeon_bo_size(track->db_s_read_bo)) { in evergreen_cs_track_validate_stencil()
623 (unsigned long)track->db_s_read_offset << 8, mslice, in evergreen_cs_track_validate_stencil()
624 radeon_bo_size(track->db_s_read_bo)); in evergreen_cs_track_validate_stencil()
626 __func__, __LINE__, track->db_depth_size, in evergreen_cs_track_validate_stencil()
627 track->db_depth_slice, track->db_s_info, track->db_z_info); in evergreen_cs_track_validate_stencil()
631 offset = track->db_s_write_offset << 8; in evergreen_cs_track_validate_stencil()
638 if (offset > radeon_bo_size(track->db_s_write_bo)) { in evergreen_cs_track_validate_stencil()
642 (unsigned long)track->db_s_write_offset << 8, mslice, in evergreen_cs_track_validate_stencil()
643 radeon_bo_size(track->db_s_write_bo)); in evergreen_cs_track_validate_stencil()
648 if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) { in evergreen_cs_track_validate_stencil()
660 struct evergreen_cs_track *track = p->track; in evergreen_cs_track_validate_depth() local
666 mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1; in evergreen_cs_track_validate_depth()
667 pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size); in evergreen_cs_track_validate_depth()
668 slice = track->db_depth_slice; in evergreen_cs_track_validate_depth()
671 surf.mode = G_028040_ARRAY_MODE(track->db_z_info); in evergreen_cs_track_validate_depth()
672 surf.format = G_028040_FORMAT(track->db_z_info); in evergreen_cs_track_validate_depth()
673 surf.tsplit = G_028040_TILE_SPLIT(track->db_z_info); in evergreen_cs_track_validate_depth()
674 surf.nbanks = G_028040_NUM_BANKS(track->db_z_info); in evergreen_cs_track_validate_depth()
675 surf.bankw = G_028040_BANK_WIDTH(track->db_z_info); in evergreen_cs_track_validate_depth()
676 surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info); in evergreen_cs_track_validate_depth()
677 surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info); in evergreen_cs_track_validate_depth()
697 __func__, __LINE__, track->db_depth_size, in evergreen_cs_track_validate_depth()
698 track->db_depth_slice, track->db_z_info); in evergreen_cs_track_validate_depth()
705 __func__, __LINE__, track->db_depth_size, in evergreen_cs_track_validate_depth()
706 track->db_depth_slice, track->db_z_info); in evergreen_cs_track_validate_depth()
710 offset = track->db_z_read_offset << 8; in evergreen_cs_track_validate_depth()
717 if (offset > radeon_bo_size(track->db_z_read_bo)) { in evergreen_cs_track_validate_depth()
721 (unsigned long)track->db_z_read_offset << 8, mslice, in evergreen_cs_track_validate_depth()
722 radeon_bo_size(track->db_z_read_bo)); in evergreen_cs_track_validate_depth()
726 offset = track->db_z_write_offset << 8; in evergreen_cs_track_validate_depth()
733 if (offset > radeon_bo_size(track->db_z_write_bo)) { in evergreen_cs_track_validate_depth()
737 (unsigned long)track->db_z_write_offset << 8, mslice, in evergreen_cs_track_validate_depth()
738 radeon_bo_size(track->db_z_write_bo)); in evergreen_cs_track_validate_depth()
743 if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) { in evergreen_cs_track_validate_depth()
934 struct evergreen_cs_track *track = p->track; in evergreen_cs_track_check() local
940 if (track->streamout_dirty && track->vgt_strmout_config) { in evergreen_cs_track_check()
942 if (track->vgt_strmout_config & (1 << i)) { in evergreen_cs_track_check()
943 buffer_mask |= (track->vgt_strmout_buffer_config >> (i * 4)) & 0xf; in evergreen_cs_track_check()
949 if (track->vgt_strmout_bo[i]) { in evergreen_cs_track_check()
950 u64 offset = (u64)track->vgt_strmout_bo_offset[i] + in evergreen_cs_track_check()
951 (u64)track->vgt_strmout_size[i]; in evergreen_cs_track_check()
952 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) { in evergreen_cs_track_check()
955 radeon_bo_size(track->vgt_strmout_bo[i])); in evergreen_cs_track_check()
964 track->streamout_dirty = false; in evergreen_cs_track_check()
967 if (track->sx_misc_kill_all_prims) in evergreen_cs_track_check()
972 if (track->cb_dirty) { in evergreen_cs_track_check()
973 tmp = track->cb_target_mask; in evergreen_cs_track_check()
975 u32 format = G_028C70_FORMAT(track->cb_color_info[i]); in evergreen_cs_track_check()
980 if (track->cb_color_bo[i] == NULL) { in evergreen_cs_track_check()
982 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i); in evergreen_cs_track_check()
992 track->cb_dirty = false; in evergreen_cs_track_check()
995 if (track->db_dirty) { in evergreen_cs_track_check()
997 if (G_028044_FORMAT(track->db_s_info) != V_028044_STENCIL_INVALID && in evergreen_cs_track_check()
998 G_028800_STENCIL_ENABLE(track->db_depth_control)) { in evergreen_cs_track_check()
1004 if (G_028040_FORMAT(track->db_z_info) != V_028040_Z_INVALID && in evergreen_cs_track_check()
1005 G_028800_Z_ENABLE(track->db_depth_control)) { in evergreen_cs_track_check()
1010 track->db_dirty = false; in evergreen_cs_track_check()
1096 struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track; in evergreen_cs_handle_reg() local
1152 track->db_depth_control = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1153 track->db_dirty = true; in evergreen_cs_handle_reg()
1170 track->db_z_info = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1179 track->db_z_info &= ~Z_ARRAY_MODE(0xf); in evergreen_cs_handle_reg()
1181 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1188 ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_handle_reg()
1195 track->db_dirty = true; in evergreen_cs_handle_reg()
1198 track->db_s_info = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1199 track->db_dirty = true; in evergreen_cs_handle_reg()
1202 track->db_depth_view = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1203 track->db_dirty = true; in evergreen_cs_handle_reg()
1206 track->db_depth_size = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1207 track->db_dirty = true; in evergreen_cs_handle_reg()
1210 track->db_depth_slice = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1211 track->db_dirty = true; in evergreen_cs_handle_reg()
1220 track->db_z_read_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1222 track->db_z_read_bo = reloc->robj; in evergreen_cs_handle_reg()
1223 track->db_dirty = true; in evergreen_cs_handle_reg()
1232 track->db_z_write_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1234 track->db_z_write_bo = reloc->robj; in evergreen_cs_handle_reg()
1235 track->db_dirty = true; in evergreen_cs_handle_reg()
1244 track->db_s_read_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1246 track->db_s_read_bo = reloc->robj; in evergreen_cs_handle_reg()
1247 track->db_dirty = true; in evergreen_cs_handle_reg()
1256 track->db_s_write_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1258 track->db_s_write_bo = reloc->robj; in evergreen_cs_handle_reg()
1259 track->db_dirty = true; in evergreen_cs_handle_reg()
1262 track->vgt_strmout_config = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1263 track->streamout_dirty = true; in evergreen_cs_handle_reg()
1266 track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1267 track->streamout_dirty = true; in evergreen_cs_handle_reg()
1280 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; in evergreen_cs_handle_reg()
1282 track->vgt_strmout_bo[tmp] = reloc->robj; in evergreen_cs_handle_reg()
1283 track->streamout_dirty = true; in evergreen_cs_handle_reg()
1291 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4; in evergreen_cs_handle_reg()
1292 track->streamout_dirty = true; in evergreen_cs_handle_reg()
1304 track->cb_target_mask = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1305 track->cb_dirty = true; in evergreen_cs_handle_reg()
1308 track->cb_shader_mask = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1309 track->cb_dirty = true; in evergreen_cs_handle_reg()
1318 track->nsamples = 1 << tmp; in evergreen_cs_handle_reg()
1327 track->nsamples = 1 << tmp; in evergreen_cs_handle_reg()
1338 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1339 track->cb_dirty = true; in evergreen_cs_handle_reg()
1346 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1347 track->cb_dirty = true; in evergreen_cs_handle_reg()
1358 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1367 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1369 track->cb_dirty = true; in evergreen_cs_handle_reg()
1376 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1385 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1387 track->cb_dirty = true; in evergreen_cs_handle_reg()
1398 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1399 track->cb_dirty = true; in evergreen_cs_handle_reg()
1406 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1407 track->cb_dirty = true; in evergreen_cs_handle_reg()
1418 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1419 track->cb_color_slice_idx[tmp] = idx; in evergreen_cs_handle_reg()
1420 track->cb_dirty = true; in evergreen_cs_handle_reg()
1427 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1428 track->cb_color_slice_idx[tmp] = idx; in evergreen_cs_handle_reg()
1429 track->cb_dirty = true; in evergreen_cs_handle_reg()
1452 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_handle_reg()
1460 track->cb_color_attrib[tmp] = ib[idx]; in evergreen_cs_handle_reg()
1461 track->cb_dirty = true; in evergreen_cs_handle_reg()
1480 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_handle_reg()
1488 track->cb_color_attrib[tmp] = ib[idx]; in evergreen_cs_handle_reg()
1489 track->cb_dirty = true; in evergreen_cs_handle_reg()
1506 track->cb_color_fmask_bo[tmp] = reloc->robj; in evergreen_cs_handle_reg()
1523 track->cb_color_cmask_bo[tmp] = reloc->robj; in evergreen_cs_handle_reg()
1534 track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1545 track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1562 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1564 track->cb_color_bo[tmp] = reloc->robj; in evergreen_cs_handle_reg()
1565 track->cb_dirty = true; in evergreen_cs_handle_reg()
1578 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1580 track->cb_color_bo[tmp] = reloc->robj; in evergreen_cs_handle_reg()
1581 track->cb_dirty = true; in evergreen_cs_handle_reg()
1590 track->htile_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1592 track->htile_bo = reloc->robj; in evergreen_cs_handle_reg()
1593 track->db_dirty = true; in evergreen_cs_handle_reg()
1597 track->htile_surface = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1600 track->db_dirty = true; in evergreen_cs_handle_reg()
1739 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; in evergreen_cs_handle_reg()
1758 struct evergreen_cs_track *track = p->track; in evergreen_is_safe_reg() local
1766 if (!(track->reg_safe_bm[i] & m)) in evergreen_is_safe_reg()
1776 struct evergreen_cs_track *track; in evergreen_packet3_check() local
1784 track = (struct evergreen_cs_track *)p->track; in evergreen_packet3_check()
2023 track->indirect_draw_buffer_size = radeon_bo_size(reloc->robj); in evergreen_packet3_check()
2045 if (idx_value + size > track->indirect_draw_buffer_size) { in evergreen_packet3_check()
2047 idx_value, size, track->indirect_draw_buffer_size); in evergreen_packet3_check()
2374 TEX_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_packet3_check()
2675 struct evergreen_cs_track *track; in evergreen_cs_parse() local
2679 if (p->track == NULL) { in evergreen_cs_parse()
2681 track = kzalloc(sizeof(*track), GFP_KERNEL); in evergreen_cs_parse()
2682 if (track == NULL) in evergreen_cs_parse()
2684 evergreen_cs_track_init(track); in evergreen_cs_parse()
2687 track->reg_safe_bm = cayman_reg_safe_bm; in evergreen_cs_parse()
2690 track->reg_safe_bm = evergreen_reg_safe_bm; in evergreen_cs_parse()
2696 track->npipes = 1; in evergreen_cs_parse()
2700 track->npipes = 2; in evergreen_cs_parse()
2703 track->npipes = 4; in evergreen_cs_parse()
2706 track->npipes = 8; in evergreen_cs_parse()
2712 track->nbanks = 4; in evergreen_cs_parse()
2716 track->nbanks = 8; in evergreen_cs_parse()
2719 track->nbanks = 16; in evergreen_cs_parse()
2725 track->group_size = 256; in evergreen_cs_parse()
2729 track->group_size = 512; in evergreen_cs_parse()
2735 track->row_size = 1; in evergreen_cs_parse()
2739 track->row_size = 2; in evergreen_cs_parse()
2742 track->row_size = 4; in evergreen_cs_parse()
2746 p->track = track; in evergreen_cs_parse()
2751 kfree(p->track); in evergreen_cs_parse()
2752 p->track = NULL; in evergreen_cs_parse()
2767 kfree(p->track); in evergreen_cs_parse()
2768 p->track = NULL; in evergreen_cs_parse()
2772 kfree(p->track); in evergreen_cs_parse()
2773 p->track = NULL; in evergreen_cs_parse()
2783 kfree(p->track); in evergreen_cs_parse()
2784 p->track = NULL; in evergreen_cs_parse()