Lines Matching +full:0 +full:x10001
11 #define GPU_ID 0x00
12 #define GPU_L2_FEATURES 0x004 /* (RO) Level 2 cache features */
13 #define GPU_CORE_FEATURES 0x008 /* (RO) Shader Core Features */
14 #define GPU_TILER_FEATURES 0x00C /* (RO) Tiler Features */
15 #define GPU_MEM_FEATURES 0x010 /* (RO) Memory system features */
16 #define GROUPS_L2_COHERENT BIT(0) /* Cores groups are l2 coherent */
18 #define GPU_MMU_FEATURES 0x014 /* (RO) MMU features */
19 #define GPU_AS_PRESENT 0x018 /* (RO) Address space slots present */
20 #define GPU_JS_PRESENT 0x01C /* (RO) Job slots present */
22 #define GPU_INT_RAWSTAT 0x20
23 #define GPU_INT_CLEAR 0x24
24 #define GPU_INT_MASK 0x28
25 #define GPU_INT_STAT 0x2c
26 #define GPU_IRQ_FAULT BIT(0)
45 #define GPU_CMD 0x30
46 #define GPU_CMD_SOFT_RESET 0x01
47 #define GPU_CMD_PERFCNT_CLEAR 0x03
48 #define GPU_CMD_PERFCNT_SAMPLE 0x04
49 #define GPU_CMD_CLEAN_CACHES 0x07
50 #define GPU_CMD_CLEAN_INV_CACHES 0x08
51 #define GPU_STATUS 0x34
53 #define GPU_LATEST_FLUSH_ID 0x38
54 #define GPU_PWR_KEY 0x50 /* (WO) Power manager key register */
55 #define GPU_PWR_KEY_UNLOCK 0x2968A819
56 #define GPU_PWR_OVERRIDE0 0x54 /* (RW) Power manager override settings */
57 #define GPU_PWR_OVERRIDE1 0x58 /* (RW) Power manager override settings */
58 #define GPU_FAULT_STATUS 0x3C
59 #define GPU_FAULT_ADDRESS_LO 0x40
60 #define GPU_FAULT_ADDRESS_HI 0x44
62 #define GPU_PERFCNT_BASE_LO 0x60
63 #define GPU_PERFCNT_BASE_HI 0x64
64 #define GPU_PERFCNT_CFG 0x68
66 #define GPU_PERFCNT_CFG_MODE_OFF 0
71 #define GPU_PRFCNT_JM_EN 0x6c
72 #define GPU_PRFCNT_SHADER_EN 0x70
73 #define GPU_PRFCNT_TILER_EN 0x74
74 #define GPU_PRFCNT_MMU_L2_EN 0x7c
76 #define GPU_THREAD_MAX_THREADS 0x0A0 /* (RO) Maximum number of threads per core */
77 #define GPU_THREAD_MAX_WORKGROUP_SIZE 0x0A4 /* (RO) Maximum workgroup size */
78 #define GPU_THREAD_MAX_BARRIER_SIZE 0x0A8 /* (RO) Maximum threads waiting at a barrier */
79 #define GPU_THREAD_FEATURES 0x0AC /* (RO) Thread features */
80 #define GPU_THREAD_TLS_ALLOC 0x310 /* (RO) Number of threads per core that
83 #define GPU_TEXTURE_FEATURES(n) (0x0B0 + ((n) * 4))
84 #define GPU_JS_FEATURES(n) (0x0C0 + ((n) * 4))
86 #define GPU_SHADER_PRESENT_LO 0x100 /* (RO) Shader core present bitmap, low word */
87 #define GPU_SHADER_PRESENT_HI 0x104 /* (RO) Shader core present bitmap, high word */
88 #define GPU_TILER_PRESENT_LO 0x110 /* (RO) Tiler core present bitmap, low word */
89 #define GPU_TILER_PRESENT_HI 0x114 /* (RO) Tiler core present bitmap, high word */
91 #define GPU_L2_PRESENT_LO 0x120 /* (RO) Level 2 cache present bitmap, low word */
92 #define GPU_L2_PRESENT_HI 0x124 /* (RO) Level 2 cache present bitmap, high word */
94 #define GPU_COHERENCY_FEATURES 0x300 /* (RO) Coherency features present */
95 #define COHERENCY_ACE_LITE BIT(0)
98 #define GPU_STACK_PRESENT_LO 0xE00 /* (RO) Core stack present bitmap, low word */
99 #define GPU_STACK_PRESENT_HI 0xE04 /* (RO) Core stack present bitmap, high word */
101 #define SHADER_READY_LO 0x140 /* (RO) Shader core ready bitmap, low word */
102 #define SHADER_READY_HI 0x144 /* (RO) Shader core ready bitmap, high word */
104 #define TILER_READY_LO 0x150 /* (RO) Tiler core ready bitmap, low word */
105 #define TILER_READY_HI 0x154 /* (RO) Tiler core ready bitmap, high word */
107 #define L2_READY_LO 0x160 /* (RO) Level 2 cache ready bitmap, low word */
108 #define L2_READY_HI 0x164 /* (RO) Level 2 cache ready bitmap, high word */
110 #define STACK_READY_LO 0xE10 /* (RO) Core stack ready bitmap, low word */
111 #define STACK_READY_HI 0xE14 /* (RO) Core stack ready bitmap, high word */
114 #define SHADER_PWRON_LO 0x180 /* (WO) Shader core power on bitmap, low word */
115 #define SHADER_PWRON_HI 0x184 /* (WO) Shader core power on bitmap, high word */
117 #define TILER_PWRON_LO 0x190 /* (WO) Tiler core power on bitmap, low word */
118 #define TILER_PWRON_HI 0x194 /* (WO) Tiler core power on bitmap, high word */
120 #define L2_PWRON_LO 0x1A0 /* (WO) Level 2 cache power on bitmap, low word */
121 #define L2_PWRON_HI 0x1A4 /* (WO) Level 2 cache power on bitmap, high word */
123 #define STACK_PWRON_LO 0xE20 /* (RO) Core stack power on bitmap, low word */
124 #define STACK_PWRON_HI 0xE24 /* (RO) Core stack power on bitmap, high word */
127 #define SHADER_PWROFF_LO 0x1C0 /* (WO) Shader core power off bitmap, low word */
128 #define SHADER_PWROFF_HI 0x1C4 /* (WO) Shader core power off bitmap, high word */
130 #define TILER_PWROFF_LO 0x1D0 /* (WO) Tiler core power off bitmap, low word */
131 #define TILER_PWROFF_HI 0x1D4 /* (WO) Tiler core power off bitmap, high word */
133 #define L2_PWROFF_LO 0x1E0 /* (WO) Level 2 cache power off bitmap, low word */
134 #define L2_PWROFF_HI 0x1E4 /* (WO) Level 2 cache power off bitmap, high word */
136 #define STACK_PWROFF_LO 0xE30 /* (RO) Core stack power off bitmap, low word */
137 #define STACK_PWROFF_HI 0xE34 /* (RO) Core stack power off bitmap, high word */
140 #define SHADER_PWRTRANS_LO 0x200 /* (RO) Shader core power transition bitmap, low word */
141 #define SHADER_PWRTRANS_HI 0x204 /* (RO) Shader core power transition bitmap, high word */
143 #define TILER_PWRTRANS_LO 0x210 /* (RO) Tiler core power transition bitmap, low word */
144 #define TILER_PWRTRANS_HI 0x214 /* (RO) Tiler core power transition bitmap, high word */
146 #define L2_PWRTRANS_LO 0x220 /* (RO) Level 2 cache power transition bitmap, low word */
147 #define L2_PWRTRANS_HI 0x224 /* (RO) Level 2 cache power transition bitmap, high word */
149 #define STACK_PWRTRANS_LO 0xE40 /* (RO) Core stack power transition bitmap, low word */
150 #define STACK_PWRTRANS_HI 0xE44 /* (RO) Core stack power transition bitmap, high word */
153 #define SHADER_PWRACTIVE_LO 0x240 /* (RO) Shader core active bitmap, low word */
154 #define SHADER_PWRACTIVE_HI 0x244 /* (RO) Shader core active bitmap, high word */
156 #define TILER_PWRACTIVE_LO 0x250 /* (RO) Tiler core active bitmap, low word */
157 #define TILER_PWRACTIVE_HI 0x254 /* (RO) Tiler core active bitmap, high word */
159 #define L2_PWRACTIVE_LO 0x260 /* (RO) Level 2 cache active bitmap, low word */
160 #define L2_PWRACTIVE_HI 0x264 /* (RO) Level 2 cache active bitmap, high word */
162 #define GPU_JM_CONFIG 0xF00 /* (RW) Job Manager configuration register (Implementation specific…
163 #define GPU_SHADER_CONFIG 0xF04 /* (RW) Shader core configuration settings (Implementation specifi…
164 #define GPU_TILER_CONFIG 0xF08 /* (RW) Tiler core configuration settings (Implementation specifi…
165 #define GPU_L2_MMU_CONFIG 0xF0C /* (RW) Configuration of the L2 cache and MMU (Implementation spec…
169 #define L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY (0x1 << L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY_SHIFT)
171 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT)
172 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_OCTANT (0x1 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT)
173 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_QUARTER (0x2 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT)
174 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_HALF (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT)
177 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT)
178 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_OCTANT (0x1 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIF…
179 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_QUARTER (0x2 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHI…
180 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_HALF (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT)
183 #define L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_READS (0x7 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT)
186 #define L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_WRITES (0x7 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT)
200 #define TC_CLOCK_GATE_OVERRIDE BIT(0)
203 #define JM_TIMESTAMP_OVERRIDE BIT(0)
207 #define JM_MAX_JOB_THROTTLE_LIMIT 0x3F
210 #define JM_MAX_IDVS_GROUP_SIZE 0x3F
214 #define JOB_INT_RAWSTAT 0x1000
215 #define JOB_INT_CLEAR 0x1004
216 #define JOB_INT_MASK 0x1008
217 #define JOB_INT_STAT 0x100c
218 #define JOB_INT_JS_STATE 0x1010
219 #define JOB_INT_THROTTLE 0x1014
221 #define MK_JS_MASK(j) (0x10001 << (j))
225 #define JS_BASE 0x1800
226 #define JS_HEAD_LO(n) (JS_BASE + ((n) * 0x80) + 0x00)
227 #define JS_HEAD_HI(n) (JS_BASE + ((n) * 0x80) + 0x04)
228 #define JS_TAIL_LO(n) (JS_BASE + ((n) * 0x80) + 0x08)
229 #define JS_TAIL_HI(n) (JS_BASE + ((n) * 0x80) + 0x0c)
230 #define JS_AFFINITY_LO(n) (JS_BASE + ((n) * 0x80) + 0x10)
231 #define JS_AFFINITY_HI(n) (JS_BASE + ((n) * 0x80) + 0x14)
232 #define JS_CONFIG(n) (JS_BASE + ((n) * 0x80) + 0x18)
233 #define JS_XAFFINITY(n) (JS_BASE + ((n) * 0x80) + 0x1c)
234 #define JS_COMMAND(n) (JS_BASE + ((n) * 0x80) + 0x20)
235 #define JS_STATUS(n) (JS_BASE + ((n) * 0x80) + 0x24)
236 #define JS_HEAD_NEXT_LO(n) (JS_BASE + ((n) * 0x80) + 0x40)
237 #define JS_HEAD_NEXT_HI(n) (JS_BASE + ((n) * 0x80) + 0x44)
238 #define JS_AFFINITY_NEXT_LO(n) (JS_BASE + ((n) * 0x80) + 0x50)
239 #define JS_AFFINITY_NEXT_HI(n) (JS_BASE + ((n) * 0x80) + 0x54)
240 #define JS_CONFIG_NEXT(n) (JS_BASE + ((n) * 0x80) + 0x58)
241 #define JS_COMMAND_NEXT(n) (JS_BASE + ((n) * 0x80) + 0x60)
242 #define JS_FLUSH_ID_NEXT(n) (JS_BASE + ((n) * 0x80) + 0x70)
255 #define JS_COMMAND_NOP 0x00
256 #define JS_COMMAND_START 0x01
257 #define JS_COMMAND_SOFT_STOP 0x02 /* Gently stop processing a job chain */
258 #define JS_COMMAND_HARD_STOP 0x03 /* Rudely stop processing a job chain */
259 #define JS_COMMAND_SOFT_STOP_0 0x04 /* Execute SOFT_STOP if JOB_CHAIN_FLAG is 0 */
260 #define JS_COMMAND_HARD_STOP_0 0x05 /* Execute HARD_STOP if JOB_CHAIN_FLAG is 0 */
261 #define JS_COMMAND_SOFT_STOP_1 0x06 /* Execute SOFT_STOP if JOB_CHAIN_FLAG is 1 */
262 #define JS_COMMAND_HARD_STOP_1 0x07 /* Execute HARD_STOP if JOB_CHAIN_FLAG is 1 */
264 #define JS_STATUS_EVENT_ACTIVE 0x08
268 #define MMU_INT_RAWSTAT 0x2000
269 #define MMU_INT_CLEAR 0x2004
270 #define MMU_INT_MASK 0x2008
271 #define MMU_INT_STAT 0x200c
274 #define AS_COMMAND_NOP 0x00 /* NOP Operation */
275 #define AS_COMMAND_UPDATE 0x01 /* Broadcasts the values in AS_TRANSTAB and ASn_MEMATTR to all MMUs…
276 #define AS_COMMAND_LOCK 0x02 /* Issue a lock region command to all MMUs */
277 #define AS_COMMAND_UNLOCK 0x03 /* Issue a flush region command to all MMUs */
278 #define AS_COMMAND_FLUSH 0x04 /* Flush all L2 caches then issue a flush region command to all MMUs
280 #define AS_COMMAND_FLUSH_PT 0x04 /* Flush all L2 caches then issue a flush region command to all M…
281 #define AS_COMMAND_FLUSH_MEM 0x05 /* Wait for memory accesses to complete, flush all the L1s cache…
284 #define MMU_AS(as) (0x2400 + ((as) << 6))
286 #define AS_TRANSTAB_LO(as) (MMU_AS(as) + 0x00) /* (RW) Translation Table Base Address for address …
287 #define AS_TRANSTAB_HI(as) (MMU_AS(as) + 0x04) /* (RW) Translation Table Base Address for address …
288 #define AS_MEMATTR_LO(as) (MMU_AS(as) + 0x08) /* (RW) Memory attributes for address space n, low w…
289 #define AS_MEMATTR_HI(as) (MMU_AS(as) + 0x0C) /* (RW) Memory attributes for address space n, high …
290 #define AS_LOCKADDR_LO(as) (MMU_AS(as) + 0x10) /* (RW) Lock region address for address space n, lo…
291 #define AS_LOCKADDR_HI(as) (MMU_AS(as) + 0x14) /* (RW) Lock region address for address space n, hi…
292 #define AS_COMMAND(as) (MMU_AS(as) + 0x18) /* (WO) MMU command register for address space n */
293 #define AS_FAULTSTATUS(as) (MMU_AS(as) + 0x1C) /* (RO) MMU fault status register for address space…
294 #define AS_FAULTADDRESS_LO(as) (MMU_AS(as) + 0x20) /* (RO) Fault Address for address space n, low …
295 #define AS_FAULTADDRESS_HI(as) (MMU_AS(as) + 0x24) /* (RO) Fault Address for address space n, high…
296 #define AS_STATUS(as) (MMU_AS(as) + 0x28) /* (RO) Status flags for address space n */
298 #define AS_TRANSCFG_LO(as) (MMU_AS(as) + 0x30) /* (RW) Translation table configuration for address…
299 #define AS_TRANSCFG_HI(as) (MMU_AS(as) + 0x34) /* (RW) Translation table configuration for address…
300 #define AS_FAULTEXTRA_LO(as) (MMU_AS(as) + 0x38) /* (RO) Secondary fault address for address space…
301 #define AS_FAULTEXTRA_HI(as) (MMU_AS(as) + 0x3C) /* (RO) Secondary fault address for address space…
306 #define AS_TRANSTAB_LPAE_ADDR_SPACE_MASK 0xfffffffffffff000
307 #define AS_TRANSTAB_LPAE_ADRMODE_IDENTITY 0x2
308 #define AS_TRANSTAB_LPAE_ADRMODE_TABLE 0x3
309 #define AS_TRANSTAB_LPAE_ADRMODE_MASK 0x3
313 #define AS_STATUS_AS_ACTIVE 0x01
315 #define AS_FAULTSTATUS_ACCESS_TYPE_MASK (0x3 << 8)
316 #define AS_FAULTSTATUS_ACCESS_TYPE_ATOMIC (0x0 << 8)
317 #define AS_FAULTSTATUS_ACCESS_TYPE_EX (0x1 << 8)
318 #define AS_FAULTSTATUS_ACCESS_TYPE_READ (0x2 << 8)
319 #define AS_FAULTSTATUS_ACCESS_TYPE_WRITE (0x3 << 8)