40 	if (nvkm_rd32(device, 0x6254e8) & 0x00000002) {  in tu102_disp_init()
41 		nvkm_mask(device, 0x6254e8, 0x00000001, 0x00000000);  in tu102_disp_init()
43 			if (!(nvkm_rd32(device, 0x6254e8) & 0x00000002))  in tu102_disp_init()
45 		) < 0)  in tu102_disp_init()
50 	tmp = 0x00000021; /*XXX*/  in tu102_disp_init()
51 	nvkm_wr32(device, 0x640008, tmp);  in tu102_disp_init()
54 	for (i = 0; i < disp->sor.nr; i++) {  in tu102_disp_init()
55 		tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800));  in tu102_disp_init()
56 		nvkm_mask(device, 0x640000, 0x00000100 << i, 0x00000100 << i);  in tu102_disp_init()
57 		nvkm_wr32(device, 0x640144 + (i * 0x08), tmp);  in tu102_disp_init()
65 		tmp = nvkm_rd32(device, 0x616300 + (id * 0x800));  in tu102_disp_init()
66 		nvkm_wr32(device, 0x640048 + (id * 0x020), tmp);  in tu102_disp_init()
69 		for (j = 0; j < 5 * 4; j += 4) {  in tu102_disp_init()
70 			tmp = nvkm_rd32(device, 0x616140 + (id * 0x800) + j);  in tu102_disp_init()
71 			nvkm_wr32(device, 0x640680 + (id * 0x20) + j, tmp);  in tu102_disp_init()
76 	for (i = 0; i < disp->wndw.nr; i++) {  in tu102_disp_init()
77 		nvkm_mask(device, 0x640004, 1 << i, 1 << i);  in tu102_disp_init()
78 		for (j = 0; j < 6 * 4; j += 4) {  in tu102_disp_init()
79 			tmp = nvkm_rd32(device, 0x630100 + (i * 0x800) + j);  in tu102_disp_init()
80 			nvkm_mask(device, 0x640780 + (i * 0x20) + j, 0xffffffff, tmp);  in tu102_disp_init()
82 		nvkm_mask(device, 0x64000c, 0x00000100, 0x00000100);  in tu102_disp_init()
86 	for (i = 0; i < 3; i++) {  in tu102_disp_init()
87 		tmp = nvkm_rd32(device, 0x62e000 + (i * 0x04));  in tu102_disp_init()
88 		nvkm_wr32(device, 0x640010 + (i * 0x04), tmp);  in tu102_disp_init()
91 	nvkm_mask(device, 0x610078, 0x00000001, 0x00000001);  in tu102_disp_init()
95 	case NVKM_MEM_TARGET_VRAM: tmp = 0x00000001; break;  in tu102_disp_init()
96 	case NVKM_MEM_TARGET_NCOH: tmp = 0x00000002; break;  in tu102_disp_init()
97 	case NVKM_MEM_TARGET_HOST: tmp = 0x00000003; break;  in tu102_disp_init()
101 	nvkm_wr32(device, 0x610010, 0x00000008 | tmp);  in tu102_disp_init()
102 	nvkm_wr32(device, 0x610014, disp->inst->addr >> 16);  in tu102_disp_init()
105 	nvkm_wr32(device, 0x611cf0, 0x00000187); /* MSK. */  in tu102_disp_init()
106 	nvkm_wr32(device, 0x611db0, 0x00000187); /* EN. */  in tu102_disp_init()
109 	nvkm_wr32(device, 0x611cec, disp->head.mask << 16 |  in tu102_disp_init()
110 				    0x00000001); /* MSK. */  in tu102_disp_init()
111 	nvkm_wr32(device, 0x611dac, 0x00000000); /* EN. */  in tu102_disp_init()
114 	nvkm_wr32(device, 0x611ce8, disp->wndw.mask); /* MSK. */  in tu102_disp_init()
115 	nvkm_wr32(device, 0x611da8, 0x00000000); /* EN. */  in tu102_disp_init()
118 	nvkm_wr32(device, 0x611ce4, disp->wndw.mask); /* MSK. */  in tu102_disp_init()
119 	nvkm_wr32(device, 0x611da4, 0x00000000); /* EN. */  in tu102_disp_init()
124 		nvkm_wr32(device, 0x611cc0 + hoff, 0x00000004); /* MSK. */  in tu102_disp_init()
125 		nvkm_wr32(device, 0x611d80 + hoff, 0x00000000); /* EN. */  in tu102_disp_init()
129 	nvkm_wr32(device, 0x611cf4, 0x00000000); /* MSK. */  in tu102_disp_init()
130 	nvkm_wr32(device, 0x611db4, 0x00000000); /* EN. */  in tu102_disp_init()
131 	return 0;  in tu102_disp_init()
145 	.ramht_size = 0x2000,