32 gv100_disp_wndw_cnt(struct nvkm_disp *disp, unsigned long *pmask)  in gv100_disp_wndw_cnt()  argument
34 	struct nvkm_device *device = disp->engine.subdev.device;  in gv100_disp_wndw_cnt()
42 	struct nv50_disp *disp =  in gv100_disp_super()  local
44 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;  in gv100_disp_super()
50 	nvkm_debug(subdev, "supervisor %d: %08x\n", ffs(disp->super), stat);  in gv100_disp_super()
51 	list_for_each_entry(head, &disp->base.head, head) {  in gv100_disp_super()
56 	if (disp->super & 0x00000001) {  in gv100_disp_super()
57 		nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG);  in gv100_disp_super()
58 		nv50_disp_super_1(disp);  in gv100_disp_super()
59 		list_for_each_entry(head, &disp->base.head, head) {  in gv100_disp_super()
62 			nv50_disp_super_1_0(disp, head);  in gv100_disp_super()
65 	if (disp->super & 0x00000002) {  in gv100_disp_super()
66 		list_for_each_entry(head, &disp->base.head, head) {  in gv100_disp_super()
69 			nv50_disp_super_2_0(disp, head);  in gv100_disp_super()
71 		nvkm_outp_route(&disp->base);  in gv100_disp_super()
72 		list_for_each_entry(head, &disp->base.head, head) {  in gv100_disp_super()
75 			nv50_disp_super_2_1(disp, head);  in gv100_disp_super()
77 		list_for_each_entry(head, &disp->base.head, head) {  in gv100_disp_super()
80 			nv50_disp_super_2_2(disp, head);  in gv100_disp_super()
83 	if (disp->super & 0x00000004) {  in gv100_disp_super()
84 		list_for_each_entry(head, &disp->base.head, head) {  in gv100_disp_super()
87 			nv50_disp_super_3_0(disp, head);  in gv100_disp_super()
91 	list_for_each_entry(head, &disp->base.head, head)  in gv100_disp_super()
97 gv100_disp_exception(struct nv50_disp *disp, int chid)  in gv100_disp_exception()  argument
99 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;  in gv100_disp_exception()
125 	if (chid < ARRAY_SIZE(disp->chan) && disp->chan[chid]) {  in gv100_disp_exception()
128 			nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERROR);  in gv100_disp_exception()
139 gv100_disp_intr_ctrl_disp(struct nv50_disp *disp)  in gv100_disp_intr_ctrl_disp()  argument
141 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;  in gv100_disp_intr_ctrl_disp()
146 		disp->super = (stat & 0x00000007);  in gv100_disp_intr_ctrl_disp()
147 		queue_work(disp->wq, &disp->supervisor);  in gv100_disp_intr_ctrl_disp()
148 		nvkm_wr32(device, 0x611860, disp->super);  in gv100_disp_intr_ctrl_disp()
174 			nv50_disp_chan_uevent_send(disp, 0);  in gv100_disp_intr_ctrl_disp()
177 		for_each_set_bit(wndw, &wndws, disp->wndw.nr) {  in gv100_disp_intr_ctrl_disp()
178 			nv50_disp_chan_uevent_send(disp, 1 + wndw);  in gv100_disp_intr_ctrl_disp()
187 gv100_disp_intr_exc_other(struct nv50_disp *disp)  in gv100_disp_intr_exc_other()  argument
189 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;  in gv100_disp_intr_exc_other()
197 		gv100_disp_exception(disp, 0);  in gv100_disp_intr_exc_other()
202 		for_each_set_bit(head, &mask, disp->wndw.nr) {  in gv100_disp_intr_exc_other()
204 			gv100_disp_exception(disp, 73 + head);  in gv100_disp_intr_exc_other()
216 gv100_disp_intr_exc_winim(struct nv50_disp *disp)  in gv100_disp_intr_exc_winim()  argument
218 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;  in gv100_disp_intr_exc_winim()
223 	for_each_set_bit(wndw, &stat, disp->wndw.nr) {  in gv100_disp_intr_exc_winim()
225 		gv100_disp_exception(disp, 33 + wndw);  in gv100_disp_intr_exc_winim()
236 gv100_disp_intr_exc_win(struct nv50_disp *disp)  in gv100_disp_intr_exc_win()  argument
238 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;  in gv100_disp_intr_exc_win()
243 	for_each_set_bit(wndw, &stat, disp->wndw.nr) {  in gv100_disp_intr_exc_win()
245 		gv100_disp_exception(disp, 1 + wndw);  in gv100_disp_intr_exc_win()
256 gv100_disp_intr_head_timing(struct nv50_disp *disp, int head)  in gv100_disp_intr_head_timing()  argument
258 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;  in gv100_disp_intr_head_timing()
269 		nvkm_disp_vblank(&disp->base, head);  in gv100_disp_intr_head_timing()
281 gv100_disp_intr(struct nv50_disp *disp)  in gv100_disp_intr()  argument
283 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;  in gv100_disp_intr()
291 			gv100_disp_intr_head_timing(disp, head);  in gv100_disp_intr()
297 		gv100_disp_intr_exc_win(disp);  in gv100_disp_intr()
302 		gv100_disp_intr_exc_winim(disp);  in gv100_disp_intr()
307 		gv100_disp_intr_exc_other(disp);  in gv100_disp_intr()
312 		gv100_disp_intr_ctrl_disp(disp);  in gv100_disp_intr()
321 gv100_disp_fini(struct nv50_disp *disp)  in gv100_disp_fini()  argument
323 	struct nvkm_device *device = disp->base.engine.subdev.device;  in gv100_disp_fini()
328 gv100_disp_init(struct nv50_disp *disp)  in gv100_disp_init()  argument
330 	struct nvkm_device *device = disp->base.engine.subdev.device;  in gv100_disp_init()
350 	for (i = 0; i < disp->sor.nr; i++) {  in gv100_disp_init()
357 	list_for_each_entry(head, &disp->base.head, head) {  in gv100_disp_init()
372 	for (i = 0; i < disp->wndw.nr; i++) {  in gv100_disp_init()
389 	switch (nvkm_memory_target(disp->inst->memory)) {  in gv100_disp_init()
397 	nvkm_wr32(device, 0x610014, disp->inst->addr >> 16);  in gv100_disp_init()
404 	nvkm_wr32(device, 0x611cec, disp->head.mask << 16 |  in gv100_disp_init()
409 	nvkm_wr32(device, 0x611ce8, disp->wndw.mask); /* MSK. */  in gv100_disp_init()
413 	nvkm_wr32(device, 0x611ce4, disp->wndw.mask); /* MSK. */  in gv100_disp_init()
417 	list_for_each_entry(head, &disp->base.head, head) {  in gv100_disp_init()