Lines Matching full:pll
14 * DSI PLL 7nm - clock diagram (eg: DSI0): TODO: updated CPHY diagram
127 * Global list of private DSI PLL struct pointers. We need this for Dual DSI
128 * mode, where the master PLL's clk_ops needs access the slave's private data
132 static void dsi_pll_setup_config(struct dsi_pll_7nm *pll) in dsi_pll_setup_config() argument
134 struct dsi_pll_config *config = &pll->pll_configuration; in dsi_pll_setup_config()
136 config->ref_freq = pll->vco_ref_clk_rate; in dsi_pll_setup_config()
156 static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll) in dsi_pll_calc_dec_frac() argument
158 struct dsi_pll_config *config = &pll->pll_configuration; in dsi_pll_calc_dec_frac()
159 struct dsi_pll_regs *regs = &pll->reg_setup; in dsi_pll_calc_dec_frac()
160 u64 fref = pll->vco_ref_clk_rate; in dsi_pll_calc_dec_frac()
167 pll_freq = pll->vco_current_rate; in dsi_pll_calc_dec_frac()
180 if (pll->base.type != MSM_DSI_PHY_7NM_V4_1) in dsi_pll_calc_dec_frac()
201 static void dsi_pll_calc_ssc(struct dsi_pll_7nm *pll) in dsi_pll_calc_ssc() argument
203 struct dsi_pll_config *config = &pll->pll_configuration; in dsi_pll_calc_ssc()
204 struct dsi_pll_regs *regs = &pll->reg_setup; in dsi_pll_calc_ssc()
245 static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll) in dsi_pll_ssc_commit() argument
247 void __iomem *base = pll->mmio; in dsi_pll_ssc_commit()
248 struct dsi_pll_regs *regs = &pll->reg_setup; in dsi_pll_ssc_commit()
250 if (pll->pll_configuration.enable_ssc) { in dsi_pll_ssc_commit()
270 static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll) in dsi_pll_config_hzindep_reg() argument
272 void __iomem *base = pll->mmio; in dsi_pll_config_hzindep_reg()
275 if (pll->base.type == MSM_DSI_PHY_7NM_V4_1) { in dsi_pll_config_hzindep_reg()
276 if (pll->vco_current_rate >= 3100000000ULL) in dsi_pll_config_hzindep_reg()
279 if (pll->vco_current_rate < 1520000000ULL) in dsi_pll_config_hzindep_reg()
281 else if (pll->vco_current_rate < 2990000000ULL) in dsi_pll_config_hzindep_reg()
309 pll->base.type == MSM_DSI_PHY_7NM_V4_1 ? 0x3f : 0x22); in dsi_pll_config_hzindep_reg()
311 if (pll->base.type == MSM_DSI_PHY_7NM_V4_1) { in dsi_pll_config_hzindep_reg()
313 if (pll->slave) in dsi_pll_config_hzindep_reg()
314 pll_write(pll->slave->mmio + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); in dsi_pll_config_hzindep_reg()
318 static void dsi_pll_commit(struct dsi_pll_7nm *pll) in dsi_pll_commit() argument
320 void __iomem *base = pll->mmio; in dsi_pll_commit()
321 struct dsi_pll_regs *reg = &pll->reg_setup; in dsi_pll_commit()
337 struct msm_dsi_pll *pll = hw_clk_to_pll(hw); in dsi_pll_7nm_vco_set_rate() local
338 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); in dsi_pll_7nm_vco_set_rate()
340 DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_7nm->id, rate, in dsi_pll_7nm_vco_set_rate()
364 static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll) in dsi_pll_7nm_lock_status() argument
371 rc = readl_poll_timeout_atomic(pll->mmio + in dsi_pll_7nm_lock_status()
378 pr_err("DSI PLL(%d) lock failed, status=0x%08x\n", in dsi_pll_7nm_lock_status()
379 pll->id, status); in dsi_pll_7nm_lock_status()
384 static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll) in dsi_pll_disable_pll_bias() argument
386 u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0); in dsi_pll_disable_pll_bias()
388 pll_write(pll->mmio + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0); in dsi_pll_disable_pll_bias()
389 pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0, data & ~BIT(5)); in dsi_pll_disable_pll_bias()
393 static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll) in dsi_pll_enable_pll_bias() argument
395 u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0); in dsi_pll_enable_pll_bias()
397 pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_0, data | BIT(5)); in dsi_pll_enable_pll_bias()
398 pll_write(pll->mmio + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0xc0); in dsi_pll_enable_pll_bias()
402 static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll) in dsi_pll_disable_global_clk() argument
406 data = pll_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1); in dsi_pll_disable_global_clk()
407 pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data & ~BIT(5)); in dsi_pll_disable_global_clk()
410 static void dsi_pll_enable_global_clk(struct dsi_pll_7nm *pll) in dsi_pll_enable_global_clk() argument
414 pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x04); in dsi_pll_enable_global_clk()
416 data = pll_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1); in dsi_pll_enable_global_clk()
417 pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1, in dsi_pll_enable_global_clk()
421 static void dsi_pll_phy_dig_reset(struct dsi_pll_7nm *pll) in dsi_pll_phy_dig_reset() argument
428 pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, BIT(0)); in dsi_pll_phy_dig_reset()
430 pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, 0x0); in dsi_pll_phy_dig_reset()
436 struct msm_dsi_pll *pll = hw_clk_to_pll(hw); in dsi_pll_7nm_vco_prepare() local
437 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); in dsi_pll_7nm_vco_prepare()
444 /* Start PLL */ in dsi_pll_7nm_vco_prepare()
448 * ensure all PLL configurations are written prior to checking in dsi_pll_7nm_vco_prepare()
449 * for PLL lock. in dsi_pll_7nm_vco_prepare()
453 /* Check for PLL lock */ in dsi_pll_7nm_vco_prepare()
456 pr_err("PLL(%d) lock failed\n", pll_7nm->id); in dsi_pll_7nm_vco_prepare()
460 pll->pll_on = true; in dsi_pll_7nm_vco_prepare()
463 * assert power on reset for PHY digital in case the PLL is in dsi_pll_7nm_vco_prepare()
479 static void dsi_pll_disable_sub(struct dsi_pll_7nm *pll) in dsi_pll_disable_sub() argument
481 pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0); in dsi_pll_disable_sub()
482 dsi_pll_disable_pll_bias(pll); in dsi_pll_disable_sub()
487 struct msm_dsi_pll *pll = hw_clk_to_pll(hw); in dsi_pll_7nm_vco_unprepare() local
488 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); in dsi_pll_7nm_vco_unprepare()
491 * To avoid any stray glitches while abruptly powering down the PLL in dsi_pll_7nm_vco_unprepare()
493 * powering down the PLL in dsi_pll_7nm_vco_unprepare()
504 pll->pll_on = false; in dsi_pll_7nm_vco_unprepare()
510 struct msm_dsi_pll *pll = hw_clk_to_pll(hw); in dsi_pll_7nm_vco_recalc_rate() local
511 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); in dsi_pll_7nm_vco_recalc_rate()
541 DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x", in dsi_pll_7nm_vco_recalc_rate()
556 * PLL Callbacks
559 static void dsi_pll_7nm_save_state(struct msm_dsi_pll *pll) in dsi_pll_7nm_save_state() argument
561 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); in dsi_pll_7nm_save_state()
577 DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x", in dsi_pll_7nm_save_state()
582 static int dsi_pll_7nm_restore_state(struct msm_dsi_pll *pll) in dsi_pll_7nm_restore_state() argument
584 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); in dsi_pll_7nm_restore_state()
602 DBG("DSI PLL%d", pll_7nm->id); in dsi_pll_7nm_restore_state()
607 static int dsi_pll_7nm_set_usecase(struct msm_dsi_pll *pll, in dsi_pll_7nm_set_usecase() argument
610 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); in dsi_pll_7nm_set_usecase()
612 u32 data = 0x0; /* internal PLL */ in dsi_pll_7nm_set_usecase()
614 DBG("DSI PLL%d", pll_7nm->id); in dsi_pll_7nm_set_usecase()
623 data = 0x1; /* external PLL */ in dsi_pll_7nm_set_usecase()
629 /* set PLL src */ in dsi_pll_7nm_set_usecase()
637 static int dsi_pll_7nm_get_provider(struct msm_dsi_pll *pll, in dsi_pll_7nm_get_provider() argument
641 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); in dsi_pll_7nm_get_provider()
644 DBG("DSI PLL%d", pll_7nm->id); in dsi_pll_7nm_get_provider()
654 static void dsi_pll_7nm_destroy(struct msm_dsi_pll *pll) in dsi_pll_7nm_destroy() argument
656 struct dsi_pll_7nm *pll_7nm = to_pll_7nm(pll); in dsi_pll_7nm_destroy()
659 DBG("DSI PLL%d", pll_7nm->id); in dsi_pll_7nm_destroy()
674 * mux API. Unlike the 14nm PHY, the slave PLL doesn't need its dividers/mux
675 * state to follow the master PLL's divider/mux state. Therefore, we don't
676 * require special clock ops that also configure the slave PLL registers
850 struct msm_dsi_pll *pll; in msm_dsi_pll_7nm_init() local
857 DBG("DSI PLL%d", id); in msm_dsi_pll_7nm_init()
871 DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n"); in msm_dsi_pll_7nm_init()
877 pll = &pll_7nm->base; in msm_dsi_pll_7nm_init()
878 pll->min_rate = 1000000000UL; in msm_dsi_pll_7nm_init()
879 pll->max_rate = 3500000000UL; in msm_dsi_pll_7nm_init()
880 if (pll->type == MSM_DSI_PHY_7NM_V4_1) { in msm_dsi_pll_7nm_init()
881 pll->min_rate = 600000000UL; in msm_dsi_pll_7nm_init()
882 pll->max_rate = (unsigned long)5000000000ULL; in msm_dsi_pll_7nm_init()
884 pll->max_rate = max(pll->max_rate, 0xffffffffUL); in msm_dsi_pll_7nm_init()
886 pll->get_provider = dsi_pll_7nm_get_provider; in msm_dsi_pll_7nm_init()
887 pll->destroy = dsi_pll_7nm_destroy; in msm_dsi_pll_7nm_init()
888 pll->save_state = dsi_pll_7nm_save_state; in msm_dsi_pll_7nm_init()
889 pll->restore_state = dsi_pll_7nm_restore_state; in msm_dsi_pll_7nm_init()
890 pll->set_usecase = dsi_pll_7nm_set_usecase; in msm_dsi_pll_7nm_init()
896 DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); in msm_dsi_pll_7nm_init()
901 msm_dsi_pll_save_state(pll); in msm_dsi_pll_7nm_init()
903 return pll; in msm_dsi_pll_7nm_init()