Lines Matching full:pll
13 * DSI PLL 14nm - clock diagram (eg: DSI0):
155 * also sets the slave DSI PLL's post-dividers if in Dual DSI mode
165 struct dsi_pll_14nm *pll; member
171 * Global list of private DSI PLL struct pointers. We need this for Dual DSI
172 * mode, where the master PLL's clk_ops needs access the slave's private data
209 DBG("DSI PLL is %slocked", pll_locked ? "" : "*not* "); in pll_14nm_poll_for_ready()
214 static void dsi_pll_14nm_input_init(struct dsi_pll_14nm *pll) in dsi_pll_14nm_input_init() argument
216 pll->in.fref = pll->vco_ref_clk_rate; in dsi_pll_14nm_input_init()
217 pll->in.fdata = 0; in dsi_pll_14nm_input_init()
218 pll->in.dsiclk_sel = 1; /* Use the /2 path in Mux */ in dsi_pll_14nm_input_init()
219 pll->in.ldo_en = 0; /* disabled for now */ in dsi_pll_14nm_input_init()
222 pll->in.refclk_dbler_en = 0; in dsi_pll_14nm_input_init()
223 pll->in.vco_measure_time = 5; in dsi_pll_14nm_input_init()
224 pll->in.kvco_measure_time = 5; in dsi_pll_14nm_input_init()
225 pll->in.bandgap_timer = 4; in dsi_pll_14nm_input_init()
226 pll->in.pll_wakeup_timer = 5; in dsi_pll_14nm_input_init()
227 pll->in.plllock_cnt = 1; in dsi_pll_14nm_input_init()
228 pll->in.plllock_rng = 0; in dsi_pll_14nm_input_init()
234 pll->in.ssc_en = 1; in dsi_pll_14nm_input_init()
235 pll->in.ssc_center = 0; /* down spread by default */ in dsi_pll_14nm_input_init()
236 pll->in.ssc_spread = 5; /* PPM / 1000 */ in dsi_pll_14nm_input_init()
237 pll->in.ssc_freq = 31500; /* default recommended */ in dsi_pll_14nm_input_init()
238 pll->in.ssc_adj_period = 37; in dsi_pll_14nm_input_init()
240 pll->in.pll_ie_trim = 4; in dsi_pll_14nm_input_init()
241 pll->in.pll_ip_trim = 4; in dsi_pll_14nm_input_init()
242 pll->in.pll_cpcset_cur = 1; in dsi_pll_14nm_input_init()
243 pll->in.pll_cpmset_cur = 1; in dsi_pll_14nm_input_init()
244 pll->in.pll_icpmset = 4; in dsi_pll_14nm_input_init()
245 pll->in.pll_icpcset = 4; in dsi_pll_14nm_input_init()
246 pll->in.pll_icpmset_p = 0; in dsi_pll_14nm_input_init()
247 pll->in.pll_icpmset_m = 0; in dsi_pll_14nm_input_init()
248 pll->in.pll_icpcset_p = 0; in dsi_pll_14nm_input_init()
249 pll->in.pll_icpcset_m = 0; in dsi_pll_14nm_input_init()
250 pll->in.pll_lpf_res1 = 3; in dsi_pll_14nm_input_init()
251 pll->in.pll_lpf_cap1 = 11; in dsi_pll_14nm_input_init()
252 pll->in.pll_lpf_cap2 = 1; in dsi_pll_14nm_input_init()
253 pll->in.pll_iptat_trim = 7; in dsi_pll_14nm_input_init()
254 pll->in.pll_c3ctrl = 2; in dsi_pll_14nm_input_init()
255 pll->in.pll_r3ctrl = 1; in dsi_pll_14nm_input_init()
260 static void pll_14nm_ssc_calc(struct dsi_pll_14nm *pll) in pll_14nm_ssc_calc() argument
266 DBG("vco=%lld ref=%lld", pll->vco_current_rate, pll->vco_ref_clk_rate); in pll_14nm_ssc_calc()
268 ssc_period = pll->in.ssc_freq / 500; in pll_14nm_ssc_calc()
269 period = (u32)pll->vco_ref_clk_rate / 1000; in pll_14nm_ssc_calc()
272 pll->out.ssc_period = ssc_period; in pll_14nm_ssc_calc()
274 DBG("ssc freq=%d spread=%d period=%d", pll->in.ssc_freq, in pll_14nm_ssc_calc()
275 pll->in.ssc_spread, pll->out.ssc_period); in pll_14nm_ssc_calc()
277 step_size = (u32)pll->vco_current_rate; in pll_14nm_ssc_calc()
278 ref = pll->vco_ref_clk_rate; in pll_14nm_ssc_calc()
283 step_size *= pll->in.ssc_spread; in pll_14nm_ssc_calc()
285 step_size *= (pll->in.ssc_adj_period + 1); in pll_14nm_ssc_calc()
296 pll->out.ssc_step_size = step_size; in pll_14nm_ssc_calc()
299 static void pll_14nm_dec_frac_calc(struct dsi_pll_14nm *pll) in pll_14nm_dec_frac_calc() argument
301 struct dsi_pll_input *pin = &pll->in; in pll_14nm_dec_frac_calc()
302 struct dsi_pll_output *pout = &pll->out; in pll_14nm_dec_frac_calc()
306 u64 vco_clk_rate = pll->vco_current_rate; in pll_14nm_dec_frac_calc()
307 u64 fref = pll->vco_ref_clk_rate; in pll_14nm_dec_frac_calc()
352 static void pll_14nm_calc_vco_count(struct dsi_pll_14nm *pll) in pll_14nm_calc_vco_count() argument
354 struct dsi_pll_input *pin = &pll->in; in pll_14nm_calc_vco_count()
355 struct dsi_pll_output *pout = &pll->out; in pll_14nm_calc_vco_count()
356 u64 vco_clk_rate = pll->vco_current_rate; in pll_14nm_calc_vco_count()
357 u64 fref = pll->vco_ref_clk_rate; in pll_14nm_calc_vco_count()
391 static void pll_db_commit_ssc(struct dsi_pll_14nm *pll) in pll_db_commit_ssc() argument
393 void __iomem *base = pll->mmio; in pll_db_commit_ssc()
394 struct dsi_pll_input *pin = &pll->in; in pll_db_commit_ssc()
395 struct dsi_pll_output *pout = &pll->out; in pll_db_commit_ssc()
427 static void pll_db_commit_common(struct dsi_pll_14nm *pll, in pll_db_commit_common() argument
431 void __iomem *base = pll->mmio; in pll_db_commit_common()
434 /* confgiure the non frequency dependent pll registers */ in pll_db_commit_common()
493 /* de assert pll start and apply pll sw reset */ in pll_14nm_software_reset()
495 /* stop pll */ in pll_14nm_software_reset()
498 /* pll sw reset */ in pll_14nm_software_reset()
506 static void pll_db_commit_14nm(struct dsi_pll_14nm *pll, in pll_db_commit_14nm() argument
510 void __iomem *base = pll->mmio; in pll_db_commit_14nm()
511 void __iomem *cmn_base = pll->phy_cmn_mmio; in pll_db_commit_14nm()
514 DBG("DSI%d PLL", pll->id); in pll_db_commit_14nm()
519 pll_db_commit_common(pll, pin, pout); in pll_db_commit_14nm()
521 pll_14nm_software_reset(pll); in pll_db_commit_14nm()
526 data = 0xff; /* data, clk, pll normal operation */ in pll_db_commit_14nm()
529 /* configure the frequency dependent pll registers */ in pll_db_commit_14nm()
566 pll_db_commit_ssc(pll); in pll_db_commit_14nm()
577 struct msm_dsi_pll *pll = hw_clk_to_pll(hw); in dsi_pll_14nm_vco_set_rate() local
578 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); in dsi_pll_14nm_vco_set_rate()
582 DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_14nm->id, rate, in dsi_pll_14nm_vco_set_rate()
609 /* commit the slave DSI PLL registers if we're master. Note that we in dsi_pll_14nm_vco_set_rate()
610 * don't lock the slave PLL. We just ensure that the PLL/PHY registers in dsi_pll_14nm_vco_set_rate()
627 struct msm_dsi_pll *pll = hw_clk_to_pll(hw); in dsi_pll_14nm_vco_recalc_rate() local
628 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); in dsi_pll_14nm_vco_recalc_rate()
681 struct dsi_pll_14nm *pll_14nm = postdiv->pll; in dsi_pll_14nm_postdiv_recalc_rate()
687 DBG("DSI%d PLL parent rate=%lu", pll_14nm->id, parent_rate); in dsi_pll_14nm_postdiv_recalc_rate()
701 struct dsi_pll_14nm *pll_14nm = postdiv->pll; in dsi_pll_14nm_postdiv_round_rate()
703 DBG("DSI%d PLL parent rate=%lu", pll_14nm->id, rate); in dsi_pll_14nm_postdiv_round_rate()
714 struct dsi_pll_14nm *pll_14nm = postdiv->pll; in dsi_pll_14nm_postdiv_set_rate()
723 DBG("DSI%d PLL parent rate=%lu parent rate %lu", pll_14nm->id, rate, in dsi_pll_14nm_postdiv_set_rate()
737 /* If we're master in dual DSI mode, then the slave PLL's post-dividers in dsi_pll_14nm_postdiv_set_rate()
759 * PLL Callbacks
762 static int dsi_pll_14nm_enable_seq(struct msm_dsi_pll *pll) in dsi_pll_14nm_enable_seq() argument
764 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); in dsi_pll_14nm_enable_seq()
778 DRM_DEV_ERROR(&pll_14nm->pdev->dev, "DSI PLL lock failed\n"); in dsi_pll_14nm_enable_seq()
780 DBG("DSI PLL lock success"); in dsi_pll_14nm_enable_seq()
785 static void dsi_pll_14nm_disable_seq(struct msm_dsi_pll *pll) in dsi_pll_14nm_disable_seq() argument
787 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); in dsi_pll_14nm_disable_seq()
795 static void dsi_pll_14nm_save_state(struct msm_dsi_pll *pll) in dsi_pll_14nm_save_state() argument
797 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); in dsi_pll_14nm_save_state()
807 DBG("DSI%d PLL save state %x %x", pll_14nm->id, in dsi_pll_14nm_save_state()
810 cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw); in dsi_pll_14nm_save_state()
813 static int dsi_pll_14nm_restore_state(struct msm_dsi_pll *pll) in dsi_pll_14nm_restore_state() argument
815 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); in dsi_pll_14nm_restore_state()
821 ret = dsi_pll_14nm_vco_set_rate(&pll->clk_hw, in dsi_pll_14nm_restore_state()
831 DBG("DSI%d PLL restore state %x %x", pll_14nm->id, in dsi_pll_14nm_restore_state()
836 /* also restore post-dividers for slave DSI PLL */ in dsi_pll_14nm_restore_state()
847 static int dsi_pll_14nm_set_usecase(struct msm_dsi_pll *pll, in dsi_pll_14nm_set_usecase() argument
850 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); in dsi_pll_14nm_set_usecase()
879 static int dsi_pll_14nm_get_provider(struct msm_dsi_pll *pll, in dsi_pll_14nm_get_provider() argument
883 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); in dsi_pll_14nm_get_provider()
894 static void dsi_pll_14nm_destroy(struct msm_dsi_pll *pll) in dsi_pll_14nm_destroy() argument
896 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); in dsi_pll_14nm_destroy()
927 pll_postdiv->pll = pll_14nm; in pll_14nm_postdiv_register()
1044 struct msm_dsi_pll *pll; in msm_dsi_pll_14nm_init() local
1054 DBG("PLL%d", id); in msm_dsi_pll_14nm_init()
1068 DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n"); in msm_dsi_pll_14nm_init()
1074 pll = &pll_14nm->base; in msm_dsi_pll_14nm_init()
1075 pll->min_rate = VCO_MIN_RATE; in msm_dsi_pll_14nm_init()
1076 pll->max_rate = VCO_MAX_RATE; in msm_dsi_pll_14nm_init()
1077 pll->get_provider = dsi_pll_14nm_get_provider; in msm_dsi_pll_14nm_init()
1078 pll->destroy = dsi_pll_14nm_destroy; in msm_dsi_pll_14nm_init()
1079 pll->disable_seq = dsi_pll_14nm_disable_seq; in msm_dsi_pll_14nm_init()
1080 pll->save_state = dsi_pll_14nm_save_state; in msm_dsi_pll_14nm_init()
1081 pll->restore_state = dsi_pll_14nm_restore_state; in msm_dsi_pll_14nm_init()
1082 pll->set_usecase = dsi_pll_14nm_set_usecase; in msm_dsi_pll_14nm_init()
1086 pll->en_seq_cnt = 1; in msm_dsi_pll_14nm_init()
1087 pll->enable_seqs[0] = dsi_pll_14nm_enable_seq; in msm_dsi_pll_14nm_init()
1091 DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); in msm_dsi_pll_14nm_init()
1095 return pll; in msm_dsi_pll_14nm_init()