Lines Matching full:base
12 void __iomem *base = phy->base; in dsi_28nm_dphy_set_timing() local
14 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_0, in dsi_28nm_dphy_set_timing()
16 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_1, in dsi_28nm_dphy_set_timing()
18 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_2, in dsi_28nm_dphy_set_timing()
21 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_3, in dsi_28nm_dphy_set_timing()
23 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_4, in dsi_28nm_dphy_set_timing()
25 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_5, in dsi_28nm_dphy_set_timing()
27 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_6, in dsi_28nm_dphy_set_timing()
29 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_7, in dsi_28nm_dphy_set_timing()
31 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_8, in dsi_28nm_dphy_set_timing()
33 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_9, in dsi_28nm_dphy_set_timing()
36 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_10, in dsi_28nm_dphy_set_timing()
38 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_11, in dsi_28nm_dphy_set_timing()
44 void __iomem *base = phy->reg_base; in dsi_28nm_phy_regulator_enable_dcdc() local
46 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x0); in dsi_28nm_phy_regulator_enable_dcdc()
47 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 1); in dsi_28nm_phy_regulator_enable_dcdc()
48 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_5, 0); in dsi_28nm_phy_regulator_enable_dcdc()
49 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_3, 0); in dsi_28nm_phy_regulator_enable_dcdc()
50 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_2, 0x3); in dsi_28nm_phy_regulator_enable_dcdc()
51 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1, 0x9); in dsi_28nm_phy_regulator_enable_dcdc()
52 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x7); in dsi_28nm_phy_regulator_enable_dcdc()
53 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4, 0x20); in dsi_28nm_phy_regulator_enable_dcdc()
54 dsi_phy_write(phy->base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x00); in dsi_28nm_phy_regulator_enable_dcdc()
59 void __iomem *base = phy->reg_base; in dsi_28nm_phy_regulator_enable_ldo() local
61 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x0); in dsi_28nm_phy_regulator_enable_ldo()
62 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 0); in dsi_28nm_phy_regulator_enable_ldo()
63 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_5, 0x7); in dsi_28nm_phy_regulator_enable_ldo()
64 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_3, 0); in dsi_28nm_phy_regulator_enable_ldo()
65 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_2, 0x1); in dsi_28nm_phy_regulator_enable_ldo()
66 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1, 0x1); in dsi_28nm_phy_regulator_enable_ldo()
67 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4, 0x20); in dsi_28nm_phy_regulator_enable_ldo()
70 dsi_phy_write(phy->base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x05); in dsi_28nm_phy_regulator_enable_ldo()
72 dsi_phy_write(phy->base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x0d); in dsi_28nm_phy_regulator_enable_ldo()
94 void __iomem *base = phy->base; in dsi_28nm_phy_enable() local
104 dsi_phy_write(base + REG_DSI_28nm_PHY_STRENGTH_0, 0xff); in dsi_28nm_phy_enable()
110 dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_1, 0x00); in dsi_28nm_phy_enable()
111 dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f); in dsi_28nm_phy_enable()
113 dsi_phy_write(base + REG_DSI_28nm_PHY_STRENGTH_1, 0x6); in dsi_28nm_phy_enable()
116 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_0(i), 0); in dsi_28nm_phy_enable()
117 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_1(i), 0); in dsi_28nm_phy_enable()
118 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_2(i), 0); in dsi_28nm_phy_enable()
119 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_3(i), 0); in dsi_28nm_phy_enable()
120 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(i), 0); in dsi_28nm_phy_enable()
121 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_DATAPATH(i), 0); in dsi_28nm_phy_enable()
122 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_DEBUG_SEL(i), 0); in dsi_28nm_phy_enable()
123 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_0(i), 0x1); in dsi_28nm_phy_enable()
124 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_1(i), 0x97); in dsi_28nm_phy_enable()
127 dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_4, 0); in dsi_28nm_phy_enable()
128 dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_1, 0xc0); in dsi_28nm_phy_enable()
129 dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR0, 0x1); in dsi_28nm_phy_enable()
130 dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR1, 0xbb); in dsi_28nm_phy_enable()
132 dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f); in dsi_28nm_phy_enable()
143 dsi_phy_write(phy->base + REG_DSI_28nm_PHY_CTRL_0, 0); in dsi_28nm_phy_disable()