Lines Matching +full:timing +full:-
1 // SPDX-License-Identifier: GPL-2.0-only
11 (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
18 v = (tmax - tmin) * percent; in linear_inter()
21 return max_t(s32, min_result, v - 1); in linear_inter()
26 static void dsi_dphy_timing_calc_clk_zero(struct msm_dsi_dphy_timing *timing, in dsi_dphy_timing_calc_clk_zero() argument
33 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui; in dsi_dphy_timing_calc_clk_zero()
34 tmin = S_DIV_ROUND_UP(temp, ui) - 2; in dsi_dphy_timing_calc_clk_zero()
44 temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7; in dsi_dphy_timing_calc_clk_zero()
45 timing->clk_zero = clk_z + 8 - temp; in dsi_dphy_timing_calc_clk_zero()
48 int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing, in msm_dsi_dphy_timing_calc() argument
51 const unsigned long bit_rate = clk_req->bitclk_rate; in msm_dsi_dphy_timing_calc()
52 const unsigned long esc_rate = clk_req->escclk_rate; in msm_dsi_dphy_timing_calc()
63 return -EINVAL; in msm_dsi_dphy_timing_calc()
68 tmax = S_DIV_ROUND_UP(95 * coeff, ui) - 2; in msm_dsi_dphy_timing_calc()
69 tmin = S_DIV_ROUND_UP(38 * coeff, ui) - 2; in msm_dsi_dphy_timing_calc()
70 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, true); in msm_dsi_dphy_timing_calc()
74 timing->hs_rqst = temp; in msm_dsi_dphy_timing_calc()
76 timing->hs_rqst = max_t(s32, 0, temp - 2); in msm_dsi_dphy_timing_calc()
79 dsi_dphy_timing_calc_clk_zero(timing, ui, coeff, pcnt2); in msm_dsi_dphy_timing_calc()
81 temp = 105 * coeff + 12 * ui - 20 * coeff; in msm_dsi_dphy_timing_calc()
82 tmax = S_DIV_ROUND_UP(temp, ui) - 2; in msm_dsi_dphy_timing_calc()
83 tmin = S_DIV_ROUND_UP(60 * coeff, ui) - 2; in msm_dsi_dphy_timing_calc()
84 timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, true); in msm_dsi_dphy_timing_calc()
87 tmax = S_DIV_ROUND_UP(temp, ui) - 2; in msm_dsi_dphy_timing_calc()
89 tmin = S_DIV_ROUND_UP(temp, ui) - 2; in msm_dsi_dphy_timing_calc()
90 timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, true); in msm_dsi_dphy_timing_calc()
93 temp = ((timing->hs_prepare >> 1) + 1) * 2 * ui + 2 * ui; in msm_dsi_dphy_timing_calc()
94 temp = 145 * coeff + 10 * ui - temp; in msm_dsi_dphy_timing_calc()
95 tmin = S_DIV_ROUND_UP(temp, ui) - 2; in msm_dsi_dphy_timing_calc()
96 timing->hs_zero = linear_inter(tmax, tmin, pcnt2, 24, true); in msm_dsi_dphy_timing_calc()
98 temp = 105 * coeff + 12 * ui - 20 * coeff; in msm_dsi_dphy_timing_calc()
99 tmax = S_DIV_ROUND_UP(temp, ui) - 2; in msm_dsi_dphy_timing_calc()
101 tmin = DIV_ROUND_UP(temp, ui) - 2; in msm_dsi_dphy_timing_calc()
102 timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, true); in msm_dsi_dphy_timing_calc()
105 tmin = S_DIV_ROUND_UP(100 * coeff, ui) - 2; in msm_dsi_dphy_timing_calc()
106 timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, true); in msm_dsi_dphy_timing_calc()
109 temp = ((timing->hs_exit >> 1) + 1) * 2 * ui; in msm_dsi_dphy_timing_calc()
110 temp = 60 * coeff + 52 * ui - 24 * ui - temp; in msm_dsi_dphy_timing_calc()
111 tmin = S_DIV_ROUND_UP(temp, 8 * ui) - 1; in msm_dsi_dphy_timing_calc()
112 timing->shared_timings.clk_post = linear_inter(tmax, tmin, pcnt2, 0, in msm_dsi_dphy_timing_calc()
115 temp = ((timing->clk_prepare >> 1) + 1) * 2 * ui; in msm_dsi_dphy_timing_calc()
116 temp += ((timing->clk_zero >> 1) + 1) * 2 * ui; in msm_dsi_dphy_timing_calc()
118 tmin = S_DIV_ROUND_UP(temp, 8 * ui) - 1; in msm_dsi_dphy_timing_calc()
121 timing->shared_timings.clk_pre = temp >> 1; in msm_dsi_dphy_timing_calc()
122 timing->shared_timings.clk_pre_inc_by_2 = true; in msm_dsi_dphy_timing_calc()
124 timing->shared_timings.clk_pre = in msm_dsi_dphy_timing_calc()
126 timing->shared_timings.clk_pre_inc_by_2 = false; in msm_dsi_dphy_timing_calc()
129 timing->ta_go = 3; in msm_dsi_dphy_timing_calc()
130 timing->ta_sure = 0; in msm_dsi_dphy_timing_calc()
131 timing->ta_get = 4; in msm_dsi_dphy_timing_calc()
134 timing->shared_timings.clk_pre, timing->shared_timings.clk_post, in msm_dsi_dphy_timing_calc()
135 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero, in msm_dsi_dphy_timing_calc()
136 timing->clk_trail, timing->clk_prepare, timing->hs_exit, in msm_dsi_dphy_timing_calc()
137 timing->hs_zero, timing->hs_prepare, timing->hs_trail, in msm_dsi_dphy_timing_calc()
138 timing->hs_rqst); in msm_dsi_dphy_timing_calc()
143 int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing, in msm_dsi_dphy_timing_calc_v2() argument
146 const unsigned long bit_rate = clk_req->bitclk_rate; in msm_dsi_dphy_timing_calc_v2()
147 const unsigned long esc_rate = clk_req->escclk_rate; in msm_dsi_dphy_timing_calc_v2()
162 return -EINVAL; in msm_dsi_dphy_timing_calc_v2()
164 timing->hs_halfbyte_en = 0; in msm_dsi_dphy_timing_calc_v2()
166 timing->hs_halfbyte_en_ckln = 0; in msm_dsi_dphy_timing_calc_v2()
168 timing->hs_prep_dly_ckln = (bit_rate > 100000000) ? 0 : 3; in msm_dsi_dphy_timing_calc_v2()
169 pd_ckln = timing->hs_prep_dly_ckln; in msm_dsi_dphy_timing_calc_v2()
170 timing->hs_prep_dly = (bit_rate > 120000000) ? 0 : 1; in msm_dsi_dphy_timing_calc_v2()
171 pd = timing->hs_prep_dly; in msm_dsi_dphy_timing_calc_v2()
179 temp = S_DIV_ROUND_UP(38 * coeff - val_ckln * ui, ui_x8); in msm_dsi_dphy_timing_calc_v2()
181 temp = (95 * coeff - val_ckln * ui) / ui_x8; in msm_dsi_dphy_timing_calc_v2()
183 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false); in msm_dsi_dphy_timing_calc_v2()
185 temp = 300 * coeff - ((timing->clk_prepare << 3) + val_ckln) * ui; in msm_dsi_dphy_timing_calc_v2()
186 tmin = S_DIV_ROUND_UP(temp - 11 * ui, ui_x8) - 3; in msm_dsi_dphy_timing_calc_v2()
188 timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false); in msm_dsi_dphy_timing_calc_v2()
191 temp = 105 * coeff + 12 * ui - 20 * coeff; in msm_dsi_dphy_timing_calc_v2()
193 timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false); in msm_dsi_dphy_timing_calc_v2()
195 temp = S_DIV_ROUND_UP(40 * coeff + 4 * ui - val * ui, ui_x8); in msm_dsi_dphy_timing_calc_v2()
197 temp = (85 * coeff + 6 * ui - val * ui) / ui_x8; in msm_dsi_dphy_timing_calc_v2()
199 timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false); in msm_dsi_dphy_timing_calc_v2()
201 temp = 145 * coeff + 10 * ui - ((timing->hs_prepare << 3) + val) * ui; in msm_dsi_dphy_timing_calc_v2()
202 tmin = S_DIV_ROUND_UP(temp - 11 * ui, ui_x8) - 3; in msm_dsi_dphy_timing_calc_v2()
204 timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false); in msm_dsi_dphy_timing_calc_v2()
207 temp = 105 * coeff + 12 * ui - 20 * coeff; in msm_dsi_dphy_timing_calc_v2()
209 timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false); in msm_dsi_dphy_timing_calc_v2()
211 temp = 50 * coeff + ((hb_en << 2) - 8) * ui; in msm_dsi_dphy_timing_calc_v2()
212 timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8); in msm_dsi_dphy_timing_calc_v2()
214 tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1; in msm_dsi_dphy_timing_calc_v2()
216 timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false); in msm_dsi_dphy_timing_calc_v2()
218 temp = 50 * coeff + ((hb_en_ckln << 2) - 8) * ui; in msm_dsi_dphy_timing_calc_v2()
219 timing->hs_rqst_ckln = S_DIV_ROUND_UP(temp, ui_x8); in msm_dsi_dphy_timing_calc_v2()
221 temp = 60 * coeff + 52 * ui - 43 * ui; in msm_dsi_dphy_timing_calc_v2()
222 tmin = DIV_ROUND_UP(temp, ui_x8) - 1; in msm_dsi_dphy_timing_calc_v2()
224 timing->shared_timings.clk_post = in msm_dsi_dphy_timing_calc_v2()
227 temp = 8 * ui + ((timing->clk_prepare << 3) + val_ckln) * ui; in msm_dsi_dphy_timing_calc_v2()
228 temp += (((timing->clk_zero + 3) << 3) + 11 - (pd_ckln << 1)) * ui; in msm_dsi_dphy_timing_calc_v2()
229 temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) : in msm_dsi_dphy_timing_calc_v2()
230 (((timing->hs_rqst_ckln << 3) + 8) * ui); in msm_dsi_dphy_timing_calc_v2()
231 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1; in msm_dsi_dphy_timing_calc_v2()
235 timing->shared_timings.clk_pre = temp >> 1; in msm_dsi_dphy_timing_calc_v2()
236 timing->shared_timings.clk_pre_inc_by_2 = 1; in msm_dsi_dphy_timing_calc_v2()
238 timing->shared_timings.clk_pre = in msm_dsi_dphy_timing_calc_v2()
240 timing->shared_timings.clk_pre_inc_by_2 = 0; in msm_dsi_dphy_timing_calc_v2()
243 timing->ta_go = 3; in msm_dsi_dphy_timing_calc_v2()
244 timing->ta_sure = 0; in msm_dsi_dphy_timing_calc_v2()
245 timing->ta_get = 4; in msm_dsi_dphy_timing_calc_v2()
248 timing->shared_timings.clk_pre, timing->shared_timings.clk_post, in msm_dsi_dphy_timing_calc_v2()
249 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero, in msm_dsi_dphy_timing_calc_v2()
250 timing->clk_trail, timing->clk_prepare, timing->hs_exit, in msm_dsi_dphy_timing_calc_v2()
251 timing->hs_zero, timing->hs_prepare, timing->hs_trail, in msm_dsi_dphy_timing_calc_v2()
252 timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en, in msm_dsi_dphy_timing_calc_v2()
253 timing->hs_halfbyte_en_ckln, timing->hs_prep_dly, in msm_dsi_dphy_timing_calc_v2()
254 timing->hs_prep_dly_ckln); in msm_dsi_dphy_timing_calc_v2()
259 int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing, in msm_dsi_dphy_timing_calc_v3() argument
262 const unsigned long bit_rate = clk_req->bitclk_rate; in msm_dsi_dphy_timing_calc_v3()
263 const unsigned long esc_rate = clk_req->escclk_rate; in msm_dsi_dphy_timing_calc_v3()
277 return -EINVAL; in msm_dsi_dphy_timing_calc_v3()
279 timing->hs_halfbyte_en = 0; in msm_dsi_dphy_timing_calc_v3()
281 timing->hs_halfbyte_en_ckln = 0; in msm_dsi_dphy_timing_calc_v3()
291 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false); in msm_dsi_dphy_timing_calc_v3()
293 temp = 300 * coeff - (timing->clk_prepare << 3) * ui; in msm_dsi_dphy_timing_calc_v3()
294 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1; in msm_dsi_dphy_timing_calc_v3()
296 timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false); in msm_dsi_dphy_timing_calc_v3()
299 temp = 105 * coeff + 12 * ui - 20 * coeff; in msm_dsi_dphy_timing_calc_v3()
301 timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false); in msm_dsi_dphy_timing_calc_v3()
307 timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false); in msm_dsi_dphy_timing_calc_v3()
309 temp = 145 * coeff + 10 * ui - (timing->hs_prepare << 3) * ui; in msm_dsi_dphy_timing_calc_v3()
310 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1; in msm_dsi_dphy_timing_calc_v3()
312 timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false); in msm_dsi_dphy_timing_calc_v3()
314 tmin = DIV_ROUND_UP(60 * coeff + 4 * ui, ui_x8) - 1; in msm_dsi_dphy_timing_calc_v3()
315 temp = 105 * coeff + 12 * ui - 20 * coeff; in msm_dsi_dphy_timing_calc_v3()
316 tmax = (temp / ui_x8) - 1; in msm_dsi_dphy_timing_calc_v3()
317 timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false); in msm_dsi_dphy_timing_calc_v3()
319 temp = 50 * coeff + ((hb_en << 2) - 8) * ui; in msm_dsi_dphy_timing_calc_v3()
320 timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8); in msm_dsi_dphy_timing_calc_v3()
322 tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1; in msm_dsi_dphy_timing_calc_v3()
324 timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false); in msm_dsi_dphy_timing_calc_v3()
326 temp = 50 * coeff + ((hb_en_ckln << 2) - 8) * ui; in msm_dsi_dphy_timing_calc_v3()
327 timing->hs_rqst_ckln = S_DIV_ROUND_UP(temp, ui_x8); in msm_dsi_dphy_timing_calc_v3()
329 temp = 60 * coeff + 52 * ui - 43 * ui; in msm_dsi_dphy_timing_calc_v3()
330 tmin = DIV_ROUND_UP(temp, ui_x8) - 1; in msm_dsi_dphy_timing_calc_v3()
332 timing->shared_timings.clk_post = in msm_dsi_dphy_timing_calc_v3()
335 temp = 8 * ui + (timing->clk_prepare << 3) * ui; in msm_dsi_dphy_timing_calc_v3()
336 temp += (((timing->clk_zero + 3) << 3) + 11) * ui; in msm_dsi_dphy_timing_calc_v3()
337 temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) : in msm_dsi_dphy_timing_calc_v3()
338 (((timing->hs_rqst_ckln << 3) + 8) * ui); in msm_dsi_dphy_timing_calc_v3()
339 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1; in msm_dsi_dphy_timing_calc_v3()
343 timing->shared_timings.clk_pre = temp >> 1; in msm_dsi_dphy_timing_calc_v3()
344 timing->shared_timings.clk_pre_inc_by_2 = 1; in msm_dsi_dphy_timing_calc_v3()
346 timing->shared_timings.clk_pre = in msm_dsi_dphy_timing_calc_v3()
348 timing->shared_timings.clk_pre_inc_by_2 = 0; in msm_dsi_dphy_timing_calc_v3()
351 timing->ta_go = 3; in msm_dsi_dphy_timing_calc_v3()
352 timing->ta_sure = 0; in msm_dsi_dphy_timing_calc_v3()
353 timing->ta_get = 4; in msm_dsi_dphy_timing_calc_v3()
356 timing->shared_timings.clk_pre, timing->shared_timings.clk_post, in msm_dsi_dphy_timing_calc_v3()
357 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero, in msm_dsi_dphy_timing_calc_v3()
358 timing->clk_trail, timing->clk_prepare, timing->hs_exit, in msm_dsi_dphy_timing_calc_v3()
359 timing->hs_zero, timing->hs_prepare, timing->hs_trail, in msm_dsi_dphy_timing_calc_v3()
360 timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en, in msm_dsi_dphy_timing_calc_v3()
361 timing->hs_halfbyte_en_ckln, timing->hs_prep_dly, in msm_dsi_dphy_timing_calc_v3()
362 timing->hs_prep_dly_ckln); in msm_dsi_dphy_timing_calc_v3()
367 int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing, in msm_dsi_dphy_timing_calc_v4() argument
370 const unsigned long bit_rate = clk_req->bitclk_rate; in msm_dsi_dphy_timing_calc_v4()
371 const unsigned long esc_rate = clk_req->escclk_rate; in msm_dsi_dphy_timing_calc_v4()
386 return -EINVAL; in msm_dsi_dphy_timing_calc_v4()
402 timing->clk_prepare = linear_inter(tmax, tmin, pcnt_clk_prep, 0, false); in msm_dsi_dphy_timing_calc_v4()
404 temp = 300 * coeff - (timing->clk_prepare << 3) * ui; in msm_dsi_dphy_timing_calc_v4()
405 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1; in msm_dsi_dphy_timing_calc_v4()
407 timing->clk_zero = linear_inter(tmax, tmin, pcnt_clk_zero, 0, false); in msm_dsi_dphy_timing_calc_v4()
410 temp = 105 * coeff + 12 * ui - 20 * coeff; in msm_dsi_dphy_timing_calc_v4()
412 timing->clk_trail = linear_inter(tmax, tmin, pcnt_clk_trail, 0, false); in msm_dsi_dphy_timing_calc_v4()
418 timing->hs_prepare = linear_inter(tmax, tmin, pcnt_hs_prep, 0, false); in msm_dsi_dphy_timing_calc_v4()
420 temp = 145 * coeff + 10 * ui - (timing->hs_prepare << 3) * ui; in msm_dsi_dphy_timing_calc_v4()
421 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1; in msm_dsi_dphy_timing_calc_v4()
423 timing->hs_zero = linear_inter(tmax, tmin, pcnt_hs_zero, 0, false); in msm_dsi_dphy_timing_calc_v4()
425 tmin = DIV_ROUND_UP(60 * coeff + 4 * ui, ui_x8) - 1; in msm_dsi_dphy_timing_calc_v4()
426 temp = 105 * coeff + 12 * ui - 20 * coeff; in msm_dsi_dphy_timing_calc_v4()
427 tmax = (temp / ui_x8) - 1; in msm_dsi_dphy_timing_calc_v4()
428 timing->hs_trail = linear_inter(tmax, tmin, pcnt_hs_trail, 0, false); in msm_dsi_dphy_timing_calc_v4()
430 temp = 50 * coeff + ((hb_en << 2) - 8) * ui; in msm_dsi_dphy_timing_calc_v4()
431 timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8); in msm_dsi_dphy_timing_calc_v4()
433 tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1; in msm_dsi_dphy_timing_calc_v4()
435 timing->hs_exit = linear_inter(tmax, tmin, pcnt_hs_exit, 0, false); in msm_dsi_dphy_timing_calc_v4()
438 * = roundup((mipi_min_ns + t_hs_trail_ns)/(16*bit_clk_ns), 0) - 1 in msm_dsi_dphy_timing_calc_v4()
440 temp = 60 * coeff + 52 * ui + + (timing->hs_trail + 1) * ui_x8; in msm_dsi_dphy_timing_calc_v4()
441 tmin = DIV_ROUND_UP(temp, 16 * ui) - 1; in msm_dsi_dphy_timing_calc_v4()
443 timing->shared_timings.clk_post = linear_inter(tmax, tmin, 5, 0, false); in msm_dsi_dphy_timing_calc_v4()
448 * final = roundup(val1/val2, 0) - 1 in msm_dsi_dphy_timing_calc_v4()
450 temp = 52 * coeff + (timing->clk_prepare + timing->clk_zero + 1) * ui_x8 + 54 * coeff; in msm_dsi_dphy_timing_calc_v4()
451 tmin = DIV_ROUND_UP(temp, 16 * ui) - 1; in msm_dsi_dphy_timing_calc_v4()
453 timing->shared_timings.clk_pre = DIV_ROUND_UP((tmax - tmin) * 125, 10000) + tmin; in msm_dsi_dphy_timing_calc_v4()
456 timing->shared_timings.clk_pre, timing->shared_timings.clk_post, in msm_dsi_dphy_timing_calc_v4()
457 timing->clk_zero, timing->clk_trail, timing->clk_prepare, timing->hs_exit, in msm_dsi_dphy_timing_calc_v4()
458 timing->hs_zero, timing->hs_prepare, timing->hs_trail, timing->hs_rqst); in msm_dsi_dphy_timing_calc_v4()
466 int phy_id = phy->id; in msm_dsi_phy_set_src_pll()
472 val = dsi_phy_read(phy->base + reg); in msm_dsi_phy_set_src_pll()
474 if (phy->cfg->src_pll_truthtable[phy_id][pll_id]) in msm_dsi_phy_set_src_pll()
475 dsi_phy_write(phy->base + reg, val | bit_mask); in msm_dsi_phy_set_src_pll()
477 dsi_phy_write(phy->base + reg, val & (~bit_mask)); in msm_dsi_phy_set_src_pll()
482 struct regulator_bulk_data *s = phy->supplies; in dsi_phy_regulator_init()
483 const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs; in dsi_phy_regulator_init()
484 struct device *dev = &phy->pdev->dev; in dsi_phy_regulator_init()
485 int num = phy->cfg->reg_cfg.num; in dsi_phy_regulator_init()
493 if (ret != -EPROBE_DEFER) { in dsi_phy_regulator_init()
507 struct regulator_bulk_data *s = phy->supplies; in dsi_phy_regulator_disable()
508 const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs; in dsi_phy_regulator_disable()
509 int num = phy->cfg->reg_cfg.num; in dsi_phy_regulator_disable()
513 for (i = num - 1; i >= 0; i--) in dsi_phy_regulator_disable()
522 struct regulator_bulk_data *s = phy->supplies; in dsi_phy_regulator_enable()
523 const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs; in dsi_phy_regulator_enable()
524 struct device *dev = &phy->pdev->dev; in dsi_phy_regulator_enable()
525 int num = phy->cfg->reg_cfg.num; in dsi_phy_regulator_enable()
551 for (i--; i >= 0; i--) in dsi_phy_regulator_enable()
558 struct device *dev = &phy->pdev->dev; in dsi_phy_enable_resource()
563 ret = clk_prepare_enable(phy->ahb_clk); in dsi_phy_enable_resource()
574 clk_disable_unprepare(phy->ahb_clk); in dsi_phy_disable_resource()
575 pm_runtime_put_autosuspend(&phy->pdev->dev); in dsi_phy_disable_resource()
580 { .compatible = "qcom,dsi-phy-28nm-hpm",
582 { .compatible = "qcom,dsi-phy-28nm-hpm-fam-b",
584 { .compatible = "qcom,dsi-phy-28nm-lp",
588 { .compatible = "qcom,dsi-phy-20nm",
592 { .compatible = "qcom,dsi-phy-28nm-8960",
596 { .compatible = "qcom,dsi-phy-14nm",
598 { .compatible = "qcom,dsi-phy-14nm-660",
602 { .compatible = "qcom,dsi-phy-10nm",
604 { .compatible = "qcom,dsi-phy-10nm-8998",
608 { .compatible = "qcom,dsi-phy-7nm",
610 { .compatible = "qcom,dsi-phy-7nm-8150",
623 struct platform_device *pdev = phy->pdev; in dsi_phy_get_id()
624 const struct msm_dsi_phy_cfg *cfg = phy->cfg; in dsi_phy_get_id()
630 return -EINVAL; in dsi_phy_get_id()
632 for (i = 0; i < cfg->num_dsi_phy; i++) { in dsi_phy_get_id()
633 if (cfg->io_start[i] == res->start) in dsi_phy_get_id()
637 return -EINVAL; in dsi_phy_get_id()
642 struct platform_device *pdev = phy->pdev; in msm_dsi_phy_init_common()
645 phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator", in msm_dsi_phy_init_common()
647 if (IS_ERR(phy->reg_base)) { in msm_dsi_phy_init_common()
648 DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy regulator base\n", in msm_dsi_phy_init_common()
650 ret = -ENOMEM; in msm_dsi_phy_init_common()
661 struct device *dev = &pdev->dev; in dsi_phy_driver_probe()
667 return -ENOMEM; in dsi_phy_driver_probe()
669 match = of_match_node(dsi_phy_dt_match, dev->of_node); in dsi_phy_driver_probe()
671 return -ENODEV; in dsi_phy_driver_probe()
673 phy->cfg = match->data; in dsi_phy_driver_probe()
674 phy->pdev = pdev; in dsi_phy_driver_probe()
676 phy->id = dsi_phy_get_id(phy); in dsi_phy_driver_probe()
677 if (phy->id < 0) { in dsi_phy_driver_probe()
678 ret = phy->id; in dsi_phy_driver_probe()
684 phy->regulator_ldo_mode = of_property_read_bool(dev->of_node, in dsi_phy_driver_probe()
685 "qcom,dsi-phy-regulator-ldo-mode"); in dsi_phy_driver_probe()
687 phy->base = msm_ioremap(pdev, "dsi_phy", "DSI_PHY"); in dsi_phy_driver_probe()
688 if (IS_ERR(phy->base)) { in dsi_phy_driver_probe()
690 ret = -ENOMEM; in dsi_phy_driver_probe()
698 phy->ahb_clk = msm_clk_get(pdev, "iface"); in dsi_phy_driver_probe()
699 if (IS_ERR(phy->ahb_clk)) { in dsi_phy_driver_probe()
701 ret = PTR_ERR(phy->ahb_clk); in dsi_phy_driver_probe()
705 if (phy->cfg->ops.init) { in dsi_phy_driver_probe()
706 ret = phy->cfg->ops.init(phy); in dsi_phy_driver_probe()
718 phy->pll = msm_dsi_pll_init(pdev, phy->cfg->type, phy->id); in dsi_phy_driver_probe()
719 if (IS_ERR_OR_NULL(phy->pll)) { in dsi_phy_driver_probe()
722 __func__, PTR_ERR(phy->pll)); in dsi_phy_driver_probe()
723 phy->pll = NULL; in dsi_phy_driver_probe()
740 if (phy && phy->pll) { in dsi_phy_driver_remove()
741 msm_dsi_pll_destroy(phy->pll); in dsi_phy_driver_remove()
742 phy->pll = NULL; in dsi_phy_driver_remove()
772 struct device *dev = &phy->pdev->dev; in msm_dsi_phy_enable()
775 if (!phy || !phy->cfg->ops.enable) in msm_dsi_phy_enable()
776 return -EINVAL; in msm_dsi_phy_enable()
792 ret = phy->cfg->ops.enable(phy, src_pll_id, clk_req); in msm_dsi_phy_enable()
804 if (phy->usecase != MSM_DSI_PHY_SLAVE) { in msm_dsi_phy_enable()
805 ret = msm_dsi_pll_restore_state(phy->pll); in msm_dsi_phy_enable()
816 if (phy->cfg->ops.disable) in msm_dsi_phy_enable()
817 phy->cfg->ops.disable(phy); in msm_dsi_phy_enable()
828 if (!phy || !phy->cfg->ops.disable) in msm_dsi_phy_disable()
831 phy->cfg->ops.disable(phy); in msm_dsi_phy_disable()
840 memcpy(shared_timings, &phy->timing.shared_timings, in msm_dsi_phy_get_shared_timings()
849 return phy->pll; in msm_dsi_phy_get_pll()
856 phy->usecase = uc; in msm_dsi_phy_set_usecase()