415 static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; }  in REG_DSI_RDBK()
417 static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; }  in REG_DSI_RDBK_DATA()
731 static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }  in REG_DSI_28nm_8960_PHY_LN()
733 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }  in REG_DSI_28nm_8960_PHY_LN_CFG_0()
735 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }  in REG_DSI_28nm_8960_PHY_LN_CFG_1()
737 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }  in REG_DSI_28nm_8960_PHY_LN_CFG_2()
739 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x…  in REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH()
741 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*…  in REG_DSI_28nm_8960_PHY_LN_TEST_STR_0()
743 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*…  in REG_DSI_28nm_8960_PHY_LN_TEST_STR_1()
960 static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }  in REG_DSI_28nm_PHY_LN()
962 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }  in REG_DSI_28nm_PHY_LN_CFG_0()
964 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }  in REG_DSI_28nm_PHY_LN_CFG_1()
966 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }  in REG_DSI_28nm_PHY_LN_CFG_2()
968 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }  in REG_DSI_28nm_PHY_LN_CFG_3()
970 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }  in REG_DSI_28nm_PHY_LN_CFG_4()
972 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0…  in REG_DSI_28nm_PHY_LN_TEST_DATAPATH()
974 static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }  in REG_DSI_28nm_PHY_LN_DEBUG_SEL()
976 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }  in REG_DSI_28nm_PHY_LN_TEST_STR_0()
978 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }  in REG_DSI_28nm_PHY_LN_TEST_STR_1()
1287 static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }  in REG_DSI_20nm_PHY_LN()
1289 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }  in REG_DSI_20nm_PHY_LN_CFG_0()
1291 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }  in REG_DSI_20nm_PHY_LN_CFG_1()
1293 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }  in REG_DSI_20nm_PHY_LN_CFG_2()
1295 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }  in REG_DSI_20nm_PHY_LN_CFG_3()
1297 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }  in REG_DSI_20nm_PHY_LN_CFG_4()
1299 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0…  in REG_DSI_20nm_PHY_LN_TEST_DATAPATH()
1301 static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }  in REG_DSI_20nm_PHY_LN_DEBUG_SEL()
1303 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }  in REG_DSI_20nm_PHY_LN_TEST_STR_0()
1305 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }  in REG_DSI_20nm_PHY_LN_TEST_STR_1()
1528 static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }  in REG_DSI_14nm_PHY_LN()
1530 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }  in REG_DSI_14nm_PHY_LN_CFG0()
1538 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }  in REG_DSI_14nm_PHY_LN_CFG1()
1541 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }  in REG_DSI_14nm_PHY_LN_CFG2()
1543 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }  in REG_DSI_14nm_PHY_LN_CFG3()
1545 static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0…  in REG_DSI_14nm_PHY_LN_TEST_DATAPATH()
1547 static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; }  in REG_DSI_14nm_PHY_LN_TEST_STR()
1549 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0…  in REG_DSI_14nm_PHY_LN_TIMING_CTRL_4()
1557 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0…  in REG_DSI_14nm_PHY_LN_TIMING_CTRL_5()
1565 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0…  in REG_DSI_14nm_PHY_LN_TIMING_CTRL_6()
1573 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) { return 0x00000024 + 0x80*i0…  in REG_DSI_14nm_PHY_LN_TIMING_CTRL_7()
1581 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) { return 0x00000028 + 0x80*i0…  in REG_DSI_14nm_PHY_LN_TIMING_CTRL_8()
1589 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) { return 0x0000002c + 0x80*i0…  in REG_DSI_14nm_PHY_LN_TIMING_CTRL_9()
1603 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) { return 0x00000030 + 0x80*i…  in REG_DSI_14nm_PHY_LN_TIMING_CTRL_10()
1611 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) { return 0x00000034 + 0x80*i…  in REG_DSI_14nm_PHY_LN_TIMING_CTRL_11()
1619 static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) { return 0x00000038 + 0x80*…  in REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0()
1621 static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) { return 0x0000003c + 0x80*…  in REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1()
1623 static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { return 0x00000064 + 0x80*i0; }  in REG_DSI_14nm_PHY_LN_VREG_CNTRL()
1789 static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }  in REG_DSI_10nm_PHY_LN()
1791 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }  in REG_DSI_10nm_PHY_LN_CFG0()
1793 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }  in REG_DSI_10nm_PHY_LN_CFG1()
1795 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }  in REG_DSI_10nm_PHY_LN_CFG2()
1797 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }  in REG_DSI_10nm_PHY_LN_CFG3()
1799 static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0…  in REG_DSI_10nm_PHY_LN_TEST_DATAPATH()
1801 static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; }  in REG_DSI_10nm_PHY_LN_PIN_SWAP()
1803 static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0…  in REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL()
1805 static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*…  in REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL()
1807 static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*…  in REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL()
1809 static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0…  in REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL()
1811 static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; }  in REG_DSI_10nm_PHY_LN_LPRX_CTRL()
1813 static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x0000002c + 0x80*i0; }  in REG_DSI_10nm_PHY_LN_TX_DCTRL()
1991 static inline uint32_t REG_DSI_7nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }  in REG_DSI_7nm_PHY_LN()
1993 static inline uint32_t REG_DSI_7nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }  in REG_DSI_7nm_PHY_LN_CFG0()
1995 static inline uint32_t REG_DSI_7nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }  in REG_DSI_7nm_PHY_LN_CFG1()
1997 static inline uint32_t REG_DSI_7nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }  in REG_DSI_7nm_PHY_LN_CFG2()
1999 static inline uint32_t REG_DSI_7nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0;…  in REG_DSI_7nm_PHY_LN_TEST_DATAPATH()
2001 static inline uint32_t REG_DSI_7nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000010 + 0x80*i0; }  in REG_DSI_7nm_PHY_LN_PIN_SWAP()
2003 static inline uint32_t REG_DSI_7nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000014 + 0x80*i0; }  in REG_DSI_7nm_PHY_LN_LPRX_CTRL()
2005 static inline uint32_t REG_DSI_7nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }  in REG_DSI_7nm_PHY_LN_TX_DCTRL()