113 static inline uint32_t MDP4_VERSION_MINOR(uint32_t val)  in MDP4_VERSION_MINOR()
119 static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val)  in MDP4_VERSION_MAJOR()
141 static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val)  in MDP4_DISP_INTF_SEL_PRIM()
147 static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val)  in MDP4_DISP_INTF_SEL_SEC()
153 static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val)  in MDP4_DISP_INTF_SEL_EXT()
183 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE0()
190 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE1()
197 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE2()
204 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE3()
211 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE4()
218 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE5()
225 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE6()
232 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE7()
243 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE0()
250 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE1()
257 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE2()
264 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE3()
271 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE4()
278 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE5()
285 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE6()
292 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE7()
310 static inline uint32_t __offset_OVLP(uint32_t idx)  in __offset_OVLP()
319 static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); }  in REG_MDP4_OVLP()
321 static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); }  in REG_MDP4_OVLP_CFG()
323 static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); }  in REG_MDP4_OVLP_SIZE()
326 static inline uint32_t MDP4_OVLP_SIZE_HEIGHT(uint32_t val)  in MDP4_OVLP_SIZE_HEIGHT()
332 static inline uint32_t MDP4_OVLP_SIZE_WIDTH(uint32_t val)  in MDP4_OVLP_SIZE_WIDTH()
337 static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); }  in REG_MDP4_OVLP_BASE()
339 static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); }  in REG_MDP4_OVLP_STRIDE()
341 static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0) { return 0x00000014 + __offset_OVLP(i0); }  in REG_MDP4_OVLP_OPMODE()
343 static inline uint32_t __offset_STAGE(uint32_t idx)  in __offset_STAGE()
353 static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset…  in REG_MDP4_OVLP_STAGE()
355 static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __off…  in REG_MDP4_OVLP_STAGE_OP()
358 static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val)  in MDP4_OVLP_STAGE_OP_FG_ALPHA()
366 static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val)  in MDP4_OVLP_STAGE_OP_BG_ALPHA()
375 static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 +…  in REG_MDP4_OVLP_STAGE_FG_ALPHA()
377 static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 +…  in REG_MDP4_OVLP_STAGE_BG_ALPHA()
379 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000…  in REG_MDP4_OVLP_STAGE_TRANSP_LOW0()
381 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x0000001…  in REG_MDP4_OVLP_STAGE_TRANSP_LOW1()
383 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x000000…  in REG_MDP4_OVLP_STAGE_TRANSP_HIGH0()
385 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x000000…  in REG_MDP4_OVLP_STAGE_TRANSP_HIGH1()
387 static inline uint32_t __offset_STAGE_CO3(uint32_t idx)  in __offset_STAGE_CO3()
397 static inline uint32_t REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) { return 0x00000000 + __of…  in REG_MDP4_OVLP_STAGE_CO3()
399 static inline uint32_t REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) { return 0x00000000 + …  in REG_MDP4_OVLP_STAGE_CO3_SEL()
402 static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0) { return 0x00000180 + __offset_OVLP(i…  in REG_MDP4_OVLP_TRANSP_LOW0()
404 static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0) { return 0x00000184 + __offset_OVLP(i…  in REG_MDP4_OVLP_TRANSP_LOW1()
406 static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0) { return 0x00000188 + __offset_OVLP(…  in REG_MDP4_OVLP_TRANSP_HIGH0()
408 static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0) { return 0x0000018c + __offset_OVLP(…  in REG_MDP4_OVLP_TRANSP_HIGH1()
410 static inline uint32_t REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0) { return 0x00000200 + __offset_OVLP(i0…  in REG_MDP4_OVLP_CSC_CONFIG()
412 static inline uint32_t REG_MDP4_OVLP_CSC(uint32_t i0) { return 0x00002000 + __offset_OVLP(i0); }  in REG_MDP4_OVLP_CSC()
415 static inline uint32_t REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) { return 0x00002400 + __offse…  in REG_MDP4_OVLP_CSC_MV()
417 static inline uint32_t REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) { return 0x00002400 + __o…  in REG_MDP4_OVLP_CSC_MV_VAL()
419 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) { return 0x00002500 + __o…  in REG_MDP4_OVLP_CSC_PRE_BV()
421 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002500 +…  in REG_MDP4_OVLP_CSC_PRE_BV_VAL()
423 static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) { return 0x00002580 + __…  in REG_MDP4_OVLP_CSC_POST_BV()
425 static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002580 …  in REG_MDP4_OVLP_CSC_POST_BV_VAL()
427 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) { return 0x00002600 + __o…  in REG_MDP4_OVLP_CSC_PRE_LV()
429 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002600 +…  in REG_MDP4_OVLP_CSC_PRE_LV_VAL()
431 static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) { return 0x00002680 + __…  in REG_MDP4_OVLP_CSC_POST_LV()
433 static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002680 …  in REG_MDP4_OVLP_CSC_POST_LV_VAL()
437 static inline uint32_t REG_MDP4_LUTN(uint32_t i0) { return 0x00094800 + 0x400*i0; }  in REG_MDP4_LUTN()
439 static inline uint32_t REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 +…  in REG_MDP4_LUTN_LUT()
441 static inline uint32_t REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*…  in REG_MDP4_LUTN_LUT_VAL()
445 static inline uint32_t REG_MDP4_DMA_E_QUANT(uint32_t i0) { return 0x000b0070 + 0x4*i0; }  in REG_MDP4_DMA_E_QUANT()
447 static inline uint32_t __offset_DMA(enum mdp4_dma idx)  in __offset_DMA()
456 static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }  in REG_MDP4_DMA()
458 static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0)…  in REG_MDP4_DMA_CONFIG()
461 static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val)  in MDP4_DMA_CONFIG_G_BPC()
467 static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val)  in MDP4_DMA_CONFIG_B_BPC()
473 static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val)  in MDP4_DMA_CONFIG_R_BPC()
480 static inline uint32_t MDP4_DMA_CONFIG_PACK(uint32_t val)  in MDP4_DMA_CONFIG_PACK()
487 static inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) { return 0x00000004 + __offset_DMA(i…  in REG_MDP4_DMA_SRC_SIZE()
490 static inline uint32_t MDP4_DMA_SRC_SIZE_HEIGHT(uint32_t val)  in MDP4_DMA_SRC_SIZE_HEIGHT()
496 static inline uint32_t MDP4_DMA_SRC_SIZE_WIDTH(uint32_t val)  in MDP4_DMA_SRC_SIZE_WIDTH()
501 static inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) { return 0x00000008 + __offset_DMA(i…  in REG_MDP4_DMA_SRC_BASE()
503 static inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) { return 0x0000000c + __offset_DMA…  in REG_MDP4_DMA_SRC_STRIDE()
505 static inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) { return 0x00000010 + __offset_DMA(i…  in REG_MDP4_DMA_DST_SIZE()
508 static inline uint32_t MDP4_DMA_DST_SIZE_HEIGHT(uint32_t val)  in MDP4_DMA_DST_SIZE_HEIGHT()
514 static inline uint32_t MDP4_DMA_DST_SIZE_WIDTH(uint32_t val)  in MDP4_DMA_DST_SIZE_WIDTH()
519 static inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) { return 0x00000044 + __offset_DM…  in REG_MDP4_DMA_CURSOR_SIZE()
522 static inline uint32_t MDP4_DMA_CURSOR_SIZE_WIDTH(uint32_t val)  in MDP4_DMA_CURSOR_SIZE_WIDTH()
528 static inline uint32_t MDP4_DMA_CURSOR_SIZE_HEIGHT(uint32_t val)  in MDP4_DMA_CURSOR_SIZE_HEIGHT()
533 static inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) { return 0x00000048 + __offset_DM…  in REG_MDP4_DMA_CURSOR_BASE()
535 static inline uint32_t REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) { return 0x0000004c + __offset_DMA…  in REG_MDP4_DMA_CURSOR_POS()
538 static inline uint32_t MDP4_DMA_CURSOR_POS_X(uint32_t val)  in MDP4_DMA_CURSOR_POS_X()
544 static inline uint32_t MDP4_DMA_CURSOR_POS_Y(uint32_t val)  in MDP4_DMA_CURSOR_POS_Y()
549 static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) { return 0x00000060 + __o…  in REG_MDP4_DMA_CURSOR_BLEND_CONFIG()
553 static inline uint32_t MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(enum mdp4_cursor_format val)  in MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT()
559 static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) { return 0x00000064 + __of…  in REG_MDP4_DMA_CURSOR_BLEND_PARAM()
561 static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) { return 0x00000068 + __offse…  in REG_MDP4_DMA_BLEND_TRANS_LOW()
563 static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) { return 0x0000006c + __offs…  in REG_MDP4_DMA_BLEND_TRANS_HIGH()
565 static inline uint32_t REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) { return 0x00001004 + __offset_D…  in REG_MDP4_DMA_FETCH_CONFIG()
567 static inline uint32_t REG_MDP4_DMA_CSC(enum mdp4_dma i0) { return 0x00003000 + __offset_DMA(i0); }  in REG_MDP4_DMA_CSC()
570 static inline uint32_t REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __o…  in REG_MDP4_DMA_CSC_MV()
572 static inline uint32_t REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 +…  in REG_MDP4_DMA_CSC_MV_VAL()
574 static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 +…  in REG_MDP4_DMA_CSC_PRE_BV()
576 static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x000035…  in REG_MDP4_DMA_CSC_PRE_BV_VAL()
578 static inline uint32_t REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 …  in REG_MDP4_DMA_CSC_POST_BV()
580 static inline uint32_t REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003…  in REG_MDP4_DMA_CSC_POST_BV_VAL()
582 static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 +…  in REG_MDP4_DMA_CSC_PRE_LV()
584 static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x000036…  in REG_MDP4_DMA_CSC_PRE_LV_VAL()
586 static inline uint32_t REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 …  in REG_MDP4_DMA_CSC_POST_LV()
588 static inline uint32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003…  in REG_MDP4_DMA_CSC_POST_LV_VAL()
590 static inline uint32_t REG_MDP4_PIPE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; }  in REG_MDP4_PIPE()
592 static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; }  in REG_MDP4_PIPE_SRC_SIZE()
595 static inline uint32_t MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val)  in MDP4_PIPE_SRC_SIZE_HEIGHT()
601 static inline uint32_t MDP4_PIPE_SRC_SIZE_WIDTH(uint32_t val)  in MDP4_PIPE_SRC_SIZE_WIDTH()
606 static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) { return 0x00020004 + 0x10000*i0; }  in REG_MDP4_PIPE_SRC_XY()
609 static inline uint32_t MDP4_PIPE_SRC_XY_Y(uint32_t val)  in MDP4_PIPE_SRC_XY_Y()
615 static inline uint32_t MDP4_PIPE_SRC_XY_X(uint32_t val)  in MDP4_PIPE_SRC_XY_X()
620 static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) { return 0x00020008 + 0x10000*i0; }  in REG_MDP4_PIPE_DST_SIZE()
623 static inline uint32_t MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val)  in MDP4_PIPE_DST_SIZE_HEIGHT()
629 static inline uint32_t MDP4_PIPE_DST_SIZE_WIDTH(uint32_t val)  in MDP4_PIPE_DST_SIZE_WIDTH()
634 static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) { return 0x0002000c + 0x10000*i0; }  in REG_MDP4_PIPE_DST_XY()
637 static inline uint32_t MDP4_PIPE_DST_XY_Y(uint32_t val)  in MDP4_PIPE_DST_XY_Y()
643 static inline uint32_t MDP4_PIPE_DST_XY_X(uint32_t val)  in MDP4_PIPE_DST_XY_X()
648 static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) { return 0x00020010 + 0x10000*i0…  in REG_MDP4_PIPE_SRCP0_BASE()
650 static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) { return 0x00020014 + 0x10000*i0…  in REG_MDP4_PIPE_SRCP1_BASE()
652 static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) { return 0x00020018 + 0x10000*i0…  in REG_MDP4_PIPE_SRCP2_BASE()
654 static inline uint32_t REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0) { return 0x0002001c + 0x10000*i0…  in REG_MDP4_PIPE_SRCP3_BASE()
656 static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) { return 0x00020040 + 0x10000*…  in REG_MDP4_PIPE_SRC_STRIDE_A()
659 static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val)  in MDP4_PIPE_SRC_STRIDE_A_P0()
665 static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P1(uint32_t val)  in MDP4_PIPE_SRC_STRIDE_A_P1()
670 static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) { return 0x00020044 + 0x10000*…  in REG_MDP4_PIPE_SRC_STRIDE_B()
673 static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val)  in MDP4_PIPE_SRC_STRIDE_B_P2()
679 static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val)  in MDP4_PIPE_SRC_STRIDE_B_P3()
684 static inline uint32_t REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x1…  in REG_MDP4_PIPE_SSTILE_FRAME_SIZE()
687 static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(uint32_t val)  in MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT()
693 static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(uint32_t val)  in MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH()
698 static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0…  in REG_MDP4_PIPE_SRC_FORMAT()
701 static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)  in MDP4_PIPE_SRC_FORMAT_G_BPC()
707 static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)  in MDP4_PIPE_SRC_FORMAT_B_BPC()
713 static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)  in MDP4_PIPE_SRC_FORMAT_R_BPC()
719 static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)  in MDP4_PIPE_SRC_FORMAT_A_BPC()
726 static inline uint32_t MDP4_PIPE_SRC_FORMAT_CPP(uint32_t val)  in MDP4_PIPE_SRC_FORMAT_CPP()
733 static inline uint32_t MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)  in MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT()
741 static inline uint32_t MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(uint32_t val)  in MDP4_PIPE_SRC_FORMAT_FETCH_PLANES()
748 static inline uint32_t MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)  in MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP()
754 static inline uint32_t MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(enum mdp4_frame_format val)  in MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT()
759 static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) { return 0x00020054 + 0x10000*i0…  in REG_MDP4_PIPE_SRC_UNPACK()
762 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val)  in MDP4_PIPE_SRC_UNPACK_ELEM0()
768 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM1(uint32_t val)  in MDP4_PIPE_SRC_UNPACK_ELEM1()
774 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM2(uint32_t val)  in MDP4_PIPE_SRC_UNPACK_ELEM2()
780 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val)  in MDP4_PIPE_SRC_UNPACK_ELEM3()
785 static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) { return 0x00020058 + 0x10000*i0; }  in REG_MDP4_PIPE_OP_MODE()
790 static inline uint32_t MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(enum mdp4_scale_unit val)  in MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL()
796 static inline uint32_t MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(enum mdp4_scale_unit val)  in MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL()
810 static inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) { return 0x0002005c + 0x10000*i…  in REG_MDP4_PIPE_PHASEX_STEP()
812 static inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) { return 0x00020060 + 0x10000*i…  in REG_MDP4_PIPE_PHASEY_STEP()
814 static inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) { return 0x00021004 + 0x10000*…  in REG_MDP4_PIPE_FETCH_CONFIG()
816 static inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) { return 0x00021008 + 0x10000*i…  in REG_MDP4_PIPE_SOLID_COLOR()
818 static inline uint32_t REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) { return 0x00024000 + 0x10000*i0; }  in REG_MDP4_PIPE_CSC()
821 static inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0…  in REG_MDP4_PIPE_CSC_MV()
823 static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400…  in REG_MDP4_PIPE_CSC_MV_VAL()
825 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500…  in REG_MDP4_PIPE_CSC_PRE_BV()
827 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x0002…  in REG_MDP4_PIPE_CSC_PRE_BV_VAL()
829 static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x0002458…  in REG_MDP4_PIPE_CSC_POST_BV()
831 static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x000…  in REG_MDP4_PIPE_CSC_POST_BV_VAL()
833 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600…  in REG_MDP4_PIPE_CSC_PRE_LV()
835 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x0002…  in REG_MDP4_PIPE_CSC_PRE_LV_VAL()
837 static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x0002468…  in REG_MDP4_PIPE_CSC_POST_LV()
839 static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x000…  in REG_MDP4_PIPE_CSC_POST_LV_VAL()
848 static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PULSEW(uint32_t val)  in MDP4_LCDC_HSYNC_CTRL_PULSEW()
854 static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PERIOD(uint32_t val)  in MDP4_LCDC_HSYNC_CTRL_PERIOD()
866 static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_START(uint32_t val)  in MDP4_LCDC_DISPLAY_HCTRL_START()
872 static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_END(uint32_t val)  in MDP4_LCDC_DISPLAY_HCTRL_END()
884 static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_START(uint32_t val)  in MDP4_LCDC_ACTIVE_HCTL_START()
890 static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_END(uint32_t val)  in MDP4_LCDC_ACTIVE_HCTL_END()
905 static inline uint32_t MDP4_LCDC_UNDERFLOW_CLR_COLOR(uint32_t val)  in MDP4_LCDC_UNDERFLOW_CLR_COLOR()
938 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL(uint32_t i0) { return 0x000c2014 + 0x8*i0; }  in REG_MDP4_LCDC_LVDS_MUX_CTL()
940 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(uint32_t i0) { return 0x000c2014 + 0x8*i0;…  in REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0()
943 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0()
949 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1()
955 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2()
961 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3()
966 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(uint32_t i0) { return 0x000c2018 + 0x8*i0;…  in REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4()
969 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4()
975 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5()
981 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6()
1022 static inline uint32_t MDP4_DTV_HSYNC_CTRL_PULSEW(uint32_t val)  in MDP4_DTV_HSYNC_CTRL_PULSEW()
1028 static inline uint32_t MDP4_DTV_HSYNC_CTRL_PERIOD(uint32_t val)  in MDP4_DTV_HSYNC_CTRL_PERIOD()
1040 static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_START(uint32_t val)  in MDP4_DTV_DISPLAY_HCTRL_START()
1046 static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_END(uint32_t val)  in MDP4_DTV_DISPLAY_HCTRL_END()
1058 static inline uint32_t MDP4_DTV_ACTIVE_HCTL_START(uint32_t val)  in MDP4_DTV_ACTIVE_HCTL_START()
1064 static inline uint32_t MDP4_DTV_ACTIVE_HCTL_END(uint32_t val)  in MDP4_DTV_ACTIVE_HCTL_END()
1079 static inline uint32_t MDP4_DTV_UNDERFLOW_CLR_COLOR(uint32_t val)  in MDP4_DTV_UNDERFLOW_CLR_COLOR()
1101 static inline uint32_t MDP4_DSI_HSYNC_CTRL_PULSEW(uint32_t val)  in MDP4_DSI_HSYNC_CTRL_PULSEW()
1107 static inline uint32_t MDP4_DSI_HSYNC_CTRL_PERIOD(uint32_t val)  in MDP4_DSI_HSYNC_CTRL_PERIOD()
1119 static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_START(uint32_t val)  in MDP4_DSI_DISPLAY_HCTRL_START()
1125 static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_END(uint32_t val)  in MDP4_DSI_DISPLAY_HCTRL_END()
1137 static inline uint32_t MDP4_DSI_ACTIVE_HCTL_START(uint32_t val)  in MDP4_DSI_ACTIVE_HCTL_START()
1143 static inline uint32_t MDP4_DSI_ACTIVE_HCTL_END(uint32_t val)  in MDP4_DSI_ACTIVE_HCTL_END()
1158 static inline uint32_t MDP4_DSI_UNDERFLOW_CLR_COLOR(uint32_t val)  in MDP4_DSI_UNDERFLOW_CLR_COLOR()