50 	VG1 = 0,
60 	MIXER0 = 0,
66 	INTF_LCDC_DTV = 0,
78 	FRAME_LINEAR = 0,
84 	SCALE_FIR = 0,
90 	DMA_P = 0,
95 #define MDP4_IRQ_OVERLAY0_DONE					0x00000001
96 #define MDP4_IRQ_OVERLAY1_DONE					0x00000002
97 #define MDP4_IRQ_DMA_S_DONE					0x00000004
98 #define MDP4_IRQ_DMA_E_DONE					0x00000008
99 #define MDP4_IRQ_DMA_P_DONE					0x00000010
100 #define MDP4_IRQ_VG1_HISTOGRAM					0x00000020
101 #define MDP4_IRQ_VG2_HISTOGRAM					0x00000040
102 #define MDP4_IRQ_PRIMARY_VSYNC					0x00000080
103 #define MDP4_IRQ_PRIMARY_INTF_UDERRUN				0x00000100
104 #define MDP4_IRQ_EXTERNAL_VSYNC					0x00000200
105 #define MDP4_IRQ_EXTERNAL_INTF_UDERRUN				0x00000400
106 #define MDP4_IRQ_PRIMARY_RDPTR					0x00000800
107 #define MDP4_IRQ_DMA_P_HISTOGRAM				0x00020000
108 #define MDP4_IRQ_DMA_S_HISTOGRAM				0x04000000
109 #define MDP4_IRQ_OVERLAY2_DONE					0x40000000
110 #define REG_MDP4_VERSION					0x00000000
111 #define MDP4_VERSION_MINOR__MASK				0x00ff0000
117 #define MDP4_VERSION_MAJOR__MASK				0xff000000
124 #define REG_MDP4_OVLP0_KICK					0x00000004
126 #define REG_MDP4_OVLP1_KICK					0x00000008
128 #define REG_MDP4_OVLP2_KICK					0x000000d0
130 #define REG_MDP4_DMA_P_KICK					0x0000000c
132 #define REG_MDP4_DMA_S_KICK					0x00000010
134 #define REG_MDP4_DMA_E_KICK					0x00000014
136 #define REG_MDP4_DISP_STATUS					0x00000018
138 #define REG_MDP4_DISP_INTF_SEL					0x00000038
139 #define MDP4_DISP_INTF_SEL_PRIM__MASK				0x00000003
140 #define MDP4_DISP_INTF_SEL_PRIM__SHIFT				0
145 #define MDP4_DISP_INTF_SEL_SEC__MASK				0x0000000c
151 #define MDP4_DISP_INTF_SEL_EXT__MASK				0x00000030
157 #define MDP4_DISP_INTF_SEL_DSI_VIDEO				0x00000040
158 #define MDP4_DISP_INTF_SEL_DSI_CMD				0x00000080
160 #define REG_MDP4_RESET_STATUS					0x0000003c
162 #define REG_MDP4_READ_CNFG					0x0000004c
164 #define REG_MDP4_INTR_ENABLE					0x00000050
166 #define REG_MDP4_INTR_STATUS					0x00000054
168 #define REG_MDP4_INTR_CLEAR					0x00000058
170 #define REG_MDP4_EBI2_LCD0					0x00000060
172 #define REG_MDP4_EBI2_LCD1					0x00000064
174 #define REG_MDP4_PORTMAP_MODE					0x00000070
176 #define REG_MDP4_CS_CONTROLLER0					0x000000c0
178 #define REG_MDP4_CS_CONTROLLER1					0x000000c4
180 #define REG_MDP4_LAYERMIXER2_IN_CFG				0x000100f0
181 #define MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK			0x00000007
182 #define MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT			0
187 #define MDP4_LAYERMIXER2_IN_CFG_PIPE0_MIXER1			0x00000008
188 #define MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK			0x00000070
194 #define MDP4_LAYERMIXER2_IN_CFG_PIPE1_MIXER1			0x00000080
195 #define MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK			0x00000700
201 #define MDP4_LAYERMIXER2_IN_CFG_PIPE2_MIXER1			0x00000800
202 #define MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK			0x00007000
208 #define MDP4_LAYERMIXER2_IN_CFG_PIPE3_MIXER1			0x00008000
209 #define MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK			0x00070000
215 #define MDP4_LAYERMIXER2_IN_CFG_PIPE4_MIXER1			0x00080000
216 #define MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK			0x00700000
222 #define MDP4_LAYERMIXER2_IN_CFG_PIPE5_MIXER1			0x00800000
223 #define MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK			0x07000000
229 #define MDP4_LAYERMIXER2_IN_CFG_PIPE6_MIXER1			0x08000000
230 #define MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK			0x70000000
236 #define MDP4_LAYERMIXER2_IN_CFG_PIPE7_MIXER1			0x80000000
238 #define REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD		0x000100fc
240 #define REG_MDP4_LAYERMIXER_IN_CFG				0x00010100
241 #define MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK			0x00000007
242 #define MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT			0
247 #define MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1			0x00000008
248 #define MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK			0x00000070
254 #define MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1			0x00000080
255 #define MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK			0x00000700
261 #define MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1			0x00000800
262 #define MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK			0x00007000
268 #define MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1			0x00008000
269 #define MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK			0x00070000
275 #define MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1			0x00080000
276 #define MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK			0x00700000
282 #define MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1			0x00800000
283 #define MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK			0x07000000
289 #define MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1			0x08000000
290 #define MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK			0x70000000
296 #define MDP4_LAYERMIXER_IN_CFG_PIPE7_MIXER1			0x80000000
298 #define REG_MDP4_VG2_SRC_FORMAT					0x00030050
300 #define REG_MDP4_VG2_CONST_COLOR				0x00031008
302 #define REG_MDP4_OVERLAY_FLUSH					0x00018000
303 #define MDP4_OVERLAY_FLUSH_OVLP0				0x00000001
304 #define MDP4_OVERLAY_FLUSH_OVLP1				0x00000002
305 #define MDP4_OVERLAY_FLUSH_VG1					0x00000004
306 #define MDP4_OVERLAY_FLUSH_VG2					0x00000008
307 #define MDP4_OVERLAY_FLUSH_RGB1					0x00000010
308 #define MDP4_OVERLAY_FLUSH_RGB2					0x00000020
313 		case 0: return 0x00010000;  in __offset_OVLP()
314 		case 1: return 0x00018000;  in __offset_OVLP()
315 		case 2: return 0x00088000;  in __offset_OVLP()
319 static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); }  in REG_MDP4_OVLP()
321 static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); }  in REG_MDP4_OVLP_CFG()
323 static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); }  in REG_MDP4_OVLP_SIZE()
324 #define MDP4_OVLP_SIZE_HEIGHT__MASK				0xffff0000
330 #define MDP4_OVLP_SIZE_WIDTH__MASK				0x0000ffff
331 #define MDP4_OVLP_SIZE_WIDTH__SHIFT				0
337 static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); }  in REG_MDP4_OVLP_BASE()
339 static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); }  in REG_MDP4_OVLP_STRIDE()
341 static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0) { return 0x00000014 + __offset_OVLP(i0); }  in REG_MDP4_OVLP_OPMODE()
346 		case 0: return 0x00000104;  in __offset_STAGE()
347 		case 1: return 0x00000124;  in __offset_STAGE()
348 		case 2: return 0x00000144;  in __offset_STAGE()
349 		case 3: return 0x00000160;  in __offset_STAGE()
353 static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset…  in REG_MDP4_OVLP_STAGE()
355 static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __off…  in REG_MDP4_OVLP_STAGE_OP()
356 #define MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK			0x00000003
357 #define MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT			0
362 #define MDP4_OVLP_STAGE_OP_FG_INV_ALPHA				0x00000004
363 #define MDP4_OVLP_STAGE_OP_FG_MOD_ALPHA				0x00000008
364 #define MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK			0x00000030
370 #define MDP4_OVLP_STAGE_OP_BG_INV_ALPHA				0x00000040
371 #define MDP4_OVLP_STAGE_OP_BG_MOD_ALPHA				0x00000080
372 #define MDP4_OVLP_STAGE_OP_FG_TRANSP				0x00000100
373 #define MDP4_OVLP_STAGE_OP_BG_TRANSP				0x00000200
375 static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 +…  in REG_MDP4_OVLP_STAGE_FG_ALPHA()
377 static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 +…  in REG_MDP4_OVLP_STAGE_BG_ALPHA()
379 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000…  in REG_MDP4_OVLP_STAGE_TRANSP_LOW0()
381 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x0000001…  in REG_MDP4_OVLP_STAGE_TRANSP_LOW1()
383 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x000000…  in REG_MDP4_OVLP_STAGE_TRANSP_HIGH0()
385 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x000000…  in REG_MDP4_OVLP_STAGE_TRANSP_HIGH1()
390 		case 0: return 0x00001004;  in __offset_STAGE_CO3()
391 		case 1: return 0x00001404;  in __offset_STAGE_CO3()
392 		case 2: return 0x00001804;  in __offset_STAGE_CO3()
393 		case 3: return 0x00001b84;  in __offset_STAGE_CO3()
397 static inline uint32_t REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) { return 0x00000000 + __of…  in REG_MDP4_OVLP_STAGE_CO3()
399 static inline uint32_t REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) { return 0x00000000 + …  in REG_MDP4_OVLP_STAGE_CO3_SEL()
400 #define MDP4_OVLP_STAGE_CO3_SEL_FG_ALPHA			0x00000001
402 static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0) { return 0x00000180 + __offset_OVLP(i…  in REG_MDP4_OVLP_TRANSP_LOW0()
404 static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0) { return 0x00000184 + __offset_OVLP(i…  in REG_MDP4_OVLP_TRANSP_LOW1()
406 static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0) { return 0x00000188 + __offset_OVLP(…  in REG_MDP4_OVLP_TRANSP_HIGH0()
408 static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0) { return 0x0000018c + __offset_OVLP(…  in REG_MDP4_OVLP_TRANSP_HIGH1()
410 static inline uint32_t REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0) { return 0x00000200 + __offset_OVLP(i0…  in REG_MDP4_OVLP_CSC_CONFIG()
412 static inline uint32_t REG_MDP4_OVLP_CSC(uint32_t i0) { return 0x00002000 + __offset_OVLP(i0); }  in REG_MDP4_OVLP_CSC()
415 …_t REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1…  in REG_MDP4_OVLP_CSC_MV()
417 …EG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1…  in REG_MDP4_OVLP_CSC_MV_VAL()
419 …EG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1…  in REG_MDP4_OVLP_CSC_PRE_BV()
421 …DP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1…  in REG_MDP4_OVLP_CSC_PRE_BV_VAL()
423 …G_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1…  in REG_MDP4_OVLP_CSC_POST_BV()
425 …P4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1…  in REG_MDP4_OVLP_CSC_POST_BV_VAL()
427 …EG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1…  in REG_MDP4_OVLP_CSC_PRE_LV()
429 …DP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1…  in REG_MDP4_OVLP_CSC_PRE_LV_VAL()
431 …G_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1…  in REG_MDP4_OVLP_CSC_POST_LV()
433 …P4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1…  in REG_MDP4_OVLP_CSC_POST_LV_VAL()
435 #define REG_MDP4_DMA_P_OP_MODE					0x00090070
437 static inline uint32_t REG_MDP4_LUTN(uint32_t i0) { return 0x00094800 + 0x400*i0; }  in REG_MDP4_LUTN()
439 …ine uint32_t REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; }  in REG_MDP4_LUTN_LUT()
441 …uint32_t REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; }  in REG_MDP4_LUTN_LUT_VAL()
443 #define REG_MDP4_DMA_S_OP_MODE					0x000a0028
445 static inline uint32_t REG_MDP4_DMA_E_QUANT(uint32_t i0) { return 0x000b0070 + 0x4*i0; }  in REG_MDP4_DMA_E_QUANT()
450 		case DMA_P: return 0x00090000;  in __offset_DMA()
451 		case DMA_S: return 0x000a0000;  in __offset_DMA()
452 		case DMA_E: return 0x000b0000;  in __offset_DMA()
456 static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }  in REG_MDP4_DMA()
458 static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0)…  in REG_MDP4_DMA_CONFIG()
459 #define MDP4_DMA_CONFIG_G_BPC__MASK				0x00000003
460 #define MDP4_DMA_CONFIG_G_BPC__SHIFT				0
465 #define MDP4_DMA_CONFIG_B_BPC__MASK				0x0000000c
471 #define MDP4_DMA_CONFIG_R_BPC__MASK				0x00000030
477 #define MDP4_DMA_CONFIG_PACK_ALIGN_MSB				0x00000080
478 #define MDP4_DMA_CONFIG_PACK__MASK				0x0000ff00
484 #define MDP4_DMA_CONFIG_DEFLKR_EN				0x01000000
485 #define MDP4_DMA_CONFIG_DITHER_EN				0x01000000
487 static inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) { return 0x00000004 + __offset_DMA(i…  in REG_MDP4_DMA_SRC_SIZE()
488 #define MDP4_DMA_SRC_SIZE_HEIGHT__MASK				0xffff0000
494 #define MDP4_DMA_SRC_SIZE_WIDTH__MASK				0x0000ffff
495 #define MDP4_DMA_SRC_SIZE_WIDTH__SHIFT				0
501 static inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) { return 0x00000008 + __offset_DMA(i…  in REG_MDP4_DMA_SRC_BASE()
503 static inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) { return 0x0000000c + __offset_DMA…  in REG_MDP4_DMA_SRC_STRIDE()
505 static inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) { return 0x00000010 + __offset_DMA(i…  in REG_MDP4_DMA_DST_SIZE()
506 #define MDP4_DMA_DST_SIZE_HEIGHT__MASK				0xffff0000
512 #define MDP4_DMA_DST_SIZE_WIDTH__MASK				0x0000ffff
513 #define MDP4_DMA_DST_SIZE_WIDTH__SHIFT				0
519 static inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) { return 0x00000044 + __offset_DM…  in REG_MDP4_DMA_CURSOR_SIZE()
520 #define MDP4_DMA_CURSOR_SIZE_WIDTH__MASK			0x0000007f
521 #define MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT			0
526 #define MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK			0x007f0000
533 static inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) { return 0x00000048 + __offset_DM…  in REG_MDP4_DMA_CURSOR_BASE()
535 static inline uint32_t REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) { return 0x0000004c + __offset_DMA…  in REG_MDP4_DMA_CURSOR_POS()
536 #define MDP4_DMA_CURSOR_POS_X__MASK				0x0000ffff
537 #define MDP4_DMA_CURSOR_POS_X__SHIFT				0
542 #define MDP4_DMA_CURSOR_POS_Y__MASK				0xffff0000
549 static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) { return 0x00000060 + __o…  in REG_MDP4_DMA_CURSOR_BLEND_CONFIG()
550 #define MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN			0x00000001
551 #define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK		0x00000006
557 #define MDP4_DMA_CURSOR_BLEND_CONFIG_TRANSP_EN			0x00000008
559 static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) { return 0x00000064 + __of…  in REG_MDP4_DMA_CURSOR_BLEND_PARAM()
561 static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) { return 0x00000068 + __offse…  in REG_MDP4_DMA_BLEND_TRANS_LOW()
563 static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) { return 0x0000006c + __offs…  in REG_MDP4_DMA_BLEND_TRANS_HIGH()
565 static inline uint32_t REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) { return 0x00001004 + __offset_D…  in REG_MDP4_DMA_FETCH_CONFIG()
567 static inline uint32_t REG_MDP4_DMA_CSC(enum mdp4_dma i0) { return 0x00003000 + __offset_DMA(i0); }  in REG_MDP4_DMA_CSC()
570 …REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1…  in REG_MDP4_DMA_CSC_MV()
572 …MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1…  in REG_MDP4_DMA_CSC_MV_VAL()
574 …MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1…  in REG_MDP4_DMA_CSC_PRE_BV()
576 …_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1…  in REG_MDP4_DMA_CSC_PRE_BV_VAL()
578 …DP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1…  in REG_MDP4_DMA_CSC_POST_BV()
580 …DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1…  in REG_MDP4_DMA_CSC_POST_BV_VAL()
582 …MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1…  in REG_MDP4_DMA_CSC_PRE_LV()
584 …_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1…  in REG_MDP4_DMA_CSC_PRE_LV_VAL()
586 …DP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1…  in REG_MDP4_DMA_CSC_POST_LV()
588 …DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1…  in REG_MDP4_DMA_CSC_POST_LV_VAL()
590 static inline uint32_t REG_MDP4_PIPE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; }  in REG_MDP4_PIPE()
592 static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; }  in REG_MDP4_PIPE_SRC_SIZE()
593 #define MDP4_PIPE_SRC_SIZE_HEIGHT__MASK				0xffff0000
599 #define MDP4_PIPE_SRC_SIZE_WIDTH__MASK				0x0000ffff
600 #define MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT				0
606 static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) { return 0x00020004 + 0x10000*i0; }  in REG_MDP4_PIPE_SRC_XY()
607 #define MDP4_PIPE_SRC_XY_Y__MASK				0xffff0000
613 #define MDP4_PIPE_SRC_XY_X__MASK				0x0000ffff
614 #define MDP4_PIPE_SRC_XY_X__SHIFT				0
620 static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) { return 0x00020008 + 0x10000*i0; }  in REG_MDP4_PIPE_DST_SIZE()
621 #define MDP4_PIPE_DST_SIZE_HEIGHT__MASK				0xffff0000
627 #define MDP4_PIPE_DST_SIZE_WIDTH__MASK				0x0000ffff
628 #define MDP4_PIPE_DST_SIZE_WIDTH__SHIFT				0
634 static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) { return 0x0002000c + 0x10000*i0; }  in REG_MDP4_PIPE_DST_XY()
635 #define MDP4_PIPE_DST_XY_Y__MASK				0xffff0000
641 #define MDP4_PIPE_DST_XY_X__MASK				0x0000ffff
642 #define MDP4_PIPE_DST_XY_X__SHIFT				0
648 static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) { return 0x00020010 + 0x10000*i0…  in REG_MDP4_PIPE_SRCP0_BASE()
650 static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) { return 0x00020014 + 0x10000*i0…  in REG_MDP4_PIPE_SRCP1_BASE()
652 static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) { return 0x00020018 + 0x10000*i0…  in REG_MDP4_PIPE_SRCP2_BASE()
654 static inline uint32_t REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0) { return 0x0002001c + 0x10000*i0…  in REG_MDP4_PIPE_SRCP3_BASE()
656 static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) { return 0x00020040 + 0x10000*…  in REG_MDP4_PIPE_SRC_STRIDE_A()
657 #define MDP4_PIPE_SRC_STRIDE_A_P0__MASK				0x0000ffff
658 #define MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT			0
663 #define MDP4_PIPE_SRC_STRIDE_A_P1__MASK				0xffff0000
670 static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) { return 0x00020044 + 0x10000*…  in REG_MDP4_PIPE_SRC_STRIDE_B()
671 #define MDP4_PIPE_SRC_STRIDE_B_P2__MASK				0x0000ffff
672 #define MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT			0
677 #define MDP4_PIPE_SRC_STRIDE_B_P3__MASK				0xffff0000
684 static inline uint32_t REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x1…  in REG_MDP4_PIPE_SSTILE_FRAME_SIZE()
685 #define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK		0xffff0000
691 #define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK			0x0000ffff
692 #define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT		0
698 static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0…  in REG_MDP4_PIPE_SRC_FORMAT()
699 #define MDP4_PIPE_SRC_FORMAT_G_BPC__MASK			0x00000003
700 #define MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT			0
705 #define MDP4_PIPE_SRC_FORMAT_B_BPC__MASK			0x0000000c
711 #define MDP4_PIPE_SRC_FORMAT_R_BPC__MASK			0x00000030
717 #define MDP4_PIPE_SRC_FORMAT_A_BPC__MASK			0x000000c0
723 #define MDP4_PIPE_SRC_FORMAT_ALPHA_ENABLE			0x00000100
724 #define MDP4_PIPE_SRC_FORMAT_CPP__MASK				0x00000600
730 #define MDP4_PIPE_SRC_FORMAT_ROTATED_90				0x00001000
731 #define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK			0x00006000
737 #define MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT			0x00020000
738 #define MDP4_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB			0x00040000
739 #define MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MASK			0x00180000
745 #define MDP4_PIPE_SRC_FORMAT_SOLID_FILL				0x00400000
746 #define MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK			0x0c000000
752 #define MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MASK			0x60000000
759 static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) { return 0x00020054 + 0x10000*i0…  in REG_MDP4_PIPE_SRC_UNPACK()
760 #define MDP4_PIPE_SRC_UNPACK_ELEM0__MASK			0x000000ff
761 #define MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT			0
766 #define MDP4_PIPE_SRC_UNPACK_ELEM1__MASK			0x0000ff00
772 #define MDP4_PIPE_SRC_UNPACK_ELEM2__MASK			0x00ff0000
778 #define MDP4_PIPE_SRC_UNPACK_ELEM3__MASK			0xff000000
785 static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) { return 0x00020058 + 0x10000*i0; }  in REG_MDP4_PIPE_OP_MODE()
786 #define MDP4_PIPE_OP_MODE_SCALEX_EN				0x00000001
787 #define MDP4_PIPE_OP_MODE_SCALEY_EN				0x00000002
788 #define MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MASK			0x0000000c
794 #define MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MASK			0x00000030
800 #define MDP4_PIPE_OP_MODE_SRC_YCBCR				0x00000200
801 #define MDP4_PIPE_OP_MODE_DST_YCBCR				0x00000400
802 #define MDP4_PIPE_OP_MODE_CSC_EN				0x00000800
803 #define MDP4_PIPE_OP_MODE_FLIP_LR				0x00002000
804 #define MDP4_PIPE_OP_MODE_FLIP_UD				0x00004000
805 #define MDP4_PIPE_OP_MODE_DITHER_EN				0x00008000
806 #define MDP4_PIPE_OP_MODE_IGC_LUT_EN				0x00010000
807 #define MDP4_PIPE_OP_MODE_DEINT_EN				0x00040000
808 #define MDP4_PIPE_OP_MODE_DEINT_ODD_REF				0x00080000
810 static inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) { return 0x0002005c + 0x10000*i…  in REG_MDP4_PIPE_PHASEX_STEP()
812 static inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) { return 0x00020060 + 0x10000*i…  in REG_MDP4_PIPE_PHASEY_STEP()
814 static inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) { return 0x00021004 + 0x10000*…  in REG_MDP4_PIPE_FETCH_CONFIG()
816 static inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) { return 0x00021008 + 0x10000*i…  in REG_MDP4_PIPE_SOLID_COLOR()
818 static inline uint32_t REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) { return 0x00024000 + 0x10000*i0; }  in REG_MDP4_PIPE_CSC()
821 …t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; }  in REG_MDP4_PIPE_CSC_MV()
823 …G_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; }  in REG_MDP4_PIPE_CSC_MV_VAL()
825 …G_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; }  in REG_MDP4_PIPE_CSC_PRE_BV()
827 …P4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; }  in REG_MDP4_PIPE_CSC_PRE_BV_VAL()
829 …_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; }  in REG_MDP4_PIPE_CSC_POST_BV()
831 …4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; }  in REG_MDP4_PIPE_CSC_POST_BV_VAL()
833 …G_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; }  in REG_MDP4_PIPE_CSC_PRE_LV()
835 …P4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; }  in REG_MDP4_PIPE_CSC_PRE_LV_VAL()
837 …_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; }  in REG_MDP4_PIPE_CSC_POST_LV()
839 …4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; }  in REG_MDP4_PIPE_CSC_POST_LV_VAL()
841 #define REG_MDP4_LCDC						0x000c0000
843 #define REG_MDP4_LCDC_ENABLE					0x000c0000
845 #define REG_MDP4_LCDC_HSYNC_CTRL				0x000c0004
846 #define MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK			0x0000ffff
847 #define MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT			0
852 #define MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK			0xffff0000
859 #define REG_MDP4_LCDC_VSYNC_PERIOD				0x000c0008
861 #define REG_MDP4_LCDC_VSYNC_LEN					0x000c000c
863 #define REG_MDP4_LCDC_DISPLAY_HCTRL				0x000c0010
864 #define MDP4_LCDC_DISPLAY_HCTRL_START__MASK			0x0000ffff
865 #define MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT			0
870 #define MDP4_LCDC_DISPLAY_HCTRL_END__MASK			0xffff0000
877 #define REG_MDP4_LCDC_DISPLAY_VSTART				0x000c0014
879 #define REG_MDP4_LCDC_DISPLAY_VEND				0x000c0018
881 #define REG_MDP4_LCDC_ACTIVE_HCTL				0x000c001c
882 #define MDP4_LCDC_ACTIVE_HCTL_START__MASK			0x00007fff
883 #define MDP4_LCDC_ACTIVE_HCTL_START__SHIFT			0
888 #define MDP4_LCDC_ACTIVE_HCTL_END__MASK				0x7fff0000
894 #define MDP4_LCDC_ACTIVE_HCTL_ACTIVE_START_X			0x80000000
896 #define REG_MDP4_LCDC_ACTIVE_VSTART				0x000c0020
898 #define REG_MDP4_LCDC_ACTIVE_VEND				0x000c0024
900 #define REG_MDP4_LCDC_BORDER_CLR				0x000c0028
902 #define REG_MDP4_LCDC_UNDERFLOW_CLR				0x000c002c
903 #define MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK			0x00ffffff
904 #define MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT			0
909 #define MDP4_LCDC_UNDERFLOW_CLR_ENABLE_RECOVERY			0x80000000
911 #define REG_MDP4_LCDC_HSYNC_SKEW				0x000c0030
913 #define REG_MDP4_LCDC_TEST_CNTL					0x000c0034
915 #define REG_MDP4_LCDC_CTRL_POLARITY				0x000c0038
916 #define MDP4_LCDC_CTRL_POLARITY_HSYNC_LOW			0x00000001
917 #define MDP4_LCDC_CTRL_POLARITY_VSYNC_LOW			0x00000002
918 #define MDP4_LCDC_CTRL_POLARITY_DATA_EN_LOW			0x00000004
920 #define REG_MDP4_LCDC_LVDS_INTF_CTL				0x000c2000
921 #define MDP4_LCDC_LVDS_INTF_CTL_MODE_SEL			0x00000004
922 #define MDP4_LCDC_LVDS_INTF_CTL_RGB_OUT				0x00000008
923 #define MDP4_LCDC_LVDS_INTF_CTL_CH_SWAP				0x00000010
924 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_RES_BIT			0x00000020
925 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_RES_BIT			0x00000040
926 #define MDP4_LCDC_LVDS_INTF_CTL_ENABLE				0x00000080
927 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE0_EN		0x00000100
928 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE1_EN		0x00000200
929 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE2_EN		0x00000400
930 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE3_EN		0x00000800
931 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE0_EN		0x00001000
932 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE1_EN		0x00002000
933 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE2_EN		0x00004000
934 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE3_EN		0x00008000
935 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_CLK_LANE_EN			0x00010000
936 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_CLK_LANE_EN			0x00020000
938 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL(uint32_t i0) { return 0x000c2014 + 0x8*i0; }  in REG_MDP4_LCDC_LVDS_MUX_CTL()
940 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(uint32_t i0) { return 0x000c2014 + 0x8*i0;…  in REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0()
941 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__MASK		0x000000ff
942 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT		0
947 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__MASK		0x0000ff00
953 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__MASK		0x00ff0000
959 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__MASK		0xff000000
966 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(uint32_t i0) { return 0x000c2018 + 0x8*i0;…  in REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4()
967 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__MASK		0x000000ff
968 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT		0
973 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__MASK		0x0000ff00
979 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__MASK		0x00ff0000
986 #define REG_MDP4_LCDC_LVDS_PHY_RESET				0x000c2034
988 #define REG_MDP4_LVDS_PHY_PLL_CTRL_0				0x000c3000
990 #define REG_MDP4_LVDS_PHY_PLL_CTRL_1				0x000c3004
992 #define REG_MDP4_LVDS_PHY_PLL_CTRL_2				0x000c3008
994 #define REG_MDP4_LVDS_PHY_PLL_CTRL_3				0x000c300c
996 #define REG_MDP4_LVDS_PHY_PLL_CTRL_5				0x000c3014
998 #define REG_MDP4_LVDS_PHY_PLL_CTRL_6				0x000c3018
1000 #define REG_MDP4_LVDS_PHY_PLL_CTRL_7				0x000c301c
1002 #define REG_MDP4_LVDS_PHY_PLL_CTRL_8				0x000c3020
1004 #define REG_MDP4_LVDS_PHY_PLL_CTRL_9				0x000c3024
1006 #define REG_MDP4_LVDS_PHY_PLL_LOCKED				0x000c3080
1008 #define REG_MDP4_LVDS_PHY_CFG2					0x000c3108
1010 #define REG_MDP4_LVDS_PHY_CFG0					0x000c3100
1011 #define MDP4_LVDS_PHY_CFG0_SERIALIZATION_ENBLE			0x00000010
1012 #define MDP4_LVDS_PHY_CFG0_CHANNEL0				0x00000040
1013 #define MDP4_LVDS_PHY_CFG0_CHANNEL1				0x00000080
1015 #define REG_MDP4_DTV						0x000d0000
1017 #define REG_MDP4_DTV_ENABLE					0x000d0000
1019 #define REG_MDP4_DTV_HSYNC_CTRL					0x000d0004
1020 #define MDP4_DTV_HSYNC_CTRL_PULSEW__MASK			0x0000ffff
1021 #define MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT			0
1026 #define MDP4_DTV_HSYNC_CTRL_PERIOD__MASK			0xffff0000
1033 #define REG_MDP4_DTV_VSYNC_PERIOD				0x000d0008
1035 #define REG_MDP4_DTV_VSYNC_LEN					0x000d000c
1037 #define REG_MDP4_DTV_DISPLAY_HCTRL				0x000d0018
1038 #define MDP4_DTV_DISPLAY_HCTRL_START__MASK			0x0000ffff
1039 #define MDP4_DTV_DISPLAY_HCTRL_START__SHIFT			0
1044 #define MDP4_DTV_DISPLAY_HCTRL_END__MASK			0xffff0000
1051 #define REG_MDP4_DTV_DISPLAY_VSTART				0x000d001c
1053 #define REG_MDP4_DTV_DISPLAY_VEND				0x000d0020
1055 #define REG_MDP4_DTV_ACTIVE_HCTL				0x000d002c
1056 #define MDP4_DTV_ACTIVE_HCTL_START__MASK			0x00007fff
1057 #define MDP4_DTV_ACTIVE_HCTL_START__SHIFT			0
1062 #define MDP4_DTV_ACTIVE_HCTL_END__MASK				0x7fff0000
1068 #define MDP4_DTV_ACTIVE_HCTL_ACTIVE_START_X			0x80000000
1070 #define REG_MDP4_DTV_ACTIVE_VSTART				0x000d0030
1072 #define REG_MDP4_DTV_ACTIVE_VEND				0x000d0038
1074 #define REG_MDP4_DTV_BORDER_CLR					0x000d0040
1076 #define REG_MDP4_DTV_UNDERFLOW_CLR				0x000d0044
1077 #define MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK			0x00ffffff
1078 #define MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT			0
1083 #define MDP4_DTV_UNDERFLOW_CLR_ENABLE_RECOVERY			0x80000000
1085 #define REG_MDP4_DTV_HSYNC_SKEW					0x000d0048
1087 #define REG_MDP4_DTV_TEST_CNTL					0x000d004c
1089 #define REG_MDP4_DTV_CTRL_POLARITY				0x000d0050
1090 #define MDP4_DTV_CTRL_POLARITY_HSYNC_LOW			0x00000001
1091 #define MDP4_DTV_CTRL_POLARITY_VSYNC_LOW			0x00000002
1092 #define MDP4_DTV_CTRL_POLARITY_DATA_EN_LOW			0x00000004
1094 #define REG_MDP4_DSI						0x000e0000
1096 #define REG_MDP4_DSI_ENABLE					0x000e0000
1098 #define REG_MDP4_DSI_HSYNC_CTRL					0x000e0004
1099 #define MDP4_DSI_HSYNC_CTRL_PULSEW__MASK			0x0000ffff
1100 #define MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT			0
1105 #define MDP4_DSI_HSYNC_CTRL_PERIOD__MASK			0xffff0000
1112 #define REG_MDP4_DSI_VSYNC_PERIOD				0x000e0008
1114 #define REG_MDP4_DSI_VSYNC_LEN					0x000e000c
1116 #define REG_MDP4_DSI_DISPLAY_HCTRL				0x000e0010
1117 #define MDP4_DSI_DISPLAY_HCTRL_START__MASK			0x0000ffff
1118 #define MDP4_DSI_DISPLAY_HCTRL_START__SHIFT			0
1123 #define MDP4_DSI_DISPLAY_HCTRL_END__MASK			0xffff0000
1130 #define REG_MDP4_DSI_DISPLAY_VSTART				0x000e0014
1132 #define REG_MDP4_DSI_DISPLAY_VEND				0x000e0018
1134 #define REG_MDP4_DSI_ACTIVE_HCTL				0x000e001c
1135 #define MDP4_DSI_ACTIVE_HCTL_START__MASK			0x00007fff
1136 #define MDP4_DSI_ACTIVE_HCTL_START__SHIFT			0
1141 #define MDP4_DSI_ACTIVE_HCTL_END__MASK				0x7fff0000
1147 #define MDP4_DSI_ACTIVE_HCTL_ACTIVE_START_X			0x80000000
1149 #define REG_MDP4_DSI_ACTIVE_VSTART				0x000e0020
1151 #define REG_MDP4_DSI_ACTIVE_VEND				0x000e0024
1153 #define REG_MDP4_DSI_BORDER_CLR					0x000e0028
1155 #define REG_MDP4_DSI_UNDERFLOW_CLR				0x000e002c
1156 #define MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK			0x00ffffff
1157 #define MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT			0
1162 #define MDP4_DSI_UNDERFLOW_CLR_ENABLE_RECOVERY			0x80000000
1164 #define REG_MDP4_DSI_HSYNC_SKEW					0x000e0030
1166 #define REG_MDP4_DSI_TEST_CNTL					0x000e0034
1168 #define REG_MDP4_DSI_CTRL_POLARITY				0x000e0038
1169 #define MDP4_DSI_CTRL_POLARITY_HSYNC_LOW			0x00000001
1170 #define MDP4_DSI_CTRL_POLARITY_VSYNC_LOW			0x00000002
1171 #define MDP4_DSI_CTRL_POLARITY_DATA_EN_LOW			0x00000004