Lines Matching full:intr

253 	/* BEGIN MAP_RANGE: 0-31, INTR */
773 static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr, in dpu_hw_intr_dispatch_irq() argument
784 if (!intr) in dpu_hw_intr_dispatch_irq()
792 spin_lock_irqsave(&intr->irq_lock, irq_flags); in dpu_hw_intr_dispatch_irq()
794 irq_status = intr->save_irq_status[reg_idx]; in dpu_hw_intr_dispatch_irq()
803 if (!test_bit(reg_idx, &intr->irq_mask) || in dpu_hw_intr_dispatch_irq()
808 * Search through matching intr status from irq map. in dpu_hw_intr_dispatch_irq()
827 intr->ops.clear_intr_status_nolock( in dpu_hw_intr_dispatch_irq()
828 intr, irq_idx); in dpu_hw_intr_dispatch_irq()
838 spin_unlock_irqrestore(&intr->irq_lock, irq_flags); in dpu_hw_intr_dispatch_irq()
841 static int dpu_hw_intr_enable_irq(struct dpu_hw_intr *intr, int irq_idx) in dpu_hw_intr_enable_irq() argument
850 if (!intr) in dpu_hw_intr_enable_irq()
862 spin_lock_irqsave(&intr->irq_lock, irq_flags); in dpu_hw_intr_enable_irq()
863 cache_irq_mask = intr->cache_irq_mask[reg_idx]; in dpu_hw_intr_enable_irq()
871 DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask); in dpu_hw_intr_enable_irq()
873 DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask); in dpu_hw_intr_enable_irq()
878 intr->cache_irq_mask[reg_idx] = cache_irq_mask; in dpu_hw_intr_enable_irq()
880 spin_unlock_irqrestore(&intr->irq_lock, irq_flags); in dpu_hw_intr_enable_irq()
888 static int dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx) in dpu_hw_intr_disable_irq_nolock() argument
896 if (!intr) in dpu_hw_intr_disable_irq_nolock()
908 cache_irq_mask = intr->cache_irq_mask[reg_idx]; in dpu_hw_intr_disable_irq_nolock()
916 DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask); in dpu_hw_intr_disable_irq_nolock()
918 DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask); in dpu_hw_intr_disable_irq_nolock()
923 intr->cache_irq_mask[reg_idx] = cache_irq_mask; in dpu_hw_intr_disable_irq_nolock()
932 static int dpu_hw_intr_disable_irq(struct dpu_hw_intr *intr, int irq_idx) in dpu_hw_intr_disable_irq() argument
936 if (!intr) in dpu_hw_intr_disable_irq()
944 spin_lock_irqsave(&intr->irq_lock, irq_flags); in dpu_hw_intr_disable_irq()
945 dpu_hw_intr_disable_irq_nolock(intr, irq_idx); in dpu_hw_intr_disable_irq()
946 spin_unlock_irqrestore(&intr->irq_lock, irq_flags); in dpu_hw_intr_disable_irq()
951 static int dpu_hw_intr_clear_irqs(struct dpu_hw_intr *intr) in dpu_hw_intr_clear_irqs() argument
955 if (!intr) in dpu_hw_intr_clear_irqs()
959 if (test_bit(i, &intr->irq_mask)) in dpu_hw_intr_clear_irqs()
960 DPU_REG_WRITE(&intr->hw, in dpu_hw_intr_clear_irqs()
970 static int dpu_hw_intr_disable_irqs(struct dpu_hw_intr *intr) in dpu_hw_intr_disable_irqs() argument
974 if (!intr) in dpu_hw_intr_disable_irqs()
978 if (test_bit(i, &intr->irq_mask)) in dpu_hw_intr_disable_irqs()
979 DPU_REG_WRITE(&intr->hw, in dpu_hw_intr_disable_irqs()
989 static void dpu_hw_intr_get_interrupt_statuses(struct dpu_hw_intr *intr) in dpu_hw_intr_get_interrupt_statuses() argument
995 if (!intr) in dpu_hw_intr_get_interrupt_statuses()
998 spin_lock_irqsave(&intr->irq_lock, irq_flags); in dpu_hw_intr_get_interrupt_statuses()
1000 if (!test_bit(i, &intr->irq_mask)) in dpu_hw_intr_get_interrupt_statuses()
1004 intr->save_irq_status[i] = DPU_REG_READ(&intr->hw, in dpu_hw_intr_get_interrupt_statuses()
1008 enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[i].en_off); in dpu_hw_intr_get_interrupt_statuses()
1011 if (intr->save_irq_status[i]) in dpu_hw_intr_get_interrupt_statuses()
1012 DPU_REG_WRITE(&intr->hw, dpu_intr_set[i].clr_off, in dpu_hw_intr_get_interrupt_statuses()
1013 intr->save_irq_status[i]); in dpu_hw_intr_get_interrupt_statuses()
1016 intr->save_irq_status[i] &= enable_mask; in dpu_hw_intr_get_interrupt_statuses()
1022 spin_unlock_irqrestore(&intr->irq_lock, irq_flags); in dpu_hw_intr_get_interrupt_statuses()
1025 static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr, in dpu_hw_intr_clear_intr_status_nolock() argument
1030 if (!intr) in dpu_hw_intr_clear_intr_status_nolock()
1034 DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, in dpu_hw_intr_clear_intr_status_nolock()
1041 static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr, in dpu_hw_intr_get_interrupt_status() argument
1048 if (!intr) in dpu_hw_intr_get_interrupt_status()
1056 spin_lock_irqsave(&intr->irq_lock, irq_flags); in dpu_hw_intr_get_interrupt_status()
1059 intr_status = DPU_REG_READ(&intr->hw, in dpu_hw_intr_get_interrupt_status()
1063 DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, in dpu_hw_intr_get_interrupt_status()
1069 spin_unlock_irqrestore(&intr->irq_lock, irq_flags); in dpu_hw_intr_get_interrupt_status()
1098 struct dpu_hw_intr *intr; in dpu_hw_intr_init() local
1103 intr = kzalloc(sizeof(*intr), GFP_KERNEL); in dpu_hw_intr_init()
1104 if (!intr) in dpu_hw_intr_init()
1107 __intr_offset(m, addr, &intr->hw); in dpu_hw_intr_init()
1108 __setup_intr_ops(&intr->ops); in dpu_hw_intr_init()
1110 intr->irq_idx_tbl_size = ARRAY_SIZE(dpu_irq_map); in dpu_hw_intr_init()
1112 intr->cache_irq_mask = kcalloc(ARRAY_SIZE(dpu_intr_set), sizeof(u32), in dpu_hw_intr_init()
1114 if (intr->cache_irq_mask == NULL) { in dpu_hw_intr_init()
1115 kfree(intr); in dpu_hw_intr_init()
1119 intr->save_irq_status = kcalloc(ARRAY_SIZE(dpu_intr_set), sizeof(u32), in dpu_hw_intr_init()
1121 if (intr->save_irq_status == NULL) { in dpu_hw_intr_init()
1122 kfree(intr->cache_irq_mask); in dpu_hw_intr_init()
1123 kfree(intr); in dpu_hw_intr_init()
1127 intr->irq_mask = m->mdss_irqs; in dpu_hw_intr_init()
1128 spin_lock_init(&intr->irq_lock); in dpu_hw_intr_init()
1130 return intr; in dpu_hw_intr_init()
1133 void dpu_hw_intr_destroy(struct dpu_hw_intr *intr) in dpu_hw_intr_destroy() argument
1135 if (intr) { in dpu_hw_intr_destroy()
1136 kfree(intr->cache_irq_mask); in dpu_hw_intr_destroy()
1137 kfree(intr->save_irq_status); in dpu_hw_intr_destroy()
1138 kfree(intr); in dpu_hw_intr_destroy()